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3N190, 3N191
MONOLITHIC DUAL
P-CHANNEL ENHANCEMENT MODE
Linear Integrated Systems
MOSFET
FEATURES
VERY HIGH INPUT IMPEDANCE
HIGH GATE BREAKDOWN
ULTRA LOW LEAKAGE
LOW CAPACITANCE
MONOLITHIC DUAL
ABSOLUTE MAXIMUM RATINGS (NOTE 1)
= 25°C unless otherwise noted)
(T
A
Drain-Source or Drain-Gate Voltage -40V (
Transient G-S Voltages (NOTES 2 and 3) ±125V
Gate-Gate Voltage ±80V
Drain Current (NOTE 2) 50mA
Storage Temperature -65°C to +200°C
Power Dissipation 375 mW
ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise specified)
SYMBOL CHARACTERISTICS MIN. MAX. UNITS CONDITIONS
I
GSSF
I
GSSR
I
DSS
I
SDS
I
D(on)
r
DS(on)
V
DS(on)
g
fs
g
os
C
iss
C
rss
C
oss
MATCHING CHARACTERISTICS 3N190
Y
fs1/Yfs2
V
GS1-2
V
GS1-2
∆T
NOTES: 1. These ratings are limiting values above which the serviceability of the semiconductor may be impaired.
Gate Forward Leakage Current -- 10 pA VGS= 40 V
Gate Reverse Leakage Current -- -10 pA VGS= -40 V
Drain to Source Leakage Current -- -200 VDS= -15 V
Source-Drain Current -- -400 VSD= -20V VDB= 0
ON Drain Current -5 -30 mA VDS= -15 V VGS= -10 V
Drain-Source ON Resistance -- 300 ohms VDS= -20 V ID= -100µA
Drain-Source ON Voltage -- 2.0 V VGS= -10 V ID= 10 mA
Forward Transconductance 1500 4000 µsVDS= -15V ID= 10mA
Output Admittance -- 300 f=1KHz
Input Capacitance -- 4.5 pF f=1MHz
Reverse Transfer Capacitance -- 1.0
Output Capacitance Input Shorted -- 3.0
Forward Transconductance Ratio 0.85 1.0 VDS= -15V ID= -500 µA f=1KHz
Offset Voltage -- 100 mV VDS= -15V ID= -500 µA
Drift vs. Temperature -- 100 µV/°CVDS= -15V ID= -500 µA
2. Per Transistor.
3. Approximately doubles for every 10°C increase in T
NOTE 2)
LIMITS
DIE MAP
Bottom View
TA= -55°C to +125°C
.
A
TO-99
Linear Integrated Systems
310 S. Milpitas Blvd., Milpitas, CA 95035 TEL: (408) 263-8401 • FAX: (408) 263-7280
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MATCHING CHARACTERISTICS 3N165
LIMITS
SYMBOL CHARACTERISTICS MIN. MAX. UNITS CONDITIONS
Y
fs1/Yfs2
V
GS1-2
∆V
GS1-2
Forward Transconductance Ratio 0.90 1.0 VDS= -15 V ID= -500 µA f=1kHz
Gate Source Threshold Voltage Differential -- 100 mV VDS= -15 V ID= -500 µA
/∆T Gate Source Threshold Voltage Differential -- 100 µV/°CVDS= -15 V IA= -500 µA
Change with Temperature TA= -55°C to = +25°C
TYPICAL SWITCHING WAVEFORM
V
DD
10%
10%
50
R
1
t
R
2
V
OUT
on
Ω
INPUT PULSE
Rise Time 2ns
Pulse Width 200ns
Switching Times Test Circuit
t
r
90%
10%
10%
t
off
SAMPLING SCOPE
≤
≤
≥
T 0.2ns
r
C 2pF
≤
IN
≥
R 10M
IN
Switching Times Test Circuit
NOTES:
1. MOS field-effect transistors have extremely high input resistance and can be damaged by the accumulation of excess static
charge. To avoid possible damage to the device while wiring, testing, or in actual operation, follow these procedures:
To avoid the build-up of static charge, the leads of the devices should remain shorted together with a metal ring except when
being tested or used. Avoid unnecessary handling. Pick up devices by the case instead of the leads. Do not insert or remove
devices from circuits with the power on, as transient voltages may cause permanant damage to the devices.
2. Per transistor.
3. Devices must mot be tested at ±125V more than once, nor for longer than 300ms.
4. For design reference only, not 100% tested.
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress
ratings only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Linear Integrated Systems
310 S. Milpitas Blvd., Milpitas, CA 95035 TEL: (408) 263-8401 • FAX: (408) 263-7280
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