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3N170, 3N171
N-CHANNEL ENHANCEMENT MODE
Linear Integrated Systems
MOSFET
FEATURES
VERY HIGH INPUT IMPEDANCE
LOW SWITCHING VOLTAGES
LOW DRAIN-SOURCE RESISTANCE
LOW REVERSE TRANSFER CAPACITANCE
ABSOLUTE MAXIMUM RATINGS (NOTE 1)
= 25°C unless otherwise noted)
(T
A
Drain-Gate Voltage ±35V
Drain-Source Voltage 25V
Gate-Gate Voltage ±35V
Drain Current 30mA
Storage Temperature -65°C to +200°C
Operating Temperature -55°C to +125°C
Power Dissipation 300 mW
ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise specified)
LIMITS
SYMBOL CHARACTERISTICS MIN. MAX. UNITS CONDITIONS
I
GSS
BV
DSS
V
GS(th)
I
DSS
r
DS(on)
I
D(on)
V
DS(on)
|Yfs| Forward Transfer Admittance 1000 -- µsVDS= -10V ID= 2.0mA f=1KHz
C
rss
C
iss
C
d(sub)
td
(on)
t
r
td
(off)
t
f
Gate-Body Leakage Current -- 10 pA VGS= -35 V VDS= 0
Drain-Source Breakdown Voltage 25 -- VGS= 0 ID= 10 mA
Threshold Voltage 3N170 1.0 2.0 V
3N171 1.5 3.0 VDS= -10V ID= 10 µA
Zero Gate Voltage Drain Current -- 10 nA VDS= -10 V VGS= 0
Drain-Source ON Resistance -- 200 ohms VGS= -10 V ID= 0 f=1KHz
ON Drain Current 10 -- mA VGS= -10 V VDS= -10 V
Drain-Source ON Voltage -- 2.0 V VGS= -10 V ID= 10 mA
Reverse Transfer Capacitance -- 1.3 VGS= 0 VDS= 0 f=1MHz
Input Capacitance -- 5.0 pF VGS= 0 VDS= -10V f=1MHz
Drain Substrate Capacitance -- 5.0 V
Turn-On Delay Time -- 3.0 VDD= -10V I
Rise Time -- 10 V
Turn-Off Delay Time -- 3.0 ns RG= 50Ω
Fall Time -- 15
DIE MAP
=-10V f=1MHz
D(SUB)
= -10V V
GS(on)
D(on)
GS(off)
TO-72
Bottom View
= 10mA
= of=1KHz
NOTES: 1. These ratings are limiting values above which the serviceability of the semiconductor may be impaired.
Linear Integrated Systems
4042 Clipper Ct., Fremont, CA 94538 TEL: (510) 490-9160 • FAX: (510) 353-0261
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MATCHING CHARACTERISTICS 3N165
LIMITS
SYMBOL CHARACTERISTICS MIN. MAX. UNITS CONDITIONS
Y
fs1/Yfs2
V
GS1-2
∆V
GS1-2
Forward Transconductance Ratio 0.90 1.0 VDS= -15 V ID= -500 µA f=1kHz
Gate Source Threshold Voltage Differential -- 100 mV VDS= -15 V ID= -500 µA
/∆T Gate Source Threshold Voltage Differential -- 100 µV/°CVDS= -15 V IA= -500 µA
Change with Temperature TA= -55°C to = +25°C
TYPICAL SWITCHING WAVEFORM
V
DD
10%
10%
50
R
1
t
R
2
V
OUT
on
Ω
INPUT PULSE
Rise Time 2ns
Pulse Width 200ns
Switching Times Test Circuit
t
r
90%
10%
10%
t
off
SAMPLING SCOPE
≤
≤
≥
T 0.2ns
r
C 2pF
≤
IN
≥
R 10M
IN
Switching Times Test Circuit
NOTES:
1. MOS field-effect transistors have extremely high input resistance and can be damaged by the accumulation of excess static
charge. To avoid possible damage to the device while wiring, testing, or in actual operation, follow these procedures:
To avoid the build-up of static charge, the leads of the devices should remain shorted together with a metal ring except when
being tested or used. Avoid unnecessary handling. Pick up devices by the case instead of the leads. Do not insert or remove
devices from circuits with the power on, as transient voltages may cause permanant damage to the devices.
2. Per transistor.
3. Devices must mot be tested at ±125V more than once, nor for longer than 300ms.
4. For design reference only, not 100% tested.
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress
ratings only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Linear Integrated Systems
4042 Clipper Ct., Fremont, CA 94538 TEL: (510) 490-9160 • FAX: (510) 353-0261
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