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3N165, 3N166
MONOLITHIC DUAL P-CHANNEL
Linear Integrated Systems
FEATURES
VERY HIGH INPUT IMPEDANCE
HIGH GATE BREAKDOWN
ULTRA LOW LEAKAGE
LOW CAPACITANCE
ABSOLUTE MAXIMUM RATINGS (NOTE 1)
= 25°C unless otherwise noted)
(T
A
Drain-Source or Drain-Gate Voltage (
3N165 40 V
3N166 30 V
Transient G-S Voltage (NOTE 3) ±125 V
Gate-Gate Voltage ±80 V
Drain Current (NOTE 2) 50 mA
Storage Temperature -65°C to +200°C
Operating Temperature -55°C to +150°C
Lead Temperature (Soldering, 10 sec.) +300°C
Power Dissipation (One Side) 300 mW
Total Derating above 25°C 4.2 mW/°C
NOTE 2)
ENHANCEMENT MODE
7
1
3
4
8
Device Schematic
5
MOSFET
C
G2
G1
D2
D1
S
TO-99
Bottom View
ELECTRICAL CHARACTERISTICS (TA=25°C and VBS=0 unless otherwise specified)
LIMITS
SYMBOL CHARACTERISTICS MIN. MAX. UNITS CONDITIONS
I
GSSR
I
GSSF
Gate Reverse Leakage Current -- 10 VGS= 40 V
Gate Forward Leakage Current -- -10 VGS= -40 V
-- -25 pA TA=+125°C
I
DSS
I
SDS
I
D(on)
V
GS(th)
V
GS(th)
r
DS(on)
g
fs
g
os
C
iss
C
rss
C
oss
R
E(Yfs
Drain to Source Leakage Current -- -200 VDS= -20 V
Source to Drain Leakage Current -- -400 VSD= -20 V VDB= 0
On Drain Current -5 -30 mA VDS= -15 V VGS= -10 V
Gate Source Threshold Voltage -2 -5 V VDS= -15 V ID= -10 µA
Gate Source Threshold Voltage -2 -5 V VDS= V
GS
ID= -10 µA
Drain Source ON Resistance -- 300 ohms VGS= -20 V ID= -100 µA
Forward Transconductance 1500 3000 µsVDS= -15V ID= -10mA f=1kHz
Output Admittance -- 300 µs
Input Capacitance -- 3.0
Reverse Transfer Capacitance -- 0.7 pF VDS= -15V ID= -10mA f=1MHz
Output Capacitance -- 3.0 (NOTE 4)
) Common Source Forward Transconductance 1200 -- µsVDS= -15V ID= -10mA f=100MHz
(
NOTE 4)
Linear Integrated Systems
4042 Clipper Ct., Fremont, CA 94538 TEL: (510) 490-9160 • FAX: (510) 353-0261
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MATCHING CHARACTERISTICS 3N165
LIMITS
SYMBOL CHARACTERISTICS MIN. MAX. UNITS CONDITIONS
Y
fs1/Yfs2
V
GS1-2
∆V
GS1-2
Forward Transconductance Ratio 0.90 1.0 VDS= -15 V ID= -500 µA f=1kHz
Gate Source Threshold Voltage Differential -- 100 mV VDS= -15 V ID= -500 µA
/∆T Gate Source Threshold Voltage Differential -- 100 µV/°CVDS= -15 V IA= -500 µA
Change with Temperature TA= -55°C to = +25°C
TYPICAL SWITCHING WAVEFORM
V
DD
10%
10%
50
R
1
t
R
2
V
OUT
on
Ω
INPUT PULSE
Rise Time 2ns
Pulse Width 200ns
Switching Times Test Circuit
t
r
90%
10%
10%
t
off
SAMPLING SCOPE
≤
≤
≥
T 0.2ns
r
C 2pF
≤
IN
≥
R 10M
IN
Switching Times Test Circuit
NOTES:
1. MOS field-effect transistors have extremely high input resistance and can be damaged by the accumulation of excess static
charge. To avoid possible damage to the device while wiring, testing, or in actual operation, follow these procedures:
To avoid the build-up of static charge, the leads of the devices should remain shorted together with a metal ring except when
being tested or used. Avoid unnecessary handling. Pick up devices by the case instead of the leads. Do not insert or remove
devices from circuits with the power on, as transient voltages may cause permanant damage to the devices.
2. Per transistor.
3. Devices must mot be tested at ±125V more than once, nor for longer than 300ms.
4. For design reference only, not 100% tested.
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress
ratings only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Linear Integrated Systems
4042 Clipper Ct., Fremont, CA 94538 TEL: (510) 490-9160 • FAX: (510) 353-0261
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