Datasheet 3D7010S-90, 3D7010S-80, 3D7010S-500, 3D7010S-400, 3D7010S-300 Datasheet (DADD)

3D7010

MONOLITHIC 10-TAP

1

16

IN

VDD

data



3

FIXED DELAY LINE
(SERIES 3D7010)

FEATURES

• All-silicon, low-power CMOS technology*

• TTL/CMOS compatible inputs and outputs

• Vapor phase, IR and wave solderable

• Auto-insertable (DIP package)

• Low ground bounce noise

• Leading- and trailing-edge accuracy

• Delay range: 8 through 500ns

• Delay tolerance: 5% or 2ns

• Temperature stability: ±3% typical (0C-70C)

• Vdd stability: ±2% typical (4.75V-5.25V)

• Minimum input pulse width: 20% of total

delay

FUNCTIONAL DESCRIPTION

The 3D7010 10-Tap Delay Line product family consists of fixed-delay
CMOS integrated circuits. Each package contains a single delay line,
tapped and buffered at 10 points spaced uniformly in time. Tap-to-tap
(incremental) delay values can range from 8ns through 50ns. The input
is reproduced at the outputs without inversion, shifted in time as per the
user-specified dash number. The 3D7010 is TTL- and CMOS­compatible, capable of driving ten 74LS-type loads, and features both
rising- and falling-edge accuracy.

The all-CMOS 3D7010 integrated circuit has been designed as a
reliable, economic alternative to hybrid TTL fixed delay lines. It is
offered in a standard 14-pin auto-insertable DIP and a space saving
surface mount 16-pin SOIC.

IN

1

N/C

O2
O4
O6
O8

GND

(For mechanical data, see Case Dimensions document)

2
3
4
5
6
7

3D7010 DIP
3D7010G Gull-Wing

(300 Mil)

delay
devices, inc.

PACKAGES

VDD

14

O1

13

O3

12

2

O5

11

O7

10

O9

9

O10

8

PIN DESCRIPTIONS

IN Delay Line Input
O1 Tap 1 Output (10%)
O2 Tap 2 Output (20%)
O3 Tap 3 Output (30%)
O4 Tap 4 Output (40%)
O5 Tap 5 Output (50%)
O6 Tap 6 Output (60%)
O7 Tap 7 Output (70%)
O8 Tap 8 Output (80%)
O9 Tap 9 Output (90%)
O10 Tap 10 Output (100%)
VCC +5 Volts
GND Ground

N/C
N/C

O2
O4
O6
O8

GND

3
4
5
6
7
8

3D7010S
(300 Mil)

SOIC

15

N/C

14

O1

13

O3

12

O5

11

O7

10

O9

9

O10

TABLE 1: PART NUMBER SPECIFICATIONS

PART NUMBER TOLERANCES INPUT RESTRICTIONS

DIP-14

3D7010

3D7010G

-80 -80

-90 -90

-100 -100

-150 -150

-200 -200

-250 -250

-300 -300

-400 -400

-500 -500

NOTE: Any dash number between 80 and 500 not shown is also available. 1996 Data Delay Devices

*PATENTED

SOIC-16

3D7010S

TOTAL
DELAY

(ns)

80 ± 4.0 8.0 ± 1.5

90 ± 4.5 9.0 ± 1.7
100 ± 5.0 10.0 ± 2.0
150 ± 7.5 15.0 ± 2.0

200 ± 10.0 20.0 ± 2.5
250 ± 12.5 25.0 ± 2.5
300 ± 15.0 30.0 ± 3.0
400 ± 20.0 40.0 ± 4.0
500 ± 25.0 50.0 ± 5.0

TAP-TO-TAP

DELAY

(ns)

Max Operating

Frequency

4.17 MHz 31.2 MHz 120.0 ns 16.0 ns

3.70 MHz 27.8 MHz 135.0 ns 18.0 ns

3.33 MHz 25.0 MHz 150.0 ns 20.0 ns

2.22 MHz 16.7 MHz 225.0 ns 30.0 ns

1.67 MHz 12.5 MHz 300.0 ns 40.0 ns

1.33 MHz 10.0 MHz 375.0 ns 50.0 ns

1.11 MHz 8.33 MHz 450.0 ns 60.0 ns

0.83 MHz 6.25 MHz 600.0 ns 80.0 ns

0.67 MHz 5.00 MHz 750.0 ns 100.0 ns

Absolute Max

Oper. Freq.

Min Operating

Pulse Width

Absolute Min

Oper. P.W.

Doc #96004 DATA DELAY DEVICES, INC. 1

12/2/96 3 Mt. Prospect Ave. Clifton, NJ 07013

3D7010

APPLICATION NOTES

OPERATIONAL DESCRIPTION

The 3D7010 ten-tap delay line architecture is
shown in Figure 1. The delay line is composed
of a number of delay cells connected in series.
Each delay cell produces at its output a replica of
the signal present at its input, shifted in time.
The delay cells are matched and share the same
compensation signals, which minimizes tap-to­tap delay deviations over temperature and
supply voltage variations.

INPUT SIGNAL CHARACTERISTICS

The Frequency and/or Pulse Width (high or low)
of operation may adversely impact the specified
delay accuracy of the particular device. The
reasons for the dependency of the output delay
accuracy on the input signal characteristics are
varied and complex. Therefore a Maximum and
an Absolute Maximum operating input
frequency and a Minimum and an Absolute
Minimum operating pulse width have been
specified.

OPERATING FREQUENCY

The Absolute Maximum Operating Frequency
specification, tabulated in Table 1, determines
the highest frequency of the delay line input
signal that can be reproduced, shifted in time at
the device output, with acceptable duty cycle
distortion.

The Maximum Operating Frequency
specification determines the highest frequency of
the delay line input signal for which the output
delay accuracy is guaranteed.

To guarantee the Table 1 delay accuracy for
input frequencies higher than the Maximum
Operating Frequency, the 3D7010 must be
tested at the user operating frequency.
Therefore, to facilitate production and device
identification, the part number will include a
custom reference designator identifying the
intended frequency of operation. The
programmed delay accuracy of the device is
guaranteed, therefore, only at the user specified
input frequency. Small input frequency variation
about the selected frequency will only marginally
impact the programmed delay accuracy, if at all.

Nevertheless, it is strongly recommended
that the engineering staff at DATA DELAY
DEVICES be consulted.

OPERATING PULSE WIDTH

The Absolute Minimum Operating Pulse
Width (high or low) specification, tabulated in
Table 1, determines the smallest Pulse Width of

the delay line input signal that can be
reproduced, shifted in time at the device output,
with acceptable pulse width distortion.

The Minimum Operating Pulse Width (high or
low) specification determines the smallest Pulse
Width of the delay line input signal for which the
output delay accuracy tabulated in Table 1 is
guaranteed.

To guarantee the Table 1 delay accuracy for
input pulse width smaller than the Minimum
Operating Pulse Width, the 3D7010 must be
tested at the user operating pulse width.
Therefore, to facilitate production and device
identification, the part number will include a

O1IN O2 O3 O4

10% 10% 10% 10% 10% 10% 10% 10% 10% 10%

VDD

Figure 1: 3D7010 Functional Diagram

O5 O6 O7 O8 O9 O10

Temp & VDD

Compensation

GND

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3D7010

APPLICATION NOTES (CONT’D)

custom reference designator identifying the

intended frequency and duty cycle of operation.
The programmed delay accuracy of the device is
guaranteed, therefore, only for the user specified
input characteristics. Small input pulse width
variation about the selected pulse width will only
marginally impact the programmed delay
accuracy, if at all. Nevertheless, it is strongly

recommended that the engineering staff at
DATA DELAY DEVICES be consulted.

POWER SUPPLY AND
TEMPERATURE CONSIDERATIONS

The delay of CMOS integrated circuits is strongly
dependent on power supply and temperature.
The monolithic 3D7010 programmable delay line

DEVICE SPECIFICATIONS

TABLE 2: ABSOLUTE MAXIMUM RATINGS

utilizes novel and innovative compensation
circuitry to minimize the delay variations induced
by fluctuations in power supply and/or
temperature.

The thermal coefficient is reduced to 600
PPM/C, which is equivalent to a variation , over
the 0C-70C operating range, of ±±3% from the
room-temperature delay settings. The power
supply coefficient is reduced, over the 4.75V-

5.25V operating range, to ±±2% of the delay
settings at the nominal 5.0VDC power supply. It

is essential that the power supply pin be
adequately bypassed and filtered. In
addition, the power bus should be of as low
an impedance construction as possible.
Power planes are preferred.

PARAMETER SYMBOL MIN MAX UNITS NOTES

DC Supply Voltage V
Input Pin Voltage V
Input Pin Current I
Storage Temperature T
Lead Temperature T

DD

IN

IN
STRG
LEAD

-0.3 7.0 V

-0.3 VDD+0.3 V

-1.0 1.0 mA 25C

-55 150 C
300 C 10 sec

TABLE 3: DC ELECTRICAL CHARACTERISTICS

(0C to 70C, 4.75V to 5.25V)

PARAMETER SYMBOL MIN MAX UNITS NOTES

Static Supply Current* I
High Level Input Voltage V
Low Level Input Voltage V
High Level Input Current I
Low Level Input Current I
High Level Output Current I

Low Level Output Current I
Output Rise & Fall Time TR & T

*IDD(Dynamic) = 10 * CLD * VDD * F Input Capacitance = 10 pf typical
where: CLD = Average capacitance load/tap (pf) Output Load Capacitance (CLD) = 25 pf max

F = Input frequency (GHz)

DD

OH

OL

IH

IL
IH
IL

2.0 V

-4.0 mA VDD = 4.75V

4.0 mA VDD = 4.75V

F

15 mA

0.8 V
10

-250

µA
µA

VIH = V

VIL = 0V
VOH = 2.4V
VOL = 0.4V

2 ns CLD = 5 pf

DD

Doc #96004 DATA DELAY DEVICES, INC. 3

12/2/96 3 Mt. Prospect Ave. Clifton, NJ 07013

3D7010

SILICON DELAY LINE AUTOMATED TESTING

Test

OUT1

OUT2

OUT4

OUT3

OUT

TRIGINREF

TRIG

PRINTER

IN

OUT5

OUT6

OUT8

OUT7

OUT10

OUT9

0.6V

0.6V

1.5V

1.5V

2.4V

2.4V

1.5V

1.5V

TEST CONDITIONS

INPUT: OUTPUT:
Ambient Temperature: 25oC ± 3oC R
Supply Voltage (Vcc): 5.0V ± 0.1V C
Input Pulse: High = 3.0V ± 0.1V Threshold: 1.5V (Rising & Falling)

Low = 0.0V ± 0.1V

Source Impedance: 50Ω Max.
Rise/Fall Time: 3.0 ns Max. (measured

between 0.6V and 2.4V )

Pulse Width: PWIN = 1.25 x Total Delay
Period: PERIN = 2.5 x Total Delay

NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.

COMPUTER

SYSTEM

: 10KΩ ± 10%

load

: 5pf ± 10%

load

Device
Under

10KΩ

470Ω

Digital
Scope

5pf

PULSE

GENERATOR

INPUT
SIGNAL

OUTPUT
SIGNAL

t

RISE

DEVICE UNDER

TEST (DUT)

Figure 2: Test Setup

PW

IN

V

IH

t

PLH

PER

V

OH

DIGITAL SCOPE/

TIME INTERVAL COUNTER

IN

t

FALL

V

IL

t

PHL

V

OL

Figure 3: Timing Diagram

Doc #96004 DATA DELAY DEVICES, INC. 4

12/2/96 Tel: [phone] Fax: [phone] http://www.datadelay.com