3D3701
MONOLITHIC GATED
DELAY LINE OSCILLATOR
(SERIES 3D3701)
FEATURES
• All-silicon, low-power CMOS technology
• Vapor phase, IR and wave solderable
• Auto-insertable (DIP pkg.)
• Frequency range: 0.3MHz through 100MHz
• Frequency tolerance: 0.5% typical
• Temperature stability: ±1.5% typical (-40C to 85C)
• Vdd stability: ±0.5% typical (3.0V to 3.6V)
• 14-pin DIP available as drop-in replacements for
hybrid delay line oscillators
O1
NC
NC
GND
3D3701Z-xx SOIC-8
For mechanical dimensions, click here.
For package marking details, click here.
1
2
3
4
FUNCTIONAL DESCRIPTION
The 3D3701 Delay Line Oscillator product family consists of fixedfrequency CMOS integrated circuit oscillators. Each package contains a
single oscillator, which is gated and can therefore be synchronized to an
external signal. The device frequency can range from 0.3MHz through
100MHz. The 3D3701 has two outputs that are in phase when the
oscillator is running. The 3D3701 is offered in a standard 14-pin autoinsertable DIP and a space saving surface mount 8-pin SOIC package.
PACKAGES
VDD
8
NC
7
O2
6
EN
5
O1
1
NC
2
NC
3
NC
4
NC
5
NC
6
GND
3D3701-xx DIP-14
3D3701K-xx NC pins removed
7
PIN DESCRIPTIONS
EN Oscillator Enable
O1 Oscillator Output 1
O2 Oscillator Output 2
VDD +3.3 Volts
GND Ground
14
13
12
11
10
VDD
NC
NC
NC
O2
NC
9
EN
8
TABLE 1: PART NUMBER SPECIFICATIONS
NUMBER
-0.3
-0.4
-0.5
-0.75
-1
-2
-2.5
-3
-4
-5
-7.5
-10
-20
-25
-30
-40
-50
-75
NOTE: Any dash number between 0.3 and 100 not shown is also available as standard. 2006 Data Delay Devices
Doc #06026 DATA DELAY DEVICES, INC. 1
-100
OUTPUT FREQUENCY (MHz) DASH
25C
Vdd=3.3V
0.3 ± 0.002 0.3 ± 0.008
0.4 ± 0.002 0.4 ± 0.010
0.5 ± 0.003 0.5 ± 0.013
0.75 ± 0.004 0.75 ± 0.019
1.0 ± 0.005 1.0 ± 0.025
2.0 ± 0.010 2.0 ± 0.050
2.5 ± 0.013 2.5 ± 0.063
3.0 ± 0.015 3.0 ± 0.075
4.0 ± 0.020 4.0 ± 0.100
5.0 ± 0.025 5.0 ± 0.125
7.5 ± 0.038 7.5 ± 0.188
10.0 ± 0.05 10.0 ± 0.25
20.0 ± 0.10 20.0 ± 0.50
25.0 ± 0.13 25.0 ± 0.63
30.0 ± 0.15 30.0 ± 0.75
40.0 ± 0.20 40.0 ± 1.00
50.0 ± 0.25 50.0 ± 1.50
75.0 ± 0.38 75.0 ± 5.25
100.0 ± 0.50 100.0 ± 12.0
-40C to 85C
3.0V<Vdd<3.6V
12/5/2006 3 Mt. Prospect Ave. Clifton, NJ 07013
3D3701
APPLICATION NOTES
OPERATIONAL DESCRIPTION
The 3D3701 delay line oscillator architecture is
shown in Figure 1. The internal delay line is
composed of a number of delay cells connected
in series and is compensated for thermal and
supply voltage variations. A low-going edge on
the EN input starts the oscillator, with the O2
output responding immediately. The O1 output is
VDD
GND
Temp & Vdd
Compensation
Delay Line
delayed by ½ cycle. The response of the output
when the oscillator is disabled depends on the
status of O2 when the EN signal goes high, as
shown in Figure 2. If O2 is low, it will remain low,
and the final pulse on O1 will be ½ of the period.
If O2 is high, it will go low as soon as EN goes
high, and the final pulse on both outputs will have
a width smaller than ½ the period.
O1
O2
EN
Figure 1: 3D3701 Functional Diagram
EN
6ns typ
O2
O1
EN
6ns typ 6ns typ
O2
O1
Figure 2: 3D3701 Timing Diagrams
Doc #06026 DATA DELAY DEVICES, INC. 2
12/5/2006 Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
3D3701
APPLICATION NOTES (CONT’D)
POWER SUPPLY AND
TEMPERATURE CONSIDERATIONS
The delay of CMOS integrated circuits is strongly
dependent on power supply and temperature.
The monolithic 3D3701 oscillator utilizes novel
and innovative compensation circuitry to
minimize the frequency variations induced by
fluctuations in power supply and/or temperature.
The thermal coefficient is reduced to 250 PPM/C,
which is equivalent to a variation, over the -40C
to 85C operating range, of ±1.5% from the room-
temperature frequency setting. The power supply
coefficient is reduced, over the 3.0V to 3.6V
operating range, to ±0.5% of the frequency
setting at the nominal 3.3VDC power supply.
These specifications hold for the lower
frequencies only. For higher dash numbers, the
variations will be slightly greater, as noted in
Table 1. It is essential that the power supply
pin be adequately bypassed and filtered. In
addition, the power bus should be of as low
an impedance construction as possible.
Power planes are preferred.
DEVICE SPECIFICATIONS
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL MIN MAX UNITS NOTES
DC Supply Voltage VDD -0.3 7.0 V
Input Pin Voltage VIN -0.3 VDD+0.3 V
Input Pin Current IIN -1.0 1.0 mA 25C
Storage Temperature T
Lead Temperature T
-55 150 C
STRG
300 C 10 sec
LEAD
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 3.0V to 3.6V)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Static Supply Current* IDD 3.5 5.5 mA
High Level Input Voltage VIH 2.0 V
Low Level Input Voltage VIL 0.8 V
High Level Input Current IIH 1.0
Low Level Input Current IIL 1.0
High Level Output
Current
Low Level Output Current IOL 4.0 15.0 mA VDD = 3.0V
Output Rise & Fall Time TR & TF 2.0 2.5 ns CLD = 5 pf
*IDD(Dynamic) = 2 * CLD * VDD * F Input Capacitance = 10 pf typical
where: C
F = Device frequency (GHz)
= Average capacitance load/output (pf) Output Load Capacitance (CLD) = 25 pf max
LD
IOH -20.0 -4.0 mA VDD = 3.0V
µA
µA
VIH = VDD
VIL = 0V
VOH = 2.4V
VOL = 0.4V
Doc #06026 DATA DELAY DEVICES, INC. 3
12/5/2006 3 Mt. Prospect Ave. Clifton, NJ 07013
3D3701
SILICON DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT: OUTPUT:
Ambient Temperature: 25oC ± 3oC R
Supply Voltage (Vcc): 3.3V ± 0.1V C
Input Pulse: High = 3.0V ± 0.1V Threshold: 1.5V (Rising & Falling)
Low = 0.0V ± 0.1V
Source Impedance: 50Ω Max.
Rise/Fall Time: 3.0 ns Max. (measured
between 0.6V and 2.4V )
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
: 10KΩ ± 10%
load
: 5pf ± 10%
load
Device
Under
10K
Ω
Test
470
Digital
Scope
5pf
Ω
PULSE
GENERATOR
OUT
TRIG
COMPUTER
SYSTEM
DEVICE UNDER
EN
TEST (DUT)
O1
O2
Figure 3: Test Setup
PRINTER
REF
IN
TRIG
FREQUENCY/
TIME INTERVAL COUNTER
EN
2.4V
1.5V
0.6V
t
ENB
t
FALL
V
IL
1/f
OSC
t
RISE
V
IH
2.4V
1.5V
0.6V
t
DIS
1.5V 1.5V 1.5V
O2
Figure 4: Timing Diagram
Doc #06026 DATA DELAY DEVICES, INC. 4
12/5/2006 Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
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