Datasheet 33C408RTFS30, 33C408RTFS25, 33C408RTFI30, 33C408RTFI25, 33C408RTFI20 Datasheet (MAXWELL)

1

Memory

All data sheets are subject to change without notice

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4 Megabit (512K x 8-Bit)

33C408

©2001 Maxwell Technologies

All rights reserved.

CMOS SRAM

12.13.01 Rev712.20.01 Rev 7

1000561

FEATURES:

•RAD-PAK® Technology radiation-hardened against natural
space radiation

• 524,288 x 8 bit organization

· Total dose hardness:

- > 100 krad (Si), depending upon space mission

• Excellent Single Event Effect

· - SEL

TH

: > 68 MeV/mg/cm

2

· - SEUTH: = 3 MeV/mg/cm

2

- SEU saturated cross section: 6E-9 cm2/bit

• Package:

- 32-Pin R

AD-PAK® flat pack

- 32-Pin Non-R

AD-PAK® flat pack

• Fast access time:

- 20, 25, 30 ns maximum times available

• Single 5V +

10% power supply

• Fully static operation

- No clock or refresh required

• Three state outputs

• TTL compatible inputs and outputs

• Low power:

- Standby: 60 mA (TTL); 10 mA (CMOS)

- Operation: 180 mA (20 ns); 170 mA (25 ns);

160 mA (30 ns)

DESCRIPTION:

Maxwell Technologies’ 33C408 high-density 4 Megabit SRAM
microcircuit features a greater than 100 krad (Si) total dose
tolerance, depending upon space mission. Using Maxwell’s
radiation-hardened R

AD-PAK® packaging technology, the

33C408 realizes a high density, high performance, and low
power consumption. Its fully static design eliminates the need
for external clocks, while the CMOS circuitry reduces power
consumption and provides higher reliability. The 33C408 is
equipped with eight common input/output lines, chip select
and output enable, allowing for greater system flexibility and
eliminating bus contention. The 33C408 features the same
advanced 512K x 8-bit SRAM, high-speed, and low-power
demand as the commercial counterpart.

Maxwell Technologies' patented R

AD-PAK packaging technol-

ogy incorporates radiation shielding in the microcircuit pack­age. It eliminates the need for box shielding while providing
the required radiation shielding for a lifetime in orbit or space
mission. In a GEO orbit, R

AD-PAK provides greater than 100

krad (Si) radiation dose tolerance. This product is available
with screening up to Class S.

Logic Diagram

Memory

2

All data sheets are subject to change without notice

©2001 Maxwell Technologies

All rights reserved.

4 Megabit (512K x 8-Bit) CMOS SRAM

33C408

12.13.01 Rev712.20.01 Rev 7

1000561

TABLE 1. PINOUT DESCRIPTION

PIN SYMBOL DESCRIPTION

12-5, 27, 26, 23, 25, 4,

28, 3, 31, 2, 30, 1

A0-A18 Address Inputs

29 WE

Write Enable

22 CS

Chip Select

24 OE

Output Enable

13-15, 17-21 I/O 1-I/O 8 Data Inputs/Outputs

32 V

CC

Power (+5.0V)

16 V

SS

Ground

TABLE 2. 33C408 ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL MIN MAX UNIT

Voltage on VCC supply relative to V

SS

V

CC

-0.5 7.0 V

Voltage on any pin relative to V

SS

VIN, V

OUT

-0.5 V

CC

+0.5 V

Power Dissipation P

D

-- 1.0 W

Storage Temperature T

S

-65 +150

°

C

Operating Temperature T

A

-55 +125

°

C

TABLE 3. DELTA LIMITS

PARAMETER VARIATION

I

CC1

±10% of stated vaule in Table 6

I

CC2

±10% of stated vaule in Table 6

I

CC3

±10% of stated vaule in Table 6

I

LI

±10% of stated vaule in Table 6

Memory

3

All data sheets are subject to change without notice

©2001 Maxwell Technologies

All rights reserved.

4 Megabit (512K x 8-Bit) CMOS SRAM

33C408

12.13.01 Rev712.20.01 Rev 7

1000561

TABLE 4. 33C408 RECOMMENDED OPERATING CONDITIONS

(VCC = 5.0 + 10%, TA = -55 TO +125 °C, UNLESS OTHERWISE NOTED)

P

ARAMETER SYMBOL MIN MAX UNIT

Supply Voltage V

CC

4.5 5.5 V

Ground V

SS

00V

Input High Voltage

1

1. V

IH

(max) = VCC +2.0V ac (pulse width < 10 ns) for I < 20 mA

V

IH

2.2 VCC+0.5 V

Input Low Voltage

2

2. V

IL

(min) = -2.0V ac(pulse width < 10 ns) for I < 20 mA

V

IL

-0.5 0.8 V

Thermal Impedance

Θ

JC

-- 1.21 °C/W

TABLE 5. 33C408 CAPACITANCE

(f = 1.0 MHZ, dV = 3.0V, TA = 25 °C)

P

ARAMETER SYMBOL

TEST

C

ONDITIONS

MAX UNITS

Input Capacitance

1

CS1 - CS4,
OE

, WE

I/O0-7, I/O8-15, I/O16-23, I/O24-31

1. Guaranteed by design.

C

IN

V

IN

= 0 V

7

28

7

pF

Input / Output Capacitance

1

C

OUT

V

I/O

= 0 V 8 pF

TABLE 6. 33C408 DC ELECTRICAL CHARACTERISTICS

(VCC = 5V + 10%, TA = -55 TO +125 °C, UNLESS OTHERWISE SPECIFIED)

P

ARAMETER SYMBOL CONDITION MIN MAX UNIT

Input Leakage Current I

LI

VIN = VSS to V

CC

-2 2 µA

Output Leakage Current I

LO

CS=VIH or OE=VIH or WE=VIL,
V

OUT

=VSS to V

CC

-2 2 µA

Output Low Voltage V

OL

IOL = 8mA -- 0.4 V

Output High Voltage V

OH

IOH = -4mA 2.4 -- V

Operating Current

-20

-25

-30

I

CC

Min cycle, 100% Duty, CS=VIL, I

OUT

=0mA,

V

IN

= VIH or V

IL

--

--

--

180
170
160

mA

Standby Power Supply Cur­rent

I

SB

CS = VIH, Min Cycle -- 60 mA

Input Capacitance

1

C

IN

VIN = 0V, f = 1MHz, TA = 25 °C -- 7 pF

Memory

4

All data sheets are subject to change without notice

©2001 Maxwell Technologies

All rights reserved.

4 Megabit (512K x 8-Bit) CMOS SRAM

33C408

12.13.01 Rev712.20.01 Rev 7

1000561

Output Capacitance

1

C

I/O

V

I/O

= 0V -- 8 pF

1. Guaranteed by design.

TABLE 7. 33C408 AC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 + 10%, TA = -55 TO +125 °C, UNLESS OTHERWISE NOTED)

P

ARAMETER MIN TYP MAX UNITS

Input Pulse Level 0.0 -- 3.0 V

Output Timing Measurement Reference Level -- -- 1.5 V

Input Rise/Fall Time -- -- 3.0 ns

Input Timing Measurement Reference Level -- -- 1.5 V

TABLE 8. 33C408 AC CHARACTERISTICS FOR READ CYCLE

(VCC = 5V + 10%, TA = -55 TO +125 °C, UNLESS OTHERWISE SPECIFIED)

P

ARAMETER SYMBOL MIN TYP MAX UNIT

Read Cycle Time

-20

-25

-30

t

RC

20
25
30

--

--

--

--

--

--

ns

Address Access Time

-20

-25

-30

t

AA

--

--

--

--

--

--

20
25
30

ns

Chip Select Access Time

-20

-25

-30

t

CO

--

--

--

--

--

--

20
25
30

ns

Output Enable to Output Valid

-20

-25

-30

t

OE

--

--

--

--

--

--

10
12
14

ns

Chip Enable to Output in Low-Z

-20

-25

-30

t

LZ

--

--

--

3
3
3

--

--

--

ns

Output Enable to Output in Low-Z

-20

-25

-30

t

OLZ

--

--

--

0
0
0

--

--

--

ns

TABLE 6. 33C408 DC ELECTRICAL CHARACTERISTICS

(VCC = 5V + 10%, TA = -55 TO +125 °C, UNLESS OTHERWISE SPECIFIED)

P

ARAMETER SYMBOL CONDITION MIN MAX UNIT

Memory

5

All data sheets are subject to change without notice

©2001 Maxwell Technologies

All rights reserved.

4 Megabit (512K x 8-Bit) CMOS SRAM

33C408

12.13.01 Rev712.20.01 Rev 7

1000561

Chip Deselect to Output in High-Z

-20

-25

-30

t

HZ

--

--

--

5
6
8

--

--

--

ns

Output Disable to Output in High-Z

-20

-25

-30

t

OHZ

--

--

--

5
6
8

--

--

--

ns

Output Hold from Address Change

-20

-25

-30

t

OH

3
5
6

--

--

--

--

--

--

ns

Chip Select to Power Up Time

-20

-25

-30

t

PU

--

--

--

0
0
0

--

--

--

ns

Chip Select to Power Down Time

-20

-25

-30

t

PD

--

--

--

10
15
20

--

--

--

ns

TABLE 9. 33C408 FUNCTIONAL DESCRIPTION

CS WE OE MODE I/O PIN SUPPLY CURRENT

HX

1

1. X = don’t care.

X

1

Not Select High-Z ISB, I

SB1

L H H Output Disable High-Z I

CC

L H L Read D

OUT

I

CC

LLX1Write D

IN

I

CC

TABLE 10. 33C408 AC CHARACTERISTICS FOR WRITE CYCLE

(VCC = 5V + 10%, TA = -55 TO +125 °C, UNLESS OTHERWISE SPECIFIED)

P

ARAMETER SYMBOL MIN TYP MAX UNIT

Write Cycle Time

-20

-25

-30

t

WC

20

25
30

--

--

--

--

--

--

ns

TABLE 8. 33C408 AC CHARACTERISTICS FOR READ CYCLE

(VCC = 5V + 10%, TA = -55 TO +125 °C, UNLESS OTHERWISE SPECIFIED)

P

ARAMETER SYMBOL MIN TYP MAX UNIT

Memory

6

All data sheets are subject to change without notice

©2001 Maxwell Technologies

All rights reserved.

4 Megabit (512K x 8-Bit) CMOS SRAM

33C408

12.13.01 Rev712.20.01 Rev 7

1000561

Chip Select to End of Write

-20

-25

-30

t

CW

14
15
17

--

--

--

--

--

--

ns

Address Setup Time

-20

-25

-30

t

AS

0
0
0

--

--

--

--

--

--

ns

Address Valid to End of Write

-20

-25

-30

t

AW

14
15
17

--

--

--

--

--

--

ns

Write Pulse Width (OE

High)

-20

-25

-30

t

WP

14
15
17

--

--

--

--

--

--

ns

Write Recovery Time

-20

-25

-30

t

WR

0
0
0

--

--

--

--

--

--

ns

Write to Output in High-Z

-20

-25

-30

t

WHZ

--

--

--

5
5
6

--

--

--

ns

Write Pulse Width (OE

Low)

-20

-25

-30

t

WP1

--

--

--

22
24
26

--

--

--

ns

Data to Write Time Overlap

-20

-25

-30

t

DW

9
10
11

--

--

--

--

--

--

ns

End Write to Output Low-Z

-20

-25

-30

t

OW

--

--

--

6
7
8

--

--

--

ns

Data Hold from Write Time

-20

-25

-30

t

DH

0

0

0

--

--

--

--

--

--

ns

TABLE 10. 33C408 AC CHARACTERISTICS FOR WRITE CYCLE

(VCC = 5V + 10%, TA = -55 TO +125 °C, UNLESS OTHERWISE SPECIFIED)

P

ARAMETER SYMBOL MIN TYP MAX UNIT

Memory

7

All data sheets are subject to change without notice

©2001 Maxwell Technologies

All rights reserved.

4 Megabit (512K x 8-Bit) CMOS SRAM

33C408

12.13.01 Rev712.20.01 Rev 7

1000561

FIGURE 1. AC TEST LOADS

FIGURE 2. TIMING WAVEFORM OF READ CYCLE(1)

Memory

8

All data sheets are subject to change without notice

©2001 Maxwell Technologies

All rights reserved.

4 Megabit (512K x 8-Bit) CMOS SRAM

33C408

12.13.01 Rev712.20.01 Rev 7

1000561

FIGURE 3. TIMING WAVEFORM OF READ CYCLE (2)

Read Cycle Notes:

1.WE is high for read cycle.
2

. All read cycle timing is referenced form the last valid address to the first transition address.

3

.tHZ and t

OHZ

are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or

V

OL

levels.

4

. At any given temperature and voltage condition, t

HZ(max)

is less than t

LZ(min)

both for a given device and from device to device.

5

. Transition is measured + 200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.

6

. Device is continuously selected with CS = V

IL.

7. Address valid prior to coincident with CS transition low.
8

. For common I/O applications, minimization or elimination of bus contention condition is necessary during read and write cycle.

FIGURE 4. TIMING WAVEFORM OF WRITE CYCLE(1)

Memory

9

All data sheets are subject to change without notice

©2001 Maxwell Technologies

All rights reserved.

4 Megabit (512K x 8-Bit) CMOS SRAM

33C408

12.13.01 Rev712.20.01 Rev 7

1000561

FIGURE 5. TIMING WAVEFORM OF WRITE CYCLE(2)

F

IGURE 6. TIMING WAVEFORM OF WRITE CYCLE (3)

WRITE CYCLE NOTE:

1. All write cycle timing is referenced from the last valid address to the first transition address.
2

. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going low and

WE

going low: A write ends at the earliest transition among CS going high and WE going high. tWP is measured from begin-

ning of write to the end of write.

3

.tCW is measured from the later of CS going low to end of write.

4

.tAS is measured from the address valid to the beginning of write.

5

.tWR is measured form the end of write to the address change. TWR applied in case a write ends as CS, or WR going high.

Memory

10

All data sheets are subject to change without notice

©2001 Maxwell Technologies

All rights reserved.

4 Megabit (512K x 8-Bit) CMOS SRAM

33C408

12.13.01 Rev712.20.01 Rev 7

1000561

6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite
phase of the output must not be applied because bus contention can occur.

7

. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write

cycle.

8

.IC CS goes low simultaneously with WE going low or after WE going low, the outputs remain high impedance state.

9

.D

OUT

is the read data of the new address.

10

. When CS is low: I/O pins are in the output state. The input signals in the opposite phase leading to the output should

not be applied.

Memory

11

All data sheets are subject to change without notice

©2001 Maxwell Technologies

All rights reserved.

4 Megabit (512K x 8-Bit) CMOS SRAM

33C408

12.13.01 Rev712.20.01 Rev 7

1000561

FIGURE 7. SRAM HEAVY ION CROSS SECTION

FIGURE 8. SRAM PROTON SEU CROSS SECTION STATIC

Memory

12

All data sheets are subject to change without notice

©2001 Maxwell Technologies

All rights reserved.

4 Megabit (512K x 8-Bit) CMOS SRAM

33C408

12.13.01 Rev712.20.01 Rev 7

1000561

F32-06

Note: All dimensions in inches

32 PIN RAD-PAK® FLAT PACKAGE

SYMBOL

DIMENSION

MIN NOM MAX

A 0.120 0.135 0.155

b 0.013 0.015 0.020

c 0.008 0.010 0.012

D -- 0.930 0.940

E 0.635 0.645 0.655

E1 -- -- 0.690

E2 0.550 0.565 --

E3 0.030 0.040 --

e 0.050 BSC

L 0.390 0.400 0.410

Q 0.026 0.098 --

S1 0.005 0.082 --

N32

Memory

13

All data sheets are subject to change without notice

©2001 Maxwell Technologies

All rights reserved.

4 Megabit (512K x 8-Bit) CMOS SRAM

33C408

12.13.01 Rev712.20.01 Rev 7

1000561

Important Notice:

These data sheets are created using the chip manufacturers published specifications. Maxwell Technologies verifies
functionality by testing key parameters either by 100% testing, sample testing or characterization.

The specifications presented within these data sheets represent the latest and most accurate information available to
date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no
responsibility for the use of this information.

Maxwell Technologies’ products are not authorized for use as critical components in life support devices or systems
without express written approval from Maxwell Technologies.

Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Tech­nologies. Maxwell Technologies’ liability shall be limited to replacement of defective parts.

Memory

14

All data sheets are subject to change without notice

©2001 Maxwell Technologies

All rights reserved.

4 Megabit (512K x 8-Bit) CMOS SRAM

33C408

12.13.01 Rev712.20.01 Rev 7

1000561

Product Ordering Options

Model Number

Feature

Option Details

33C408

XX

F X

-XX

Access Time

Screening Flow

Package

Radiation Feature

Base Product
Nomenclature

20 = 20 ns
25 = 25 ns
30 = 30 ns

Monolithic
S = Maxwell Class S
B = Maxwell Class B
E = Engineering (testing @ +25°C

)

I = Industrial (testing @ -55°C,
+25°C, +125°C)

F = Flat Pack

RP = R

AD-PAK® package

RT = Non-R

AD-PAK® package

4 Megabit CMOS SRAM