Datasheet 2SK3326 Datasheet (NEC)

DATA SHEET

MOS FIELD EFFECT TRANSISTOR

SWITCHING

N-CHANNEL POWER MOS FET

INDUSTRIAL USE

2SK3326

DESCRIPTION

The 2SK3326 is N-Channel DMOS FET device that features
a low gate charge and excellent switching characteristics, and
designed for high voltage applications such as switching power
supply, AC adapter.

FEATURES

• Low gate charge :
QG = 22 nC TYP. (VDD = 400 V, VGS = 10 V, ID = 10 A)

• Gate voltage rating : ±30 V

• Low on-state resistance :

DS(on)

R

= 0.85 Ω MAX. (VGS = 10 V, ID = 5.0 A)

• Avalanche capability ratings

• Isolated TO-220(MP-45F) package

ABSOLUTE MAXIMUM RATINGS (TA = 25°C)

Drain to Source Voltage (VGS = 0 V) V
Gate to Source Voltage (V

DS

= 0 V) V
Drain Current (DC) I
Drain Current (pulse)
Total Power Dissipation (T
Total Power Dissipation (T

Note1

C

= 25°C) P

A

= 25°C) P
Channel Temperature T
Storage Temperature T
Single Avalanche Current
Single Avalanche Energy

Note2

Note2

DSS

GSS(AC)

D(DC)

D(pulse)

I

ch

stg

AS

I

AS

E

T

T

–55 to +150 °C

ORDERING INFORMATION

PART NUMBER PACKAGE

2SK3326 Isolated TO-220

(Isolated TO-220)

500 V

±30 V
±10 A
±40 A

40 W

2.0 W

150 °C

10 A

10.7 mJ

Notes 1.

Document No. D14204EJ1V0DS00 (1st edition)
Date Published March 2000 NS CP(K)
Printed in Japan

PW ≤ 10

2.

Starting Tch = 25 °C, VDD = 150 V, RG = 25 Ω, VGS = 20 V → 0 V

µ

s, Duty Cycle ≤ 1 %

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.

©

2000

ELECTRICAL CHARACTERISTICS (TA = 25 °C)

CHARACTERISTICS SYMBOL TE ST CONDITIONS MIN. TYP. MAX. UNIT

2SK3326

Drain Leakage Current I
Gate to Source Leakage Current I
Gate to Source Cut-off Voltage V

DSS

VDS = 500 V, VGS = 0 V 100

GSS

VGS = ±30 V, VDS = 0 V

GS(off)VDS

= 10 V, ID = 1 mA 2.5 3.5 V

100 nA

±

Forward Transfer Admittance | yfs |VDS = 10 V, ID = 5.0 A 2.0 4.0 S
Drain to Source On-state Resi stance R
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Turn-on Delay Time t
Rise Time t
Turn-off Delay Time t
Fall Time t
Total Gate Charge Q
Gate to Source Charge Q
Gate to Drain Charge Q
Body Diode Forward Voltage V

Reverse Recovery Time t
Reverse Recovery Charge Q

DS(on)VGS

iss

oss

rss

d(on)

r

d(off)

f

G

GS

GD

F(S-D)IF

rr

rr

= 10 V, ID = 5.0 A 0.68 0.85

VDS = 10 V, VGS = 0 V, f = 1 MHz

VDD = 150 V, ID = 5.0 A, V

G

Ω,

R

L

= 60

R

= 10

VDD = 400 V, VGS = 10 V, ID = 10 A

= 10 A, VGS = 0 V1.0V

IF = 10 A, VGS = 0 V, di/dt = 50 A /

1200 pF

190 pF

10 pF

GS(on)

= 10 V,

Ω

21 ns
11 ns
40 ns

9.5 ns
22 nC

6.5 nC

7.5 nC

s

µ

0.5

2.6

A

µ

Ω

s

µ

C

µ

TEST CIRCUIT 1 AVALANCHE CAPABILITY

PG.

VGS = 20 → 0 V

V

G

R

DD

= 25 Ω

50 Ω

I

D

D.U.T.

I

AS

BV

DSS

V

DS

Starting T

L

DD

V

ch

TEST CIRCUIT 3 GATE CHARGE

D.U.T.

I

G

PG.

= 2 mA

50 Ω

R

L

V

DD

TEST CIRCUIT 2 SWITCHING TIME

D.U.T.

R

PG.

V

GS

0

τ

τ = 1 µs

Duty Cycle ≤ 1 %

G

V

L

R

V

Wave Form

V

DD

I

Wave Form

GS

GS

D

10 %

0

I

D

10 %10

0

t

d(on)

V

90

%

I

trt

t

on

GS(on)

D

d(off)tf

t

%

90

90

%

%

off

2

Data Sheet D14204EJ1V0DS00

TYPICAL CHARACTERISTICS(TA = 25 °C)

2SK3326

Figure1. DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA

100

80

60

40

20

dT - Percentage of Rated Power - %

020 80

40 60 100 120 140 160
T

c

- Case Temperature - ˚C

Figure3. FORWARD BIAS SAFE OPERATING AREA

100

I

D (pulse)

PW = 10 µs

Limited

I

D (DC)

10

1

- Drain Current - A

D

I

Tc = 25 ˚C
Single Pulse

0.1
1

V

= 10 V)

DS(on)

GS

R

(at V

Power Dissipation Limited

100 ms

10 100 1000

DS

- Drain to Source Voltage - V

100 µs

1ms

10 ms

Figure5. DRAIN CURRENT vs.
GATE TO SOURCE VOLTAGE

100

Pulsed

Figure2. TOTAL POWER DISSIPATION vs.
CASE TEMPERATURE

50

40

30

20

10

- Total Power Dissipation - W

T

P

20 40 60 80 100 120 140 160

0

c

- Case Temperature - ˚C

T

Figure4. DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE

20

Pulsed

10

ID - Drain Current - A

0

4 8 12 16

DS - Drain to Source Voltage - V

V

VGS = 20 V

10 V

8.0 V

VGS = 6.0 V

10

1

0.1

0.01

- Drain Current - A

D

I

0.001

0.0001
0

V

TA = –25 ˚C

25 ˚C
75 ˚C

125 ˚C

51015

GS

- Gate to Source Voltage - V

Data Sheet D14204EJ1V0DS00

3

Figure6. TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH

2SK3326

100

10

1

0.1

rth (t) - Transient Thermal Resistance - ˚C/W

0.01

0.0001 0.001 0.01 0.1 1 10 100 1000

Figure7. FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT

10

1

TA = –25 ˚C

25 ˚C
75 ˚C

0.1

125 ˚C

R

th(ch-A) = 62.5 ˚C/W

PW - Pulse Width - s

Figure8. DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE

2.0

1.0

Rth(ch-C) = 3.2 ˚C/W

Tc = 25 ˚C
Single Pulse

ID = 10 A

5.0 A

2.0 A

I - Forward Transfer Admittance - S

fs

Iy

0.01

0.01

110

ID - Drain Current - A

Figure9. DRAIN TO SOURCE ON-STATE
RESISTANCE vs. DRAIN CURRENT

3.0
Pulsed

2.0

1.0

- Drain to Source On-state Resistance - Ω

0

DS(on)

0.1 10

R

1

I

D

- Drain Current - A

VDS = 10 V
Pulsed

1000.1

100

- Drain to Source On-state Resistance - Ω

0.0

DS(on)

R

V

10 15 20

GS

- Gate to Source Voltage - V

Figure10. GATE TO SOURCE CUT-OFF VOLTAGE vs.
CHANNEL TEMPERATURE

4.0
V

DS

I

D

= 1 mA

3.0

2.0

1.0

- Gate to Source Cut-off Voltage - V

GS(off)

0.0

V

–50 0 50 100 150 200

Tch - Channel Temperature - ˚C

Pulsed

2505

= 10 V

4

Data Sheet D14204EJ1V0DS00

2SK3326

Figure11. DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE

3.0

2.0
ID = 10 A

I

D

1.0

- Drain to Source On-state Resistance - Ω

0.0

DS(on)

–50 0 50 100 150

R

T

ch

- Channel Temperature - ˚C

= 5.0 A

VGS = 10 V

Figure13. CAPACITANCE vs. DRAIN TO
SOURCE VOLTAGE

10000

C

iss

VGS = 0 V
f = 1.0 MHz

1000

C

oss

100

- Capacitance - pF

10

rss

, C

oss

, C

iss

C

1

C

rss

0.1
1 100 1000

10

DS

- Drain to Source Voltage - V

V

Figure12. SOURCE TO DRAIN DIODE
FORWARD VOLTAGE

100

10

VGS = 10 V

1

VGS = 0 V

0.1

- Diode Forward Current - A

SD

I

0.01

0.5

V

SD

- Source to Drain Voltage - V

1.00.0

Figure14. SWITCHING CHARACTERISTICS

1000

100

- Switching Time - ns

f

, t

10

d(off)

, t

r

, t

d(on)

t

1

0.1 100

110

D

- Drain Current - A

I

V
VGS = 10 V
RG = 10 Ω

DD

= 150 V

Pulsed

t

r

t

f

t

d(on)

t

d(off)

1.5

Figure15. REVERSE RECOVERY TIME vs.
DRAIN CURRENT

1000

di/dt = 50 A/µs

900

GS

= 0 V

V

800
700
600
500
400
300
200

- Reverse Recovery Time - ns

rr

100

t

0

0.1 10 100

1

IF - Drain Current - A

Figure16. DYNAMIC INPUT/OUTPUT CHARACTERISTICS

800
700
600
500
400

300
200

- Drain to Source Voltage - V

100

DS

V

0

Data Sheet D14204EJ1V0DS00

VDD = 400 V

250 V
100 V

V

DS

105202515

QG - Gate Charge - nC

ID = 10 A

V

GS

14
12
10
8
6

4

- Gate to Source Voltage - V

GS

2

V

0

5

2SK3326

Figure17. SINGLE AVALANCHE ENERGY vs
STARTING CHANNEL TEMPERATURE

16
14
12
10

EAS = 10.7 mJ

D(peak)

= I

I
RG = 25 Ω
VGS = 20 V → 0 V
VDD = 150 V

8
6
4

- Single Avalanche Energy - mJ

2

AS

E

0

25

50 75 100 125

Starting T

ch

- Starting Channel Temperature - ˚C

AS

150 175

Figure18. SINGLE AVALANCHE ENERGY vs
INDUCTIVE LOAD

100

RG = 25 Ω
VDD = 150 V
VGS = 20 V → 0 V
Starting Tch = 25 ˚C

IAS = 10 A

10

1

- Single Avalanche Energy - A

AS

I

0.1

10 µ

100 µ

L - Inductive Load - H

E

AS

= 10.7 mJ

1 m 10 m

6

Data Sheet D14204EJ1V0DS00

PACKAGE DRAWING (Unit: mm)

Isolated TO-220(MP-45F)

10.0±0.3

3.2±0.2

4.5±0.2

2SK3326

2.7±0.2

Remark

15.0±0.3

2.54

123

3±0.1

4±0.2

1.3±0.20.7±0.1

1.5±0.2

2.54

13.5 MIN. 12.0±0.2

2.5±0.1

0.65±0.1

1. Gate

2. Drain

3. Source

EQUIVALENT CIRCUIT

Drain

Body

Gate

Source

Diode

Strong electric field, when exposed to this device, cause destruction of the gate oxide and ultimately
degrade the device operation. Steps must be taken to stop generation of static electricity as much as
possible, and quickly dissipate it once, when it has occurred.

Data Sheet D14204EJ1V0DS00

7

2SK3326

• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.

• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.

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M7 98. 8