Drain to source voltageV
Gate to source voltageV
Drain currentI
Drain peak currentI
Drain peak currentI
Channel dissipationPch*
DSS
GSS
D
D(pulse)
DR
1
*
2
Channel temperatureTch150°C
Storage temperatureTstg–55 to +150°C
Notes: 1. PW ≤ 100 µs, duty cycle ≤ 10%
2. When using aluminium ceramic board (12.5 × 20 × 70 mm)
–60V
±20V
–1A
–2A
–1A
1W
2
Page 3
Electrical Characteristics (Ta = 25°C)
ItemSymbolMinTypMaxUnitTest conditions
Drain to source breakdown
V
(BR)DSS
voltage
Gate to source breakdown
V
(BR)GSS
voltage
Zero gate voltage drain current I
Gate to source leak currentI
Gate to source cutoff voltageV
Static drain to source on state
R
DSS
GSS
GS(off)
DS(on)
resistance
Static drain to source on state
R
DS(on)
resistance
Fowerd transfer admittance|yfs|0.61.0—SID = –0.5 A
Input capacitanceCiss—150—pFVDS = –10 V
Output capacitanceCoss—72—pFVGS = 0
Reverse transfer capacitanceCrss—24—pFf = 1 MHz
Turn-on delay timet
Rise timet
Turn-off delay timet
Fall timet
Body to drain diode forward
V
d(on)
r
d(off)
f
DF
voltage
Body to drain diode reverse
t
rr
recovery time
Note:1. Pulse Test
Marking is "UY".
–60——VID = –10 mA, VGS = 0
±20——VIG = ±100 µA, VDS = 0
——–50µAVDS = –50 V, VGS = 0
——±10µAVGS = ±16 V, VDS = 0
–0.5—–1.5VVDS = –10 V, ID = –1 mA
—0.851.2ΩID = –0.5 A
V
= –4 V*
GS
—1.11.9ΩID = –0.3 A
V
= –2.5 V*
GS
V
= –10 V
DS
1
1
—6 —nsVGS = –10 V, ID = –0.5 A
—9 —nsR
= 60 Ω
L
—50—ns
—35—ns
—–0.9—VIF = –1 A, VGS = 0
—100—nsIF = –1 A, VGS = 0
diF/dt = 50A/µs
2SJ450
3
Page 4
2SJ450
Power vs. Temperature Derating
2.0
Test Condition :
When using the aliminium Ceramic
board (12.5 x 20 x 70 mm)
1.5
1.0
0.5
Channel Dissipation Pch (W)
0
50100150200
Case Temperature Tc (°C)
Typical Output Characteristics
–10 V –6 V
–2.0
–4 V
–3 V
–1.6
D
–1.2
Pulse Test
–2.5 V
–10
–3
–1
D
–0.3
–0.1
Operation in
Drain Current I (A)
–0.03
this area is
limited by R
DS(on)
PW = 10 ms
DC Operation
Ta = 25 °C
Maximum Safe Operation Area
–0.01
0.10.3131030100
Drain to Source Voltage V (V)
Typical Transfer Characteristics
–2.0
V = –10 V
DS
Pulse Test
D
–1.6
–25°C
–1.2
Tc = 75°C
25°C
10 µs
100 µs
1 ms
DS
–0.8
Drain Current I (A)
–0.4
0
–2–4–6–8–10
Drain to Source Voltage V (V)
–2 V
V = –1.5 V
GS
DS
–0.8
Drain Current I (A)
–0.4
0
–1–2–3–4–5
Gate to Source Voltage V (V)
GS
4
Page 5
2SJ450
Drain to Source Saturation Voltage vs.
Gate to Source Voltage
–2.0
–1.6
DS(on)
–1.2
–0.8
–0.4
Pulse Test
I = –1.5 A
D
–1 A
–0.5 A
Drain to Source Voltage V (V)
0
–2
Gate to Source Voltage V (V)
–4
–6–8–10
GS
Static Drain to Source on State Resistance
vs. Temperature
10
Pulse Test
Ω
8
Static Drain to Source on State Resistance
vs. Drain Current
20
Ω
10
5
DS(on)
R ( )
2
V = –2.5 V
GS
1
0.5
0.2
Pulse Test
Drain to Source On State Resistance
–4 V
–0.1 –0.2–0.5–1–2
Drain Current I (A)
D
Forward Transfer Admittance vs.
Drain Current
10
3
Tc = –25 °C
–5
–10
DS(on)
R ( )
6
I = –1.5 A
D
4
V = –2.5 V
GS
2
–4 V
0
Static Drain to Source on State Resistance
–4004080120160
–0.5 A
–1.0 A
–0.5 A
1.5 A
–1.0 A
Case Temperature Tc (°C)
1
0.3
25 °C
75 °C
0.1
0.03
Forward Transfer Admittance |yfs| (S)
0.01
–0.01 –0.03 –0.1 –0.3
Drain Current I (A)
V = –10 V
DS
Pulse Test
–1
–3–10
D
5
Page 6
2SJ450
Body to Drain Diode Reverse
Recovery Time
1000
500
200
100
50
20
Reverse Recovery Time trr (ns)
10
–0.1
–0.2
di / dt = 50 A / µs
V = 0, Ta = 25 °C
GS
–0.5 –1–2–5–10
Reverse Drain Current I (A)
Dynamic Input Characteristics
DS
0
–20
V = –10 V
DD
–25 V
–50 V
DR
0
–4
Typical Capacitance vs.
Drain to Source Voltage
500
200
100
50
20
Capacitance C (pF)
10
V = 0
GS
f = 1 MHz
5
0–10–20–30–40–50
Drain to Source Voltage V (V)
Switching Characteristics
200
100
GS
50
t
d(off)
Ciss
Coss
Crss
DS
–40
–60
V
DS
V = –50 V
DD
V
GS
–25 V
–10 V
–80
Drain to Source Voltage V (V)
–100
I = –2 A
D
0
246810
Gate Charge Qg (nc)
–8
t
20
–12
–16
–20
10
Switching Time t (ns)
5
V = –10 V, V = –30 V
Gate to Source Voltage V (V)
2
duty < 1 %
–0.1 –0.2–0.5 –1–2–5–10
Drain Current I (A)
f
GS
t
r
t
d(on)
DD
D
6
Page 7
–2.0
–1.6
DR
2SJ450
Reverse Drain Current vs.
Source to Drain Voltage
Pulse Test
Vin Monitor
Vin
–10 V
50Ω
–1.2
–5 V
V = 0, 5 V
–0.8
GS
–0.4
Reverse Drain Current I (A)
0
–0.4–0.8–1.2–1.6–2.0
Source to Drain Voltage V (V)
Avalanche Test Circuit and Waveform
Vout
Monitor
D.U.T.
R
L
V
DD
= –30 V
Vin
Vout
SD
10%
10%
90%
90%
90%
10%
td(on)
tr
td(off)
t
f
7
Page 8
Unit: mm
0.53 Max
0.48 Max
4.5 ± 0.1
1.8 Max
1.5
1.5
3.0
1.5 ± 0.1
0.4
φ
1
0.44 Max
(1.5)
(2.5)
2.5 ± 0.1
4.25 Max
0.44 Max
(0.4)
(0.2)
0.8 Min
Hitachi Code
JEDEC
EIAJ
Weight
(reference value)
UPAK
—
Conforms
0.050 g
Page 9
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URLNorthAmerica : http:semiconductor.hitachi.com/
For further information write to:
Hitachi Semiconductor
(America) Inc.
179 East Tasman Drive,
San Jose,CA 95134
Tel: <1> (408) 433-1990
Fax: <1>(408) 433-0223
Europe: http://www.hitachi-eu.com/hel/ecg
Asia (Singapore): http://www.has.hitachi.com.sg/grp3/sicd/index.htm
Asia (Taiwan): http://www.hitachi.com.tw/E/Product/SICD_Frame.htm
Asia (HongKong): http://www.hitachi.com.hk/eng/bo/grp3/index.htm
Japan: http://www.hitachi.co.jp/Sicd/indx.htm
Hitachi Asia Ltd.
Taipei Branch Office
3F, Hung Kuo Building. No.167,
Tun-Hwa North Road, Taipei (105)
Tel: <886> (2) 2718-3666
Fax: <886> (2) 2718-8180
Copyright ' Hitachi, Ltd., 1999. All rights reserved. Printed in Japan.
Hitachi Asia (Hong Kong) Ltd.
Group III (Electronic Components)
7/F., North Tower, World Finance Centre,
Harbour City, Canton Road, Tsim Sha Tsui,
Kowloon, Hong Kong
Tel: <852> (2) 735 9218
Fax: <852> (2) 730 0281
Telex: 40815 HITEC HX
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