Designed primarily for full-wave ac control applications, such as
light dimmers, motor controls, heating controls and power supplies; or
wherever full-wave silicon gate controlled solid-state devices are
needed. Triac type thyristors switch from a blocking to a conducting
state for either polarity of applied anode voltage with positive or
negative gate triggering.
• Blocking Voltage to 800 Volts
• All Diffused and Glass Passivated Junctions for Greater Parameter
Uniformity and Stability
• Small, Rugged, Thermowatt Construction for Low Thermal
Resistance, High Heat Dissipation and Durability
• Gate Triggering Guaranteed in all Four Quadrants
• For 400 Hz Operation, Consult Factory
• 8 Ampere Devices Available as 2N6344 thru 2N6349
• Device Marking: Logo, Device Type, e.g., 2N6344A, Date Code
MAXIMUM RATINGS (T
RatingSymbolValueUnit
*Peak Repetitive Off−State Voltage(Note 1)
(Gate Open, T
Sine Wave 50 to 60 Hz, Gate Open)
*On−State RMS Current
(Full Cycle Sine Wave 50 to 60 Hz)
*Peak Non−repetitive Surge Current
(One Full Cycle, 60 Hz, T
Preceded and followed by rated current
Circuit Fusing Consideration (t = 8.3 ms)I2t59A2s
*Peak Gate Power (TC = +80°C,
Pulse Width = 2.0 µs)
*Average Gate Power
= +80°C, t = 8.3 ms)
(T
C
*Peak Gate Current
(Pulse Width = 2.0 µs; T
*Peak Gate Voltage
(Pulse Width = 2.0 µs; T
*Operating Junction Temperature RangeT
*Storage Temperature RangeT
*Indicates JEDEC Registered Data.
1. V
and V
DRM
voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.
= −40 to +110°C,
J
for all types can be applied on a continuous basis. Blocking
0.80.41.21.62.02.42.83.23.64.0 4.4
, MAXIMUM INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)
v
TM
1.0
0.5
(NORMALIZED)
0.2
0.1
0.05
0.02
Figure 5. On−State Characteristics
40
, PEAK SURGE CURRENT (AMP)
20
TSM
I
0
1.0
CYCLE
T
= 100°C
J
f = 60 Hz
Surge is preceded and followed by rated current
2.03.05.07.010
NUMBER OF CYCLES
Figure 7. Maximum Non−Repetitive
Surge Current
Z
= r(t) • R
θ
JC(t)
θ
JC
0.01
r(t), TRANSIENT THERMAL RESISTANCE
0.1
2.0 k10 k205.0 k1.0 k500200100505.02.01.00.50.2
t,TIME (ms)
Figure 8. Typical Thermal Response
http://onsemi.com
5
Page 6
2N6344A, 2N6348A, 2N6349A
PACKAGE DIMENSIONS
TO−220AB
CASE 221A−07
ISSUE AA
SEATING
−T−
PLANE
FB
Q
4
A
123
T
U
C
S
H
K
Z
L
V
R
J
G
D
N
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
DIM MINMAXMINMAX
A0.570 0.620 14.48 15.75
B 0.380 0.4059.66 10.28
C 0.160 0.1904.074.82
D 0.025 0.0350.640.88
F0.142 0.1473.613.73
G 0.095 0.1052.422.66
H0.110 0.1552.803.93
J0.014 0.0220.360.55
K 0.500 0.562 12.70 14.27
L0.045 0.0601.151.52
N 0.190 0.2104.835.33
Q 0.100 0.1202.543.04
R 0.0800.1102.042.79
S0.045 0.0551.151.39
T0.235 0.2555.976.47
U 0.000 0.0500.001.27
V0.045−−−1.15−−−
Z−−− 0.080−−−2.04
STYLE 4:
PIN 1. MAIN TERMINAL 1
2. MAIN TERMINAL 2
3. GATE
4. MAIN TERMINAL 2
MILLIMETERSINCHES
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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2N6344A/D
6
Page 7
This datasheet has been download from:
www.datasheetcatalog.com
Datasheets for electronics components.
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