Plastic medium−power complementary silicon transistors are
designed for general−purpose amplifier and low−speed switching
applications.
Features
• High DC Current Gain − h
• Collector−Emitter Sustaining Voltage − @ 100 mAdc −
V
CEO(sus)
= 100 Vdc (Min) − 2N6042, 2N6045
= 60 Vdc (Min) − 2N6040, 2N6043
• Low Collector−Emitter Saturation Voltage −
V
= 2.0 Vdc (Max) @ I
= 2.0 Vdc (Max) @ IC = 4.0 Adc − 2N6043,44
CE(sat)
• Monolithic Construction with Built−In Base−Emitter Shunt Resistors
• Epoxy Meets UL 94 V−0 @ 0.125 in
• ESD Ratings:Human Body Model, 3B > 8000 V
Machine Model, C > 400 V
• These Devices are Pb−Free and are RoHS Compliant*
MAXIMUM RATINGS (Note 1)
RatingSymbolValueUnit
Collector−Emitter Voltage2N6040
Collector−Base Voltage2N6040
Emitter−Base VoltageV
Collector CurrentContinuous
Base CurrentI
Total Power Dissipation @ TC = 25°C
Derate above 25°C
Operating and Storage Junction
Temperature Range
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Indicates JEDEC Registered Data.
= 2500 (Typ) @ IC = 4.0 Adc
FE
= 3.0 Adc − 2N6042, 2N6045
C
2N6043
2N6042
2N6045
2N6043
2N6042
2N6045
Peak
V
CEO
V
I
P
TJ, T
CB
EB
C
B
D
stg
60
100
60
100
5.0Vdc
8.0
16
120mAdc
75
0.60
–65 to +150°C
Vdc
Vdc
Adc
W
W/°C
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DARLINGTON, 8 AMPERES
COMPLEMENTARY SILICON
POWER TRANSISTORS
60 − 100 VOLTS, 75 WATTS
TO−220
CASE 221A
STYLE 1
MARKING DIAGRAM
2N604xG
AYWW
2N604x = Device Code
x = 0, 2, 3, or 5
A= Assembly Location
Y= Year
WW= Work Week
G= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Base−Emitter Saturation Voltage (IC = 8.0 Adc, IB = 80 mAdc)V
Base−Emitter On Voltage (IC = 4.0 Adc, VCE = 4.0 Vdc)V
h
V
CE(sat)
BE(sat)
BE(on)
FE
1000
1000
100
20.000
20,000
−
−
−
−
2.0
2.0
4.0
−4.5Vdc
−2.8Vdc
−
Vdc
DYNAMIC CHARACTERISTICS
Small Signal Current Gain (I
Output Capacitance2N6040/2N6042
(V
= 10 Vdc, IE = 0, f = 0.1 MHz)2N6043/2N6045
CB
Small−Signal Current Gain (IC = 3.0 Adc, VCE = 4.0 Vdc, f = 1.0 kHz)h
= 3.0 Adc, VCE = 4.0 Vdc, f = 1.0 MHz)|hfe|4.0−
C
C
ob
fe
−
−
300−−
300
200
pF
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
*Indicates JEDEC Registered Data.
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PNP − 2N6040, 2N6042, NPN − 2N6043, 2N6045
0
0
T
T
C
A
80
4.0
3.0
60
2.0
40
1.0
20
, POWER DISSIPATION (WATTS)
D
P
0
0
020406080100120160
RB & RC VARIED TO OBTAIN DESIRED CURRENT LEVELS
MUST BE FAST RECOVERY TYPE, eg:
D
1
1N5825 USED ABOVE I
MSD6100 USED BELOW I
V
2
approx
+8.0 V
0
V
1
approx
-12 V
, tf ≤ 10 ns
t
r
DUTY CYCLE = 1.0%
25 ms
≈ 100 mA
B
≈ 100 mA
B
R
B
D
1
51
for td and tr, D1 is disconnected
and V
= 0
2
For NPN test circuit reverse all polarities and D1.
≈ 8.0 k
+4.0 V
T
C
T
A
T, TEMPERATURE (°C)
Figure 1. Power Derating
5.0
t, TIME (s)μ
3.0
2.0
1.0
0.7
0.5
0.3
0.2
0.1
0.07
0.05
0.1
TUT
≈120
R
V
-30 V
C
CC
SCOPE
140
t
s
t
f
VCC = 30 V
= 250
I
C/IB
= I
I
B1
B2
TJ = 25°C
PNP
NPN
td @ V
BE(off)
= 0 V
0.2 0.30.5 0.7 1.02.0 3.01
IC, COLLECTOR CURRENT (AMP)
t
r
5.0 7.0
Figure 2. Switching Times Equivalent Circuit
1.0
0.7
D = 0.5
0.5
0.3
0.2
0.1
0.07
0.05
0.03
r(t), EFFECTIVE TRANSIENT
0.02
THERMAL RESISTANCE (NORMALIZED)
0.01
0.2
0.1
0.05
0.02
SINGLE PULSE
0.02 0.030.33.030300
0.01
0.01
0.050.10.20.51.02.05.0102050100200100
qJC(t) = r(t) q
JC
qJC = 1.67°C/W
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
T
- TC = P
J(pk)
1
(pk) qJC
t, TIME OR PULSE WIDTH (ms)
Figure 4. Thermal Response
Figure 3. Switching Times
P
(pk)
t
1
t
(t)
2
DUTY CYCLE, D = t1/t
2
500
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PNP − 2N6040, 2N6042, NPN − 2N6043, 2N6045
S
S
G
C
G
20
10
5.0
2.0
1.0
0.5
0.2
0.1
, COLLECTOR CURRENT (AMP)
C
I
0.05
0.02
1.0
TJ = 150°C
BONDING WIRE LIMITED
THERMALLY LIMITED @ T
(SINGLE PULSE)
SECOND BREAKDOWN LIMITED
CURVES APPLY BELOW RATED V
2.0 3.07.050100
VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS)
5.0
500 ms
1.0ms
5.0ms
102030
dc
= 25°C
C
CEO
2N6040, 2N6043
2N6045
100 ms
70
There are two limitations on the power handling ability of
a transistor: average junction temperature and second
breakdown. Safe operating area curves indicate I
C
− V
CE
limits of the transistor that must be observed for reliable
operation; i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.
The data of Figure 5 is based on T
= 150°C; TC is
J(pk)
variable depending on conditions. Second breakdown pulse
limits are valid for duty cycles to 10% provided T
< 150°C. T
may be calculated from the data in Figure 4.
J(pk)
J(pk)
At high case temperatures, thermal limitations will reduce
the power that can be handled to values less than the
limitations imposed by second breakdown.
Figure 5. Active−Region Safe Operating Area
10,000
5000
AIN
3000
2000
1000
URRENT
500
300
NAL
I
200
100
MALL-
50
,
fe
30
h
20
10
1.0
2.05.02050100010010
TC = 25°C
= 4.0 Vdc
V
CE
I
= 3.0 Adc
C
PNP
NPN
200500
f, FREQUENCY (kHz)
Figure 6. Small−Signal Current Gain
300
200
100
70
C, CAPACITANCE (pF)
50
30
C
ob
C
ib
PNP
NPN
0.51.02.0
VR, REVERSE VOLTAGE (VOLTS)
5.00.10.2
Figure 7. Capacitance
1020
TJ = 25°C
100
50
PNP
2N6040, 2N6042
20,000
10,000
7000
5000
TJ = 150°C
3000
2000
1000
, DC CURRENT GAIN
FE
700
h
500
300
200
0.1
VCE = 4.0 V
25°C
-55°C
0.2 0.30.51.02.010
IC, COLLECTOR CURRENT (AMP)
0.77.0
3.05.0
NPN
2N6043, 2N6045
20,000
10,000
7000
5000
TJ = 150°C
3000
2000
1000
, DC CURRENT GAIN
FE
700
h
500
300
200
0.1
VCE = 4.0 V
25°C
-55°C
0.2 0.30.51.02.0100.77.0
I
, COLLECTOR CURRENT (AMP)
C
3.05.0
Figure 8. DC Current Gain
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Page 5
PNP − 2N6040, 2N6042, NPN − 2N6043, 2N6045
, COLLECTOR-EMITTER VOLTAGE (VOLTS)
CE
V
3.0
2.6
2.2
1.8
1.4
1.0
3.0
2.5
2.0
IC = 2.0 A
0.3
0.51.02.01030
0.75.020
4.0 A
3.07.0
6.0 A
IB, BASE CURRENT (mA)
Figure 9. Collector Saturation Region
TJ = 25°C
TJ = 25°C
, COLLECTOR-EMITTER VOLTAGE (VOLTS)
CE
V
3.0
2.6
2.2
1.8
1.4
1.0
3.0
2.5
2.0
IC = 2.0 A
0.3
0.51.02.01030
0.75.020
4.0 A
I
, BASE CURRENT (mA)
B
6.0 A
3.07.0
TJ = 25°C
TJ = 25°C
1.5
VBE @ VCE = 4.0 V
V, VOLTAGE (VOLTS)
V
@ IC/IB = 250
1.0
0.5
0.1
BE(sat)
V
@ IC/IB = 250
CE(sat)
0.2 0.30.5 0.7 1.03.010
2.0
7.05.0
IC, COLLECTOR CURRENT (AMP)
Figure 10. “On” Voltages
ORDERING INFORMATION
DevicePackageShipping
2N6040GTO−220
2N6042GTO−220
2N6043GTO−220
2N6045GTO−220
(Pb−Free)
(Pb−Free)
(Pb−Free)
(Pb−Free)
V
@ IC/IB = 250
1.5
V, VOLTAGE (VOLTS)
BE(sat)
VBE @ VCE = 4.0 V
1.0
V
@ IC/IB = 250
CE(sat)
0.5
0.10.2 0.30.5 0.7 1.03.010
I
, COLLECTOR CURRENT (AMP)
C
2.07.05.0
50 Units / Rail
50 Units / Rail
50 Units / Rail
50 Units / Rail
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Page 6
PNP − 2N6040, 2N6042, NPN − 2N6043, 2N6045
P
al
PACKAGE DIMENSIONS
TO−220
CASE 221A−09
ISSUE AH
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
SEATING
−T−
PLANE
B
4
Q
123
F
T
A
U
C
S
H
K
Z
L
V
R
J
G
D
N
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
DIM MINMAXMINMAX
A 0.570 0.620 14.48 15.75
B 0.380 0.4159.66 10.53
C 0.160 0.1904.074.83
D 0.025 0.0380.640.96
F 0.142 0.1613.614.09
G 0.095 0.1052.422.66
H 0.110 0.1612.804.10
J 0.014 0.0240.360.61
K 0.500 0.562 12.70 14.27
L 0.045 0.0601.151.52
N 0.190 0.2104.835.33
Q 0.100 0.1202.543.04
R 0.080 0.1102.042.79
S 0.045 0.0551.151.39
T 0.235 0.2555.976.47
U 0.000 0.0500.001.27
V 0.045---1.15---
Z--- 0.080---2.04
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
MILLIMETERSINCHES
ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/ Patent− Marking.pdf . S CILLC reserves t he right to m ake changes wit hout further notice to any products h erein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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or authorized for use as components in systems intended for surgic al i mplant into the body, or other applications intended to s upport o r sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, em ployees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable at torney f ees a r ising o ut o f, d irectly o r indirectly, any claim o f p ersonal i njury o r d eath a ssociated w ith s uch u nint ended o r u nauthorized u se, even if such claim
alleges that SCILLC was negligent r egarding the design o r manuf acture o f t he p art. SCILLC is an E qual O pportunity/Af firmative Act ion Employer. This literature is s ubject t o all applicable
copyright laws and is not for resale in any manner.
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Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your loc
Sales Representative
2N6040/D
6
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