D Two-Chip Design
D High Slew Rate
D Low Offset/Drift Voltage
D Low Gate Leakage: 1 pA
D Low Noise
D High CMRR: 85 dB
GS(off)
(V)V
(BR)GSS
Min (V)gfs Min (mS)IG Typ (pA)jV
D Minimum Parasitics Ensuring Maximum
High-Frequency Performance
D Improved Op Amp Speed, Settling Time Accuracy
D Minimum Input Error/Trimming Requirement
D Insignificant Signal Loss/Error Voltage
D High System Sensitivity
D Minimum Error with Large Input Signal
GS1
– V
j Max (mV)
GS2
D Wideband Differential Amps
D High-Speed, Temp-Compensated,
Single-Ended Input Amps
D High Speed Comparators
D Impedance Converters
DESCRIPTION
The 2N5911/5912 are matched pairs of JFETs mounted in a
TO-78 package. This two-chip design reduces parasitics and
gives better performance at high frequencies while ensuring
extremely tight matching.
The hermetically-sealed TO-78 package is available with full
military screening per MIL-S-19500 (see Military Information).
S
1
1
D
1
2
3
G
1
ABSOLUTE MAXIMUM RATINGS
TO-78
4
Case
Top View
For similar products see the SO-8 packaged
SST440/SST441, the TO-71 packaged U440/U441, the
low-noise SST/U401 series, and the low-leakage U421/423
data sheets.
Gate-Source Cutoff VoltageV
Saturation Drain Current
b
Gate Reverse CurrentI
Gate Operating CurrentI
Gate-Source VoltageV
Gate-Source
Forward Voltage
c
Dynamic
Common-Source
Forward Transconductance
Common-Source
Output Conductance
Common-Source
Forward Transconductance
Common-Source
Output Conductance
Common-Source
Input Capacitance
Common-Source Reverse
Transfer Capacitance
Equivalent Input
Noise Voltage
Noise FigureNF
Matching
Differential
Gate-Source Voltage
Gate-Source Voltage
Differential Change
with Temperature
Saturation Drain
Current Ratio
Transconductance Ratio
V
(BR)GSS
GS(off)
I
DSS
IG = –1 mA, VDS = 0 V
VDS = 10 V, ID = 1 nA–3.5–1–5–1–5
VDS = 10 V, VGS = 0 V15740740mA
VGS = –15 V, VDS = 0 V–1–100–100pA
GSS
TA = 150_C
VDG = 10 V, ID = 5 mA–1–100–100pA
V
C
G
GS
GS(F)
g
fs
g
os
g
fs
g
os
C
iss
rss
e
n
VDG = 10 V, IG = 5 mA–1.5–0.3–4–0.3–4
IG = 1 mA, VDS = 0 V0.7
VDG = 10 V, ID = 5 mA
VDG = 10 V, ID = 5 mA
VDG = 10 V, ID = 5 mA
VDG = 10 V, ID = 5 mA
f = 100 MHz
VDG = 10 V, ID = 5 mA
VDG = 10 V, ID = 5 mA
VDG = 10 V, ID = 5 mA
TA = 125_C
f = 1 kHz
f = 1 MHz
f = 10 kHz
RG = 100 kW
|
V
GS1
|
D
V
GS1
– V
DT
I
DSS1
I
DSS2
g
g
– V
fs1
fs2
GS2
GS2
|
|
VDG = 10 V, ID = 5 mA41015mV
VDG = 10 V, ID = 5 mA
T
= –55 to 125_C
A
VDS = 10 V, VGS = 0 V0.980.9510.951
VDS = 10 V, ID = 5 mA
f = 1 kHz
Limits
2N59112N5912
–35–25–25
–2–250–250nA
–0.3–100–100nA
6510510mS
70100100
5.8510510mS
90150150
355
11.21.2
42020
0.111dB
152040
0.980.9510.951
mS
mS
pF
nV⁄
√Hz
mV/_C
V
V
V
|
|
Differential Gate Current
Common Mode
Rejection Ratio
Notes
a. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.NZF
b. Pulse test: PW v300 ms duty cycle v3%.
c. This parameter not registered with JEDEC.
All product specifications and data are subject to change without notice.
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