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2N5018 SERIES
SINGLE P-CHANNEL
Linear Integrated Systems
FEATURES
DIRECT REPLACEMENT FOR SILICONIX 2N5018
ZERO OFFSET VOLTAGE
LOW ON RESISTANCE 75Ω
ABSOLUTE MAXIMUM RATINGS1
@ 25 °C (unless otherwise stated)
Maximum Temperatures
Storage Temperature -55 to 200°C
Junction Operating Temperature -55 to 200°C
Maximum Power Dissipation
Continuous Power Dissipation 500mW
Maximum Currents
Gate Current -50mA
Maximum Voltages
Gate to Drain 30V
Gate to Source 30V
STATIC ELECTRICAL CHARACTERISTICS @25 °C (unless otherwise stated)
SYM. CHARACTERISTIC TYP
BV
Gate to Source Breakdown Voltage 30 30 IG = 1µA, VDS = 0V
GSS
V
Gate to Source Cutoff Voltage 10 5 VDS = -15V, ID = -1µA
GS(off)
V
Drain to Source On Voltage
DS(on)
I
Drain to Source Saturation Current2 -10 -5 mA VDS = -20V, VGS = 0V
DSS
I
Gate Leakage Current 2 2 VGS = 15V, VDS = 0V
GSS
I
Drain Cutoff Current
D(off)
I
Drain Reverse Current -2 -2 nA VDG = -15V, IS = 0A
DGO
r
Drain to Source On Resistance 75 150 Ω ID = -1mA, VGS = 0V
DS(on)
-0.5 VGS = 0V, ID = -6mA
-0.5 V V
-10 -10
-10 -10 µA V
2N5018 2N5019
MIN MAX MIN MAX
JFET SWITCH
TO-18
BOTTOM VIEW
G
2
1
S
UNITS CONDITIONS
nA
D
3
= 0V, ID = -3mA
GS
VDS = -15V, VGS = 12V
= -15V, VGS = 7V
DS
Linear Integrated System
• 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261
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DYNAMIC ELECTRICAL CHARACTERISTICS @25 °C (unless otherwise stated)
SYM. CHARACTERISTIC TYP
r
Drain to Source On Resistance 75 150 Ω
ds(on)
C
Input Capacitance 45 45
iss
2N5018 2N5019
MIN MAX MIN MAX
10
C
Reverse Transfer Capacitance
rss
10
UNITS CONDITIONS
ID = 0A, VGS = 0V
f = 1kHz
V
= -15V, VGS = 0V
DS
f = 1MHz
pF
VDS = 0V, VGS = 12V
f = 1MHz
V
= 0V, VGS = 7V
DS
f = 1MHz
SWITCHING CHARACTERISTICS (max)
SYM. CHARACTERISTIC 2N5018 2N5019 UNITS
t
15 15
d(on)
Turn On Time
tr
t
15 25
d(off)
Turn Off Time
tf
20 75
50 100
ns
SWITCHING CIRCUIT CHARACTERISTICS
SYM. 2N5018 2N5019
VDD -6V -6V
VGG 12V 8V
RL 910Ω 1.8kΩ
RG 220Ω 390Ω
I
-6mA -3mA
D(on)
V
0V 0V
GS(H)
V
12V 7V
GS(L)
1. Absolute maximum ratings are limiting values above which serviceability may be impaired.
2. Pulse test: PW ≤ 300µs, Duty Cycle ≤ 3%
Information furnished by Linear Integrated Systems is believed to be accurate and reliable. However, no responsibility is assumed for its
use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implicatio
otherwise under any patent or patent rights of Linear Integrated Systems.
Three Lead
0.195
DIA.
0.175
0.030
MAX.
3 LEADS
0.019
0.016
0.100
45°
0.046
0.036
TO-18
DIA.
1
2
0.150
0.115
0.500 MIN.
0.050
3
0.048
0.028
0.230
0.209
DIA.
SWITCHING TEST CIRCUIT
V
GG
1.2k
0.1µF
1.2k
Ω
R
G
Ω
51
Ω
V
GS(H)
V
GS(L)
51
Ω
Sampling
Scope
V
DD
R
L
7.5k
Ω
51
Ω
NOTES
n or
Linear Integrated System
• 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261
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