-SEU saturated cross section = 5E-3 cm
hard errors
• Package:
- 32 Pin R
- 32 Pin R
AD-PAK® flat pack
AD-PAK® DIP
- JEDEC-approved byte-wide pinout
• Address Access Time:
- 200, 250 ns maximum access times available
• High endurance:
- 10,000 erase/write (in Page Mode), 10-year data
retention
• Page write mode:
- 1 to 128 bytes
• Automatic programming
- 10 ms automatic page/byte write
• Low power dissipation
- 20 mW/MHz active current (typ.)
- 72 µW standby (maximum)
2
2
(read mode)
2
(write mode) with
V
CC
V
SS
RES
OE
CE
WE
RES
A0
A6
A7
A16
High Voltage
Generator
Control Logic Timing
Address
Buffer and
Latch
Y Decoder
X Decoder
I/O0I/O7 RDY/Busy
I/O Buffer and
Input Latch
Y Gating
Memory Array
Data Latch
Logic Diagram
DESCRIPTION:
Maxwell Technologies’ 28LV010 high density, 3.3V, 1 Megabit
EEPROM microcircuit features a greater than 100 krad (Si)
total dose tolerance, depending upon space mission. The
28LV010 is capable of in-system electrical Byte and Page programmability. It has a 128-Byte Page Programming function to
make its erase and write operations faster. It also features
Data
Polling and a Ready/Busy signal to indicate the completion of erase and programming operations. In the 28LV010,
hardware data protection is provided with the RES
tion to noise protection on the WE
signal and write inhibit on
power on and off. Meanwhile, software data protection is
implemented using the JEDEC-optional Standard algorithm.
The 28LV010 is designed for high reliability in the most
demanding space applications.
Maxwell Technologies' patented R
AD-PAK® packaging technol-
ogy incorporates radiation shielding in the microcircuit package. It eliminates the need for box shielding while providing
the required radiation shielding for a lifetime in orbit or space
mission. In a GEO orbit, R
AD-PAK provides greater than 100
krad (Si) radiation dose tolerance. This product is available
with screening up to Class S.
Note:The recommended form of data protection during power
on/off is to hold the RES
pin to VSS during power up and power
down. This may be accompanied by connecting the RES
to the CPU reset line. Failure to provide adequate protection
during power on/off may result in lost or modified data.
FIGURE 11. SEU SATURATED CROSS SECTION VALUESIN WRITE MODE
28LV010 WRITE MODE AVERAGE CROS S-S ECTION
1.00E-01
1.00E-02
1.00E-03
28LV010
1.00E-04
CROSS-SECTION [cm^2]
1.00E-05
1.00E-06
0 102030405060708090
LET [MeV-cm^2/mg]
SL1
SL2
SL3
N4
N5
EEPROM APPLICATION NOTES
This application note describes the programming procedures for the EEPROM modules and with details of various
techniques to preserve data protection.
Automatic Page Write
Page-mode write feature allows 1 to 128 bytes of data to be written into the EEPROM in a single write cycle, and
allows the undefined data within 128 bytes to be written corresponding to the undefined address (A0 to A6). Loading
the first byte of data, the data load window opens 30 µs for the second byte. In the same manner each additional byte
of data can be loaded within 30 µs. In case CE
erase and write mode automatically and only the input data are written into the EEPROM.
and WE are kept high for 100(s after data input, EEPROM enters
Memory
WE CE Pin Operation
During a write cycle, addresses are latched by the falling edge of WE or CE, and data is latched by the rising edge of
WE
or CE.
Data Polling
Data Polling function allows the status of the EEPROM to be determined. If EEPROM is set to read mode during a
write cycle, an inversion of the last byte of data to be loaded outputs from I/O 7 to indicate that the EEPROM is performing a write operation.
1000579
12.19.01 Rev 3
All data sheets are subject to change without notice
RDY/Busy signal also allows a comparison operation to determine the status of the EEPROM. The RDY/Busy signal
has high impedance except in write cycle and is lowered to V
the RDY/Busy
signal changes state to high impedance.
after the first write signal. At the-end of a write cycle,
OL
RES Signal
When RES is LOW, the EEPROM cannot be read and programmed. Therefore, data can be protected by keeping
low when VCC is switched. RES should be high during read and programming because it doesn’t provide a latch
RES
function.
Memory
Data Protection
To protect the data during operation and power on/off, the EEPROM has the internal functions described below.
1. Data Protection against Noise of Control Pins (CE, OE, WE) during Operation.
During readout or standby, noise on the control pins may act as a trigger and turn the EEPROM to programming mode by mistake. To prevent this phenomenon, the EEPROM has a noise cancellation function that cuts noise if its width is 20 ns or less in
programming mode. Be careful not to allow noise of a width of more than 20 ns on the control pins.
2. Data Protection at V
CC
on/off
1000579
12.19.01 Rev 3
All data sheets are subject to change without notice
When VCC is turned on or off, noise on the control pins generated by external circuits, such as CPUs, may turn the EEPROM to
programming mode by mistake. To prevent this unintentional programming, the EEPROM must be kept in unprogrammable
state during V
RES
should be kept at VSS level when VCC is turned on or off. The EEPROM breaks off programming operation when RES
become low, programming operation doesn’t finish correctly in case that RES
should be kept high for 10 ms after the last data input.
on/off by using a CPU reset signal to RES pin.
CC
falls low during programming operation. RES
28LV010
Memory
3. Software Data Protection
The software data protection function is to prevent unintentional programming caused by noise generated by external circuits.
In software data protection mode, 3 bytes of data must be input before write data as follows. These bytes can switch the nonprotection mode to the protection mode.
Software data protection mode can be canceled by inputting the following 6 bytes. Then, the EEPROM turns to the non-protection mode and can write data normally. However, when the data is input in the canceling cycle, the data cannot be written.
1000579
12.19.01 Rev 3
All data sheets are subject to change without notice
These data sheets are created using the chip manufacturers published specifications. Maxwell Technologies verifies
functionality by testing key parameters either by 100% testing, sample testing or characterization.
The specifications presented within these data sheets represent the latest and most accurate information available to
date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no
responsibility for the use of this information.
Maxwell Technologies’ products are not authorized for use as critical components in life support devices or systems
without express written approval from Maxwell Technologies.
Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Technologies. Maxwell Technologies’ liability shall be limited to replacement of defective parts.
28LV010
Memory
1000579
12.19.01 Rev 3
All data sheets are subject to change without notice