Datasheet 28C64ATM-4, 28C64ATM-3, 28C64ATM-2, 28C64ATM-1, 28C64ATI-4 Datasheet (Turbo IC)

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Page 1
ADDRESSES (A0 - A12)
The Addresses are used to select an 8 bits memory location during a write or read opera­tion.
OUTPUT ENABLE (OE)
The Output Enable input activates the output buff­ers during the read operations.
CHIP ENABLES (CE)
FEATURES:
120 ns Access Time
Automatic Page Write Operation Internal Control Timer Internal Data and Address Latches for 64 Bytes
Fast Write Cycle Times Byte or Page Write Cycles: 10 ms Time to Rewrite Complete Memory: 1.25 sec T ypical Byte Write Cycle Time: 160 µsec
Software Data Protection
Low P ower Dissipation 50 mA Active Current 200 µA CMOS Standby Current
Direct Microprocessor End of Write Detection Data Polling
High Reliability CMOS Technology with Self Redundant
EEPROM Cell
Endurance: 100,000 Cycles Data Retention: 10 Years
TTL and CMOS Compatible Inputs and Outputs
Single 5 V ± 10% Pow er Supply f or Read and
Programming l Oper ations
JEDEC Approved Byte-Write Pinout
Turbo IC, Inc.
DESCRIPTION:
The Turbo IC 28C64A is a 8K X 8 EEPROM fabricated with T urbo’ s proprietary, high reliability, high performance CMOS technology. The 64K bits of memory are organized as 8K by 8 bits. The de vice offers access time of 120 ns with power dissipation below 250 mW .
The 28C64A has a 64-bytes page write operation enabling the entire memory to be typically written in less than 1.25 seconds. During a write cycle, the address and 1 to 64 b ytes of data are internally latched, freeing the address and data bus for other microprocessor operations. The programming process is automatically controlled by the device using an internal control timer. Data polling on one or all I/O can be used to detect the end of a programming cycle. In addition, the 28C64A includes an user-optional software data write mode offering additional protection against unwanted (false) write. The de vice utiliz es an error protected self redundant cell for extended data retention and endur ance.
WRITE ENABLE (WE)
The Write Enable input initiates the writing of data into the memory.
DATA INPUT/OUTPUT (I/O0-I/O7)
Data Input/Output pins are used to read data out of the memory or to write Data into the memory.
PIN DESCRIPTION
HIGH SPEED CMOS
64K ELECTRICALLY ERASABLE PROGRAMMABLE ROM
8K X 8 BIT EEPROM
28C64A
4
3
5
2
1
6 7 8 9 10 11 12 13
303132
A8 A9 A11 NC OE A10 CE I/O7 I/O6
A6 A5 A4 A3 A2 A1 A0
NC
I/O0
I/O1
I/O2
GNDNCI/O3
I/O4
I/O5
A12
A7 NCNCVCCWENC
32 pins PLCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
16
17
18
19
20
21
22
23
24
25
26
27
28NC
A12
A7 A6 A5 A4 A3 A2 A1
A0 I/O0 I/O1 I/O2
GND
VCC WE NC A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
16
17
18
19
20
21
22
23
24
25
26
27
28NC
A12
A7 A6 A5 A4 A3 A2 A1
A0 I/O0 I/O1 I/O2
GND
VCC WE NC A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10 I/O7 I/O5 I/O3 I/O2 I/O0 A1
A2
A0
I/O1
GND
I/O4
I/O6
CE
OE
A9
NC
VCC
A12
A6 A4
A3
A5
A7
NC
WE
A8
A11
28 pins PDIP
28 pins SOIC (SOG)
28 pins TSOP
14
29 28 27 26 25 24 23 22
21
20
19
18
17
16
15
Page 2
DEVICE OPERA TION
READ:
The 28C64A is accessed like a static RAM. Read operations are initiated by both CE and OE going low and terminated by either CE or OE return­ing high. The outputs are at the high impedance state whenever CE or OE returns high. The two line control architecture gives designers flex­ibility in preventing bus contention.
WRITE:
A write cycle is initiated when CE and WE are low and OE is high. The address is latched internally on the falling edge of CE or WE whichever occurs last. The data is latched b y the rising edge of CE or WE whiche ver occurs first. Once a byte write cycle has been started, the inter nal timer automatically generates the write sequence to the completion of the write operation.
P A GE WRITE OPERATION:
The page write operation of 28C64A allows one to 64 bytes of data to be serially loaded into the device and then simultaneously written into memory during the internally generated write cycle. After the first byte has been loaded, successive bytes of data may be loaded until the full page of 64 bytes is loaded. Each new byte to be written must be loaded within 200 µs of the previously loaded byte. The page address defined by the ad­dresses A6-A12 is latched by the first CE or WE falling edge which ini­tiates a writing cycle and they will stay latched until the completion of the page write. Any changes in the page addresses during the load-write cycle will not affect the initially latched page addresses. Addresses A0 ­A5 are used to define which bytes will be loaded and written within the 64 bytes page. The bytes may be loaded in any order that is convenient to the user. The content of a loaded byte may be altered at any time during the loading cycle if the maximum allowed byte-load time (200 µs) is not exceeded. Only loaded bytes within the page will be written; no rewriting will occur to the non-selected bytes in the page.
DATA POLLING:
The 28C64A features DATA POLLING to indicate the completion of a write cycle to the host system. During a byte or page write cycle, an attempted read of the last byte loaded into the page will result in the complement of the loaded byte on all outputs I/O0 - I/O7 (i.e. loaded data 01010110, read data 10101001). Data P olling feature may be used by an attempted read on one or more outputs (whatever is convenient for the system developer). Once the write cycle has been completed, true data is valid on all outputs and the next cycle may be started.
DATA PROTECTION:
The 28C64A has three hardware features to protect the written content of the memory against inadvertent writes :
a.) Vcc threshold detector: If Vcc is below 2.5 V, the write capa­bilities of the chip is inhibited for whatever input conditions. b.) Noise protection: A WE, OE, or CE pulse less than 10 ns in width is not able to initiate a write cycle. c.) Write inhibit: Holding OE at low, or CE at high, or WE at high inhibits the write cycle.
SOFTWARE WRITE PROTECTION:
The 28C64A offers a software controlled data write protection feature. The device is delivered to the user with the software data write protection DIS­ABLED; i.e. the device will go to the data write operation as long as Vcc exceeds 2.5 V and CE, WE, and OE inputs are set at write mode levels. The 28C64A can be automatically protected against an accidental write operation during power-up or power-down without any external circuitry by enabling the software data write protection features. This features is en­abled after the first write cycle which includes the software algorithm. After this operation is done, the data write function of the device may be per­formed only if every page write cycle is preceded by the software algo­rithm. The device will maintain its software protect feature for the rest of its life unless that the software algorithm for disabling the protection is imple­mented.
SOFTWARE ALGORITHM:
The 28C64A has an internal register for the software algorithm which en­ables the memory to provide the user with additional features:
Turbo IC, Inc.
a.) Software Write Protect Enable
A sequence of three dummy data writes to the memory will activate internal EEPROM fuses during the first page write cycle. These EE­PROM fuses will reject any write attempts of new pages of data unless the three dummy data writes are repeated at the beginning of any page writes. The timing f or the dummy data and addresses m ust be the same as for a normal write operation. A violation of the three steps write protect sequence in data or address timing and content will abort the procedure and reset the device to the starting point condition.
Note: After the three dummy data writes, at least one page load/ write cycle must be performed. If no additional page data is added to the three dummy data writes, the software write protect will not be enabled until the next write, which will not be protected.
T able 1 sho ws the required procedure for enab ling the software write protect:
Step Mode Address A12-A0 Data I/O 7-0 1 Page Write 1555 Hex AA Hex 2 Page Write 0AAA Hex 55 Hex 3 Page Write 1555 Hex A0 Hex 4-67 P age Write Address Data
b.) Software Write Protect Disable
The software algorithm of 28C64A includes a six steps sequence of dummy data writing to disable the software write protect feature de­scribed in a.). The six steps write sequence shown in Table 2 must be performed at the beginning of a page write cycle. A violation of the six steps write sequence in data or address timing and content will abort the procedure and reset the chip to the starting point con­dition. After a page write cycle including the six steps write sequence has been performed, the 28C64A does not require the use of three dummy data writes described in a.) for the following page write cycle. The device is at the software write protect disabled state.
Note: After the six dummy data writes, at least one page load/ write cycle must be performed. If no additional page data is added to the six dummy data writes, the software write pr otect disable will not be activated. Table 2 shows the required procedure for dis-
abling the software write protect: step Mode Address A12-A0 Data I/O 7-0
1 Page Write 1555 Hex AA Hex 2 Page Write 0AAA Hex 55 Hex 3 Page Write 1555 Hex 80 Hex 4 Page Write 1555 Hex AA Hex 5 Page Write 0AAA Hex 55 Hex 6 Page Write 1555 Hex 20 Hex 7-70 Page Write Address Data
c.) Software Chip Clear
The software algorithm of 28C64A includes a sequence of six steps dummy data writing to perform a chip clear operation. Table 3 shows the six steps write sequence to perform the software chip clear op­eration:
Step Mode Address A12-A0 Data I/O 7-0 1 Page Write 1555 Hex AA Hex 2 Page Write 0AAA Hex 55 Hex 3 Page Write 1555 Hex 80 Hex 4 Page Write 1555 Hex AA Hex 5 Page Write 0AAA Hex 55 Hex 6 Page Write 1555 Hex 10 Hex
At the end of the six steps write sequence shown in Table 3, the device automatically activates its internal timer to control the chip
28C64A
Page 3
A.C. CHARACTERISTICS - READ OPERATION
28C64A-1 28C64A-2 28C64A-3 28C64A-4
Symbol Parameters Min Max Min Max Min Max Min MaxUnit tacc Address to 120 150 200 250 ns
Output Delay
tce CE to Output 120 150 200 250 ns
Delay toe OE to Output 70 90 110 150 ns tdf OE to Output 0 40 0 60 0 90 0 90 n s
In High Z toh Output Hold 0000ns
from Address
Changes, Chip
Enable or
Output Enable
Whichever
Occurs First
Symbol Parameter Condition Min Max Units
Icc Active Vcc CE=OE=Vil; All I/O 50 (C) mA
Current Open, Min Read or 70 (I) mA
Write Cycle Time 90 (M) mA
Isb1 CMOS CE=Vcc-0.3 V to 200 (C) µA
Standby Vcc+1 V 300 (I&M) µA Current
Isb2 TTL Standby CE=Vih, OE=Vil, 3 mA
Current All I/O Open, Other
Inputs=Vcc Max Vin=Vcc Max
Iil Input 1 µA
Leakage Current
Iol Output 10 µA
Leakage Current
Vil Input Low -0.1 -0.8 V
Voltage
Vih Input High 2 Vcc+0.3 V
Voltage
Vol Output Low Iol=2.1 mA 0.45 V
Voltage
Voh Output High Ioh=-0.45 mA 2.4 V
Voltage
28C64A
Turbo IC, Inc.
D.C. CHARACTERISTICS
erase cycle; typically takes 20 msec. After a software chip clear op­eration has been completed, all 64K bit locations of memory show high level at read operation mode.
d.) Software Autoclear Disable Mode
This software algorithm disables the internal automatic clear before write cycle. Table 4 shows the six steps needed to perform the auto­clear disable mode:
Step Mode Address A12-A0 Data I/O 7-0 1 Page Write 1555 Hex AA Hex 2 Page Write 0AAA Hex 55 Hex 3 Page Write 1555 Hex 80 Hex 4 Page Write 1555 Hex AA Hex 5 Page Write 0AAA Hex 55 Hex 6 Page Write 1555 Hex 40 Hex 7-70 Page Write Address Data
Page write operation using the software autoclear disable mode will reduce programming time to typically 5 msec. The page write using software autoclear disable mode is usually used after a chip clear or a software chip clear operation. At the end of the six steps sequence, the autoclear before write is disabled and will stay that wa y unless a power-down occurs or the software autoclear enable procedure is initiated.
e.) Software Autoclear Enable Mode
Automatic page clear before page write can be restored to 28C64A either by Vcc power-down or by software autoclear enable mode. Table 5 shows the six steps page write procedure needed to enable software autoclear mode:
Step Mode Address A12-A0 Data I/O 7-0 1 Page Write 1555 Hex AA Hex 2 Page Write 0AAA Hex 55 Hex 3 Page Write 1555 Hex 80 Hex 4 Page Write 1555 Hex AA Hex 5 Page Write 0AAA Hex 55 Hex 6 Page Write 1555 Hex 50 Hex 7-70 Page Write Address Data
A.C. Read Wave Forms
A.C. TEST CONDITIONS
Output Load : 1 TTL Load and Cl=100 pF Input Rise and Fall Times : < 10 ns Input Pulse Level : 0 V to 3 V Timing Measurement Reference Level : 1.5 V
ABSOLUTE MAXIMUM STRESS RANGES *
TEMPERATURE
Storage: -65° C to 150° C Under Bias: -55° C to 125° C
ALL INPUT OR OUTPUT VOLTAGES
with respect to Vss +6 V to -0.3 V
“Absolute Maximum Ratings” ma y cause perma­nent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indi­cated in the operation section of this specifica­tion is not implied. Exposure to absolute maxi­mum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS Temperature Range: Commercial: 0° C to 70° C
Industrial: -40° C to 85° C Military: -55° C to 125° C
Vcc Supply Voltage:5 V ± 10%
Endurance: 100,000 Cycles/Byte (Typical) Data Retention: 10 Years
(C) = COMMERICAL (I) = INDUSTRIAL (M) = MILITAR Y
tacc
ADDRESS VALID
ADDRESS
CE
OE
OUTPUT HIGH-Z
toe
tce
tdf
toh
OUTPUT VALID
HIGH-Z
Page 4
A.C. WRITE CHARACTERISTICS
Symbol Parameter Min Max Units tas Address Set-up Time 20 ns tah Address Hold Time 100 ns tcs Write Set-up Time 0 ns tch Write Hold Time 0 ns tcw CE Pulse Width 150 ns twp WE Pulse Width 150 ns toes OE Set-up Time 20 ns toeh OE Hold Time 20 ns tds Data Set-up Time 50 ns tdh Data Hold Time 0 ns tblc Byte Load Cycle 0.2 200 µs tlp Last Byte Loaded to Data
Polling Output 500 µ s
twc Write Cycle Time 10 ms
Part Numbers & Order Inf ormation
28C64APC-2
Turbo IC, Inc.
Speed
-1 120 ns
-2 150 ns
-3 200 ns
-4 250 ns
Temperature C -Commercial I -Industrial M -Military
Package J -PLCC
P -PDIP
S -SOIC T -TSOP
Turbo IC, Inc. 2365 Paragon Drive, Suite I, San Jose, CA 95131 Phone: 408-392-0208 Fax: 408-392-0207
See us at www.turbo-ic.com
8K x 8 EEPROM
Page Mode Write Wave Form
PAGE MODE WRITE CHARACTERISTICS
Symbol Parameter Min Max Unit
twc Write Cycle Time 10 ms tas Address Set-up Time 20 ns tah Address Hold Time 100 ns tds Data Set-up Time 50 n s tdh Data Hold Time 0 ns twp Write Pulse Width 150 ns tblc Byte Load Cycle Time 0.2 200 µs
28C64A
TURBO IC PRODUCTS AND DOCUMENTS
1. All documents are subject to change without notice. Please contact Turbo IC for the latest revision of documents.
2. T urbo IC does not assume an y responsibility for an y damage to the user that ma y result from accidents or operation under abnormal conditions.
3. Turbo IC does not assume any responsibility for the use of any circuitry other than what
embodied in a Turbo IC product. No other circuits, patents, licenses are implied.
4. T urbo IC products are not authorized f or use in lif e support systems or other critical systems
where component failure may endanger life. System designers should design with error de­tection and
correction, redundancy and back-up features.
Chip Clear Wave Form
The content of the 28C64A may be altered to HIGH by the use of the Chip Clear operation. By setting CE to low, OE to 12 volts, and WE to low, the entire memory can be cleared (written HIGH) within 20 ms. The Chip Clear operation is a latch operation mode. After the Chip Clear starts, the internal chip timer takes over and completes the clear with­out CE, OE and WE being held active.
Rev . 3.0 - 10/28/
01
A.C. Write Characteristics CE-Controlled
A.C. Write Characteristics WE-Controlled
twc Write Cycle Time (IND & MIL) 15 ms
OE
ADDRESS
CE
WE
DATA
toes
tas
tcs tah
toeh
tch
tcw
tds
tblc
twc
tdh
HIGH-Z
DATA VALID
HIGH-Z
VALID
OE
ADDRESS
CE
WE
DATA
toes
tas
tcs tah
toeh
tch
twp
tds
tblc
twc
tdh
HIGH-Z
DATA VALID
HIGH-Z
VALID
OE
CE
WE
ts= 20 ns tp= 200 ns th= 20 ns VH=12.0 V±0.5V
tp
ts th
VH
VIH
VIH
VIL
VIH
VIL
OE
CE
WE
A0-A5
DATA
twp
tblc
tah
tas
tds
tdh
BYTE-0
BYTE-1
BYTE-2
AD-VALID
AD-VALID
AD-VALID
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