Datasheet 25LC640XT-I-ST, 25LC640XT-ST, 25LC640X-I-ST, 25LC640X-ST, 25LC640T-I-ST Datasheet (Microchip Technology Inc)

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Page 1



1997 Microchip Technology Inc.

Preliminary

DS21223A-page 1

25AA640/25LC640/25C640

DEVICE SELECTION TABLE

FEATURES

• Low power CMOS technology

- Write current: 3 mA typical

- Read current: 500 µ A typical

- Standby current: 500 nA typical

• 8192 x 8 bit organization

• 32 byte page

• Write cycle time: 5ms max.

• Self-timed ERASE and WRITE cycles

• Block write protection

- Protect none, 1/4, 1/2, or all of array

• Built-in write protection

- Power on/off data protection circuitry

- Write enable latch

- Write protect pin

• Sequential read

• High reliability

- Endurance: 1M cycles (guaranteed)

- Data retention: > 200 years

- ESD protection: > 4000 V

• 8-pin PDIP, SOIC, and TSSOP packages

• Temperature ranges supported:

DESCRIPTION

The Microchip Technology Inc. 25AA640/25LC640/ 25C640 (25xx640

) is a 64K bit serial Electrically Erasable PROM. The memory is accessed via a simple Serial Peripheral Interface (SPI) compatible serial bus. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a chip select (CS

) input.

Communication to the device can be paused via the hold pin (HOLD

). While the device is paused, transitions on its inputs will be ignored, with the exception of chip select, allowing the host to service higher priority interrupts.

PACKAGE TYPES

BLOCK DIAGRAM

Part

Number

Range

Max Clock Frequency

Temp

Ranges

25AA640 1.8-5.5V 1 MHz C,I 25LC640 2.5-5.5V 2 MHz C,I

25C640 4.5-5.5V 3 MHz C,I,E

- Commercial: (C) 0 ° C to +70 ° C

- Industrial: (I) -40 ° C to +85 ° C

- Automotive: (E) (25C640) -40 ° C to +125 ° C

25xx640

TSSOP

1 2 3 4

8 7 6 5

SCK SI V

HOLD

VCC

CS SO

25xx640

PDIP/SOIC

1 2 3 4

8 7 6 5

HOLD SCK SI

CS SO

VSS

SCK

HOLD

Status

I/O Control

Memory

Control

Logic

Dec

HV Generator

EEPROM

Array

Page Latches

Y Decoder

Sense Amp. R/W Control

Logic

VCC VSS

64K SPI

™

Bus Serial EEPROM

*25xx640 is used in this document as a generic part number for the 25AA640/25LC640/25C640 devices. SPI is a trademark of Motorola.

Page 2

25AA640/25LC640/25C640

DS21223A-page 2

Preliminary



1997 Microchip Technology Inc.

1.0 ELECTRICAL CHARACTERISTICS

1.1 Maxim

um Ratings*

Vcc...................................................................................7.0V

All inputs and outputs w.r.t. Vss.................. -0.6V to Vcc+1.0V

Storage temperature.......................................-65˚C to 150˚C

Ambient temperature under bias..................... -65˚C to 125˚C

Soldering temperature of leads (10 seconds).............+300˚C

ESD protection on all pins.................................................4kV

*Notice: Stresses above those listed under ‘Maximum ratings’ may

cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this speciﬁcation is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability

TABLE 1-1: PIN FUNCTION TABLE

FIGURE 1-1: AC TEST CIRCUIT

1.2 A

C Test Conditions

Name Function

Chip Select Input

SO Serial Data Output

SI Serial Data Input

SCK Serial Clock Input

Write Protect Pin

Ground

Supply Voltage

HOLD

Hold Input

AC Waveform:

= 0.2V

= V

- 0.2V (Note 1)

= 4.0V (Note 2)

Timing Measurement Reference Level

Input 0.5 V

Output 0.5 V

Note 1: For V

≤

4.0V

For V

> 4.0V

VCC

100 pF

1.8 K

2.25 K

TABLE 1-2: DC CHARACTERISTICS

All parameters apply over the speciﬁed operating ranges unless otherwise noted.

Commercial (C): Tamb = 0 ° C to +70 ° C

= 1.8V to 5.5V

Industrial (I): Tamb = -40 ° C to +85 ° C V

= 1.8V to 5.5V

Automotive (E): Tamb = -40 ° C to +125 ° C V

= 4.5V to 5.5V (25C640 only)

Parameter Symbol Min Max Units Test Conditions

High level input voltage

1 2.0 V

+1 V V

≥ 2.7V (Note)

2 0.7 V

+1 V V

< 2.7V (Note)

Low level input voltage

1 -0.3 0.8 V V

≥ 2.7V (Note)

2 -0.3 0.3 V

V V

< 2.7V (Note)

Low level output voltage

— 0.4 V I

= 2.1 mA

— 0.2 V I

= 1.0 mA, V

< 2.5V

High level output voltage V

-0.5 — V I

=-400 µ A

Input leakage current I

-10 10

A CS

= V

, V

= V

Output leakage current I

-10 10

A CS

= V

, V

OUT

= V

Internal Capacitance (all inputs and outputs)

INT

— 7 pF T

AMB

= 25˚C, CLK = 1.0 MHz,

= 5.0V (Note)

Operating Current

Read —

—

500

= 5.5V; F

CLK

=3.0 MHz; SO = Open

= 2.5V; F

CLK

=2.0 MHz; SO = Open

Write —

—

5 3

mAmAV

= 5.5V

= 2.5V

Standby Current I

CCS

— —

5 1

µ A µ

= Vcc = 5.5V, Inputs tied to V

or V

CS = Vcc = 2.5V, Inputs tied to V

or V

Note: This parameter is periodically sampled and not 100% tested.

Page 3

25AA640/25LC640/25C640



1997 Microchip Technology Inc.

Preliminary

DS21223A-page 3

TABLE 1-3: AC CHARACTERISTICS

All parameters apply over the speciﬁed operating ranges unless otherwise noted.

Commercial (C): Tamb = 0 ° C to +70 ° C V

= 1.8V to 5.5V

Industrial (I): Tamb = -40 ° C to +85 ° C V

= 1.8V to 5.5V

Automotive (E): Tamb = -40 ° C to +125°C V

CC = 4.5V to 5.5V (25C640 only)

Parameter Symbol Min Max Units Test Conditions

Clock Frequency FCLK —

— —

3 2 1

MHz MHz MHz

VCC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V

CS Setup Time TCSS 100

250 500

— — —

ns ns ns

VCC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V

CS Hold Time TCSH 150

250 475

— — —

ns ns ns

VCC = 4.5V to 5.5V VCC = 2.5V to 4.5V

VCC = 1.8V to 2.5V CS Disable Time TCSD 500 — ns Data Setup Time TSU 30

50 50

— — —

ns ns ns

VCC = 4.5V to 5.5V

VCC = 2.5V to 4.5V

VCC = 1.8V to 2.5V Data Hold Time THD 50

100 100

— — —

ns ns ns

VCC = 4.5V to 5.5V

VCC = 2.5V to 4.5V

VCC = 1.8V to 2.5V CLK Rise Time TR — 2 µs (Note 1) CLK Fall Time TF — 2 µs (Note 1) Clock High Time THI 150

250 475

— — —

ns ns ns

VCC = 4.5V to 5.5V

VCC = 2.5V to 4.5V

VCC = 1.8V to 2.5V Clock Low Time TLO 150

250 475

— — —

ns ns ns

VCC = 4.5V to 5.5V

VCC = 2.5V to 4.5V

CC = 1.8V to 2.5V

Clock Delay Time TCLD 50 — ns Clock Enable Time TCLE 50 — ns Output Valid from

Clock Low

TV —

— —

150 250 475

ns ns ns

VCC = 4.5V to 5.5V

VCC = 2.5V to 4.5V

VCC = 1.8V to 2.5V Output Hold Time THO 0 — ns (Note 1) Output Disable Time TDIS —

— —

200 250 500

ns ns ns

VCC = 4.5V to 5.5V (Note 1)

VCC = 2.5V to 4.5V (Note 1)

VCC = 1.8V to 2.5V (Note 1) HOLD Setup Time THS 100

100 200

— — —

ns ns ns

VCC = 4.5V to 5.5V

VCC = 2.5V to 4.5V

VCC = 1.8V to 2.5V HOLD Hold Time THH 100

100 200

— — —

ns ns ns

VCC = 4.5V to 5.5V

VCC = 2.5V to 4.5V

VCC = 1.8V to 2.5V HOLD Low to Output High-Z THZ 100

150 200

— — —

ns ns ns

VCC = 4.5V to 5.5V (Note 1)

VCC = 2.5V to 4.5V (Note 1)

VCC = 1.8V to 2.5V (Note 1) HOLD High to Output Valid THV 100

150 200

— — —

ns ns ns

VCC = 4.5V to 5.5V

VCC = 2.5V to 4.5V

VCC = 1.8V to 2.5V Internal Write Cycle Time TWC — 5 ms Endurance — 1M — E/W Cycles (Note 2)

Note 1: This parameter is periodically sampled and not 100% tested.

2: This parameter is not tested but guaranteed by characterization. For endurance estimates in a speciﬁc application, please

consult the Total Endurance Model which can be obtained on Microchip’s BBS or website.

Page 4

25AA640/25LC640/25C640

DS21223A-page 4 Preliminary  1997 Microchip Technology Inc.

FIGURE 1-2: HOLD TIMING

FIGURE 1-3: SERIAL INPUT TIMING

FIGURE 1-4: SERIAL OUTPUT TIMING

SCK

HOLD

THH

THS THS THH

THVTHZ

don’t care

TSU

high impedance

n+2 n+1 n n-1

n+2 n+1 n

n-1

SCK

TCSS

THDTsu

TCSD

TCLD

TCSH

LSB in

MSB in

high impedance

TCLE

Mode 1,1 Mode 0,0

SCK

TLO

THI

THO

MSB out

LSB out

TCSH

TDIS

don’t care

Mode 1,1 Mode 0,0

Page 5

25AA640/25LC640/25C640

 1997 Microchip Technology Inc. Preliminary DS21223A-page 5

2.0 PIN DESCRIPTIONS

2.1 Chip Select (CS)

A low level on this pin selects the device. A high level deselects the device and forces it into standby mode. However, a programming cycle which is already initiated or in progress will be completed, regardless of the CS

input signal. If CS is brought high during a program cycle, the device will go in standby mode as soon as the programming cycle is complete. As soon as the device is deselected, SO goes to the high impedance state, allowing multiple parts to share the same SPI bus. A low to high transition on CS

after a valid write sequence initiates an internal write cycle. After powerup, a high to low transition on CS

is required prior to

any sequence being initiated.

2.2 Serial Input (SI)

The SI pin is used to transfer data into the device. It receives instructions, addresses, and data. Data is latched on the rising edge of the serial clock.

2.3 Serial Output (SO)

The SO pin is used to transfer data out of the 25xx640. During a read cycle, data is shifted out on this pin after the falling edge of the serial clock.

2.4 Serial Clock (SCK)

The SCK is used to synchronize the communication between a master and the 25xx640. Instructions, addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin is updated after the falling edge of the clock input.

2.5 Write Protect (WP)

This pin is used in conjunction with the WPEN bit in the status register to prohibit writes to the non-volatile bits in the status register. When WP

is low and WPEN is high, writing to the non-volatile bits in the status register is disabled. All other operations function normally. When WP

is high, all functions, including writes to the non-volatile bits in the status register operate normally. If the WPEN bit is set, WP

low during a status register write sequence will disable writing to the status register. If an inter nal write cycle has already begun, WP going low will have no effect on the write.

The WP

pin function is blocked when the WPEN bit in the status register is low . This allows the user to install the 25AA640/25LC640/25C640 in a system with WP pin grounded and still be able to write to the status register. The WP

pin functions will be enabled when the

WPEN bit is set high.

2.6 Hold (HOLD)

The HOLD pin is used to suspend transmission to the 25xx640 while in the middle of a serial sequence without having to re-transmit the entire sequence over at a later time. It must be held high any time this function is not being used. Once the device is selected and a serial sequence is underway, the HOLD

pin may be pulled low to pause further serial communication without resetting the serial sequence. The HOLD

pin must be brought low while SCK is low, otherwise the HOLD function will not be invoked until the next SCK high to low transition. The 25xx640 must remain selected during this sequence. The SI, SCK, and SO pins are in a high impedance state during the time the part is paused and transitions on these pins will be ignored. To resume serial communication, HOLD

must be brought high while the SCK pin is low, otherwise serial communication will not resume. Lowering the HOLD line at any time will tri-state the SO line.

Page 6

25AA640/25LC640/25C640

DS21223A-page 6 Preliminary  1997 Microchip Technology Inc.

3.0 FUNCTIONAL DESCRIPTION

3.1 PRINCIPLES OF OPERATION

The 25xx640 is a 8192 byte Serial EEPROM designed to interface directly with the Serial Peripheral Interface (SPI) port of many of today’s popular microcontroller families, including Microchip’s PIC16C6X/7X microcontrollers. It may also interface with microcontrollers that do not have a built-in SPI port by using discrete I/O lines programmed properly with the software.

The 25xx640 contains an 8-bit instruction register. The part is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The CS

pin must be low

and the HOLD

pin must be high for the entire opera-

tion. Table 3-1 contains a list of the possible instruction

bytes and format for device operation. All instructions, addresses, and data are transferred MSB ﬁrst, LSB last.

Data is sampled on the ﬁrst rising edge of SCK after CS

goes low. If the clock line is shared with other peripheral devices on the SPI bus, the user can assert the HOLD

input and place the 25xx640 in ‘HOLD’

mode. After releasing the HOLD

pin, operation will

resume from the point when the HOLD

was asserted.

3.2 Read Sequence

The part is selected by pulling CS low. The 8-bit read instruction is transmitted to the 25xx640 followed by the 16-bit address with the three MSB’s of the address being don’t care bits. After the correct read instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. The data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses . The internal address pointer is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached (1FFFh), the address counter rolls over to address 0000h allowing the read cycle to be continued indeﬁnitely. The read operation is terminated by raising the CS

pin (Figure 3-1).

3.3 Write Sequence

Prior to any attempt to write data to the 25xx640 array or status register, the write enable latch must be set b y issuing the WREN instruction (Figure 3-4). This is done by setting CS

low and then clocking out the proper instruction into the 25xx640. After all eight bits of the instruction are transmitted, the CS

must be brought high to set the write enable latch. If the write operation is initiated immediately after the WREN instruction without CS

being brought high, the data will not be written to the array because the write enable latch will not have been properly set.

Once the write enable latch is set, the user may proceed by setting the CS

low, issuing a write instruction, followed by the address, and then the data to be written. Up to 32 bytes of data can be sent to the 25xx640 before a write cycle is necessary . The only restriction is that all of the bytes must reside in the same page. A page address begins with XXX0 0000 and ends with XXX1 1111. If the internal address counter reaches XXX1 1111 and the clock continues, the counter will roll back to the ﬁrst address of the page and overwrite any data in the page that may have been written.

For the data to be actually written to the array, the CS must be brought high after the least signiﬁcant bit (D0) of the n

data byte has been clocked in. If CS is brought high at any other time, the write operation will not be completed. Refer to Figure 3-2 and Figure 3-3 for more detailed illustrations on the byte write sequence and the page write sequence respectively. While the write is in progress, the status register may be read to check the status of the WPEN, WIP, WEL, BP1, and BP0 bits (Figure 3-6). A read attempt of a memory array location will not be possible during a write cycle. When the write cycle is completed, the write enable latch is reset.

TABLE 3-1: INSTRUCTION SET

Instruction Name Instruction Format Description

READ 0000 0011 Read data from memory array beginning at selected address

WRITE 0000 0010 Write data to memory array beginning at selected address

WREN 0000 0110 Set the write enable latch (enable write operations)

WRDI 0000 0100 Reset the write enable latch (disable write operations)

RDSR 0000 0101 Read status register

WRSR 0000 0001 Write status register

Page 7

25AA640/25LC640/25C640

 1997 Microchip Technology Inc. Preliminary DS21223A-page 7

FIGURE 3-1: READ SEQUENCE

FIGURE 3-2: BYTE WRITE SEQUENCE

FIGURE 3-3: PAGE WRITE SEQUENCE

SCK

0 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 311

0 100000 1 15 14 13 12 2 1 0

7 6 5 4 3 2 1 0

instruction 16 bit address

data out

high impedance

0 000000 1 15 14 13 12 2 1 0 7 6 5 4 3 2 1 0

instruction 16 bit address data byte

high impedance

Twc

9 10 11 21 22 23 24 25 26 27 28 29 30 31

0 000000 1 15 14 13 12

2 1 0 7 6 5 4 3 2 1 0

instruction 16 bit address data byte 1

SCK

0 2 3 4 5 6 71

41 42 43 46 47

7 6 5 4 3 2 1 0

data byte n (32 max)

SCK

32 34 35 36 37 38 3933

7 6 5 4 3 2 1 0

data byte 3

7 6 5 4 3 2 1 0

data byte 2

44 45

Page 8

25AA640/25LC640/25C640

DS21223A-page 8 Preliminary  1997 Microchip Technology Inc.

3.4 Write Enable (WREN) and Write Disable (WRDI)

The 25xx640 contains a write enable latch. See Table 3-3 for the Write Protect Functionality Matrix. This latch must be set before any write operation will be completed internally. The WREN instruction will set the latch, and the WRDI will reset the latch.

The following is a list of conditions under which the write enable latch will be reset:

• Power-up

• WRDI instruction successfully executed

• WRSR instruction successfully executed

• WRITE instruction successfully executed

FIGURE 3-4: WRITE ENABLE SEQUENCE

FIGURE 3-5: WRITE DISABLE SEQUENCE

SCK

0 2 3 4 5 6 71

high impedance

0 10 0 0 0 01

SCK

0 2 3 4 5 6 71

high impedance

0 10 0 0 0 01

Page 9

25AA640/25LC640/25C640

 1997 Microchip Technology Inc. Preliminary DS21223A-page 9

3.5 Read Status Register (RDSR)

The RDSR instruction provides access to the status register. The status register may be read at any time, even during a write cycle. The status register is formatted as follows:

The Write-In-Process (WIP) bit indicates whether the 25xx640 is busy with a write operation. When set to a ‘1’ a write is in progress, when set to a ‘0’ no write is in progress. This bit is read only.

The Write Enable Latch (WEL) bit indicates the status of the write enable latch. When set to a ‘1’ the latch allows writes to the array and status register, when set to a ‘0’ the latch prohibits writes to the array and status register. The state of this bit can always be updated via the WREN or WRDI commands regardless of the state of write protection on the status register. This bit is read only.

The Block Protection (BP0 and BP1) bits indicate which blocks are currently write protected. These bits are set by the user issuing the WRSR instruction. These bits are non-volatile.

See Figure 3-6 for RDSR timing sequence

3.6 Write Status Register(WRSR)

The WRSR instruction allows the user to select one of four levels of protection for the array by writing to the appropriate bits in the status register. The array is

divided up into four segments. The user has the ability to write protect none, one, two, or all four of the segments of the array. The partitioning is controlled as illustrated in Table 3-2.

The Write Protect Enable (WPEN) bit is a non-volatile bit that is available as an enable bit for the WP

pin.

The Write Protect (WP

) pin and the Write Protect Enable (WPEN) bit in the status register control the programmable hardware write protect feature. Hardware write protection is enabled when WP

pin is low and the WPEN bit is high. Hardw are write protection is disabled when either the WP

pin is high or the WPEN bit is low. When the chip is hardware write protected, only writes to non-volatile bits in the status register are disabled. See Table 3-3 for a matrix of functionality on the WPEN bit.

See Figure 3-7 for WRSR timing sequence

TABLE 3-2: ARRAY PROTECTION

FIGURE 3-6: READ STATUS REGISTER SEQUENCE

FIGURE 3-7: WRITE STATUS REGISTER SEQUENCE

7 6 5 4 3 2 1 0

WPEN X X X BP1 BP0 WEL WIP

BP1 BP0

Array Addresses

Write Protected

0 0 none 0 1

upper 1/4

(1800h - 1FFFh)

1 0

upper 1/2

(1000h - 1FFFh)

1 1

all

(0000h - 1FFFh)

9 10 11 12 13 14 15

1 100000 0

7 6 5 4 2 1 0

instruction

data from status register

high impedance

SCK

0 2 3 4 5 6 71

9 10 11 12 13 14 15

0 100000 0

7 6 5 4 2 1 0

instruction data to status register

high impedance

SCK

0 2 3 4 5 6 71

Page 10

25AA640/25LC640/25C640

DS21223A-page 10 Preliminary  1997 Microchip Technology Inc.

3.7 Data Protection

The following protection has been implemented to prevent inadvertent writes to the array:

• The write enable latch is reset on power-up.

• A write enable instruction must be issued to set the write enable latch.

• After a byte write, page write, or status register write, the write enable latch is reset.

• CS

must be set high after the proper number of

clock cycles to start an internal write cycle.

• Access to the array during an internal write cycle is ignored and programming is continued.

3.8 Power On State

The 25xx640 powers on in the following state:

• The device is in low power standb y mode (CS

=1).

• The write enable latch is reset.

• SO is in high impedance state.

• A high to low transition on CS

is required to enter

the active state.

TABLE 3-3: WRITE PROTECT FUNCTIONALITY MATRIX

WPEN WP WEL Protected Blocks Unprotected Blocks Status Register

X X 0 Protected Protected Protected 0 X 1 Protected Writable Writable 1 Low 1 Protected Writable Protected X High 1 Protected Writable Writable

Page 11

25AA640/25LC640/25C640

 1997 Microchip Technology Inc. Preliminary DS21223A-page 11

25AA640/25LC640/25C640 PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales ofﬁce.

Sales and Support

Package:

P = Plastic DIP (300 mil Body), 8-lead

SN = Plastic SOIC (150 mil Body), 8-lead

ST = TSSOP, 8-lead

Temperature Range:

Blank = 0°C to +70°C

I = –40°C to +85°C

E = –40°C to +125°C

Devices:

25AA640 64K bit 1.8V SPI Serial EEPROM

25AA640T 64K bit 1.8V SPI Serial EEPROM Tape and Reel

25AA640X 64K bit 1.8V SPI Serial EEPROM

in alternate pinout (ST only)

25AA640XT 64K bit 1.8V SPI Serial EEPROM

in alternate pinout Tape and Reel (ST only)

25LC640 64K bit 2.5V SPI Serial EEPROM 25LC640T 64K bit 2.5V SPI Serial EEPROM Tape and Reel 25LC640X 64K bit 2.5V SPI Serial EEPROM

in alternate pinout (ST only)

25LC640XT 64K bit 2.5V SPI Serial EEPROM

in alternate pinout Tape and Reel (ST only)

25C640 64K bit 5.0V SPI Serial EEPROM 25C640T 64K bit 5.0V SPI Serial EEPROM Tape and Reel 25C640X 64K bit 5.0V SPI Serial EEPROM

in alternate pinout (ST only)

25C640XT 64K bit 5.0V SPI Serial EEPROM

in alternate pinout Tape and Reel (ST only)

25xx640 — /P

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales ofﬁce.

2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277.

3. The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).

Page 12

Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are convey ed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.

DS21223A-page 12



1997 Microchip Technology Inc.

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Microchip Asia Paciﬁc RM 3801B, To wer Two Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2-401-1200 Fax: 852-2-401-3431

India

Microchip T echnology Inc. India Liaison Ofﬁce No. 6, Legacy, Convent Road Bangalore 560 025, India Tel: 91-80-229-4036 Fax: 91-80-559-9840

Korea

Microchip T echnology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea Tel: 82-2-554-7200 Fax: 82-2-558-5934

Shanghai

Microchip T echnology RM 406 Shanghai Golden Bridge Bldg. 2077 Yan’an Road West, Hong Qiao District Shanghai, PRC 200335 Tel: 86-21-6275-5700 Fax: 86 21-6275-5060

Singapore

Microchip T echnology Taiwan Singapore Branch 200 Middle Road #07-02 Prime Centre Singapore 188980 Tel: 65-334-8870 Fax: 65-334-8850

Taiwan, R.O.C

Microchip T echnology Taiwan 10F-1C 207 Tung Hua North Road T aipei, Taiwan, ROC Tel: 886 2-717-7175 Fax: 886-2-545-0139

EUROPE

United Kingdom

Arizona Microchip Technology Ltd. Unit 6, The Courtyard Meadow Bank, Furlong Road Bourne End, Buckinghamshire SL8 5AJ Tel: 44-1628-851077 Fax: 44-1628-850259

France

Arizona Microchip Technology SARL Zone Industrielle de la Bonde 2 Rue du Buisson aux Fraises 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79

Germany

Arizona Microchip Technology GmbH Gustav-Heinemann-Ring 125 D-81739 Müchen, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44

Italy

Arizona Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-39-6899939 Fax: 39-39-6899883

JAPAN

Microchip Technology Intl. Inc. Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa 222 Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122

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