• Organized as 8 blocks of 256 bytes (8 x 256 x 8)
• 2-wire serial interface bus, I
• Schmitt trigger inputs for noise suppression
• Output slope control to eliminate ground bounce
• 100 kHz (E-temp.) and 400 kHz (C/I-temp.)
compatibility
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 16 bytes
• 2 ms typical write cycle time for page-write
• Hardware write protect for entire memory
• Can be operated as a serial ROM
• Factory programming (QTP) available
• ESD protection > 4,000V
• 1,000,000 erase/write cycles
• Data retention > 200 years
• 8-pin PDIP, SOIC, TSSOP and MSOP packages
• Available for extended temperature ranges:
- Industrial (I): -40°C to+85°C
- Automotive (E):-40°C to +125°C
2
C™ compatible
DESCRIPTION
The Microchip Technology Inc. 24LC16B is a 16 Kbit
Electrically Erasable PROM. The device is organized
as eight blocks of 256 x 8-bit memory with a 2-wire
serial interface. Low voltage design permits operation
down to 2.5V with standby and active currents of only
5 µA and 1 mA respect ively. The 24LC16B also ha s a
page-write capability for up to 16 bytes of data. The
24LC16B is availabl e in the stan dard 8-pin DIP, surface
mount SOIC, TSSOP and MSOP packages.
BLOCK DIAGRAM
I/O
CONTROL
LOGIC
I/O
SDA
V
CC
VSS
SCL
WP
MEMORY
CONTROL
LOGIC
XDEC
HV GENERATOR
EEPROM
ARRAY
PAGE LATCHES
YDEC
SENSE AMP
R/W CONTROL
PACKAGE TYPES
PDIP
A0
1
A1
2
A2
3
V
4
SS
I2C™ is a trademark of the Philips Corporation
2001 Microchip Technology Inc.DS20070M-page 1
24LC16B
8
VCC
WP
7
6
SCL
5
SDA
Note: Pins A0, A1 and A2 are not used by the 24LC16B. (No internal connections).
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temp. with power applied.................................. ...... .................................................. ..... ...........-65°C to +125°C
Soldering temperature of leads (10 seconds).......................................................................................................+300°C
ESD protection on all pins .....................................................................................................................................................≥ 4KV
† NOTICE: Stresses a bove thos e listed under “Ma ximu m ratin gs” may cause pe rmanent d amage to the devic e.
This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
1.1DC Characteristics
DC CHARACTERISTICS
SS ......................................................................................................... -0.3V to VCC +1.0V
V
CC = +2.5V to +5.5V
Industrial (I): T
Automotive (E): T
AMB = -40°C to +85°C
AMB = -40°C to +125°C
Param.
No.
D1V
D2—High level input volta ge.7 VCC—V—
D3V
D4VHYSHysteresis of Schmitt
D5V
D6ILIInput leakage current-1010µAVIN = .1V to VCC
D7ILOOutput leakage curre nt-1010µAVOUT = .1V to VCC
D8CIN,
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined T
suppression. This eliminates the need for a T
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please
consult the Total Endurance Model which can be obtained on Microchip’s website: www.microchip.com.
SP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise spike
CC = +2.5V to +5.5V
Industrial (I): T
Automotive (E): T
—
4000
4700
—
—
1000
600
4000
600
4700
250
600
4000
—
—
3500
1300
4700
20+0.1C
B
—
400
100
—
—
—
—
300
—
—
—
—
—
—
—
—
900
—
—
250
250
AMB = -40°C to +85°C
AMB = -40°C to +125°C
kHz2.5V ≤ VCC≤ 5.5V
ns2.5V ≤ VCC≤ 5.5V
ns2.5V ≤ VCC≤ 5.5V
ns2.5V ≤ VCC≤ 5.5V (Note 1)
ns2.5V ≤ VCC≤ 5.5V
ns2.5V ≤ VCC≤ 5.5V
ns2.5V ≤ VCC≤ 5.5V
ns2.5V ≤ VCC≤ 5.5V
ns2.5V ≤ VCC≤ 5.5V
ns2.5V ≤ VCC≤ 5.5V
ns2.5V ≤ V
—50ns(Notes 1 and 3)
—5ms—
I specification for standard operation.
2.5V ≤ V
2.5V ≤ V
2.5V ≤ V
2.5V ≤ V
(Note 1)
2.5V ≤ V
2.5V ≤ V
2.5V ≤ V
2.5V ≤ V
2.5V ≤ V
2.5V ≤ V
2.5V ≤ V
(Note 4)
24LC16B
CC≤ 5.5V (E-temp. range)
CC≤ 5.5V (E-temp. range)
CC≤ 5.5V (E-temp. range)
CC≤ 5.5V (E-temp. range)
CC≤ 5.5V (E-temp. range)
CC≤ 5.5V (E-temp. range)
CC≤ 5.5V (E-temp. range)
CC≤ 5.5V (E-temp. range)
CC≤ 5.5V (E-temp. range)
CC≤ 5.5V (E-temp. range)
CC≤ 5.5V
CC≤ 5.5V (E-temp. range)
CC = 5.0V, Block Mode
2001 Microchip Technology Inc.DS20070M-page 3
Page 4
24LC16B
FIGURE 1-1:BUS TIMING DATA
5
3
SCL
7
SDA
IN
SDA
OUT
14
6
FIGURE 1-2:BUS TIMING START/STOP
SCL
7
SDA
6
2
8
9
11
D4
4
10
12
10
STARTSTOP
DS20070M-page 4 2001 Microchip Technology Inc.
Page 5
24LC16B
2.0FUNCTIONAL DESCRIPTION
The 24LC16B supports a bi-directional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving dat a as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCL), controls the bus access and generates the
START and STOP conditions, while the 24LC16B
works as slave. Both master and slave can operate as
transmitter or receiver, but the master device determines which mode is activated.
3.0BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whene ver the cloc k line i s HIG H. Chang es
in the data l ine while the clock lin e i s HI GH w ill be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is H IGH determines a START condition.
All commands must be preceded by a START condition.
3.3Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
3.4Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clo ck sign al. Th ere is one c lock pulse p er
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The n um ber of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoreti cally u nlimited , althoug h only the las t sixteen will be stor ed when doing a write oper ation. When
an overwrite does occur it will replace data in a first-in
first-out (FIFO) fashion.
3.5Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The ma ster devi ce m ust gener at e an ex tr a cloc k
pulse which is associated with this acknowledge bit.
Note:The 24LC16B does not generate any
acknowledge bits if an internal programming cy cle is in progress.
The device that acknowledges, has to pull down the
SDA line during the ackn owledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the sl av e b y n ot generating an acknowledg e b it
on the last byte that has be en c locked out of the slave.
In this case, the slave (24LC16B) will leave the data
line HIGH to enable the master to generate the STOP
condition.
FIGURE 3-1:DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)(B)(D)(D)(A)(C)
SCL
SDA
START
CONDITION
2001 Microchip Technology Inc.DS20070M-page 5
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
Page 6
24LC16B
3.6Device Addressing
A control byte is the first byte received following the
start conditi on from t he mast er device. The contr ol byte
consists of a fou r bit con trol co de, for th e 24LC 16B this
is set as
The next three bits of the control byte are the block
select bits (B2, B1, B0). They are used by the master
device to select which of the eight 256 word blocks of
memory are to be access ed. These bits are in effect the
three most significant bits of the word address. It
should be noted that the protocol limits the size of the
memory to eight blocks of 256 word s, therefore the protocol can support only one 24LC16B per system.
The last bit of the control byte defines the operation to
be performed. When set to ‘
selected, when set to ‘
Following the START condition, the 24LC16B mon itors
the SDA bus checking the device type identifier being
transmitted, upon a
puts an acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24LC16B will select
a read or write operation.
Operation
1010 binary for read and write operations.
1’ a read operation is
0’ a write operation is selected.
1010 code the slave device out-
Read
Write
Control
Code
1010
1010
Block SelectR/W
Block Address
Block Address
1
0
FIGURE 3-2:CONTROL BYTE
ALLOCATION
STARTREAD/WRITE
SLAVE ADDRESS
1010B2B1B0
X = Don’t care
R/W
A
DS20070M-page 6 2001 Microchip Technology Inc.
Page 7
24LC16B
4.0WRITE OPERATION
4.1Byte Write
Following the START condition from the master, the
device code (4 bits), the block address (3 bits) and the
R/W
bit which is a logic LO W i s p lac ed ont o the bus by
the master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow after it has generated an acknowl edge bit during
the ninth clock cycl e. Therefore, th e next byte trans mitted by the master is the word address and will be written into the address pointer of the 24LC16B. After
receiving another acknowledge signal from the
24LC16B, the master de vice will tran smit the dat a word
to be written into the addressed memory location. The
24LC16B acknowledges again and the master generates a STOP condition. This initiates the internal write
cycle, and during this time the 24LC 16B will not generate acknowledge signals (Figure 4-1).
4.2Page Write
The write control byte, word address and the first data
byte are transmitted to the 24LC16B in the same way
as in a byte write. But instead of generating a STOP
condition the master transmits up to 16 data bytes to
the 24LC16B, which are temporarily stored in the onchip page buffer and will be written into the memory
after the master has transmitted a STOP condition.
After the receipt of each word, the four lower order
address pointer bits are internally incremented by ‘
1’.
The higher order 7 bits of the word address remains
constant. If the master should transmit more than 16
words prior to generating the STOP condition, the
address counter will roll over and the previously
received data will be overwri tten. As w ith the by te writ e
operation, once the STOP condition is received an
internal write cycle will begin (Figure 4-2).
Note: Page write operations a re limited to writ-
ing bytes within a single physical page,
regardless of the number of by tes ac tually being written. Physical page boundaries start at addresses that are integer
multiples of the page buffer size (or
‘page size’) and end at addresses that
are integer multiples of [pa ge size - 1]. If
a page write co mm and at tem pts to write
across a physical page boundary, the
result is that the data wraps around to
the beginning of the current page (overwriting data previously stored there),
instead of being wr itt en to th e n ex t p a ge
as might be expected. It is therefore
necessary for the application software to
prevent page write operations that
would attempt to cross a page bo undary .
FIGURE 4-1:BYTE WRITE
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
T
A
R
T
SP
CONTROL
S
FIGURE 4-2:PAGE WRITE
S
T
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
CONTROL
A
BYTE
R
T
SP
BYTE
A
C
K
WORD
ADDRESS (n)
A
C
K
WORD
ADDRESS
A
C
K
DATA (n)DATA (n + 15)
A
C
K
DATA (n + 1)
A
C
K
DATA
A
C
K
S
T
O
P
A
C
K
S
T
O
P
A
C
K
2001 Microchip Technology Inc.DS20070M-page 7
Page 8
24LC16B
5.0ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once th e STOP condition for a wri te com mand has been issued from the master, the device initiates the internally timed write cycle. ACK polling can
be initiated immedi ately . This in volves the master s ending a start condition followed by the control byte for a
write command (R/W
the write cycle, then no ACK will be returned. If the
cycle is complete, then the device will return the ACK
and the master can then proceed with the next read or
write command. See Figure 5-1 for flow diagram.
FIGURE 5-1:ACKNOW LEDGE POLLING
= 0). If the device is still busy with
FLOW
Send
Write Command
Send Stop
Condition to
Initiate Wr ite Cycle
6.0WRITE PROTECTION
The 24LC16B can be used as a serial ROM when the
WP pin is connected to V
inhibited and the entire memory will b e writ e-protec ted.
CC. Programming will be
Send Start
Send Control Byte
with R/W
Acknowledge
= 0
Did Device
(ACK = 0)?
Yes
Next
Operation
No
DS20070M-page 8 2001 Microchip Technology Inc.
Page 9
24LC16B
7.0READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W
slave address is se t to ‘
1’. There are three basic ty pes
of read operations: current add ress read, ran dom read
and sequential read.
7.1Current Address Read
The 24LC16B contains an address counter that maintains the address of the last word accessed, internally
incremented by ‘
1’. Therefore, if the previous access
(either a read or write operation) was to address
next current address read operati on would access da ta
from address
with R/W
n + 1. Upon receipt o f the slave addres s
bit set to ‘1’, the 24 LC16B issues an acknowledge and transmits the 8-b it data w ord. The master will
not acknowledge the transfer but does generate a
STOP condition and the 24LC16B discontinues transmission (Figure 7-1).
7.2Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operatio n, fi rst the word address must
be set. This is d one by sending the word a ddress to the
24LC16B as part of a write operation. After the word
address is sent, the master generates a START condition following the acknowledge. This terminates the
write operation, but not before the internal address
pointer is set. Then the master issues the control byte
again but with the R/W
then issue an acknow ledge and tran smits the 8-bit data
word. The master will n ot acknow ledg e the tra nsfer but
does generate a ST OP conditio n and the 24LC16 B discontinues transmission (Figure 7-2).
bit set to a ‘1’. The 24LC16B wil l
bit of the
n, the
7.3Sequential Read
Sequential reads are ini tiated in the sam e way as a random read except that after the 24LC16B transmits the
first data byte, the master issues an acknowledge as
opposed to a STOP condition in a random read. This
directs the 24LC16B to transmit the next sequentially
addressed 8-bit word (Figure 7-3).
To provide sequential reads the 24LC16B contains an
internal address poin ter which is i ncremented by o ne at
the completion of ea ch operation. This address pointer
allows the entire memory contents to be serially read
during one operation.
7.4Noise Protection
The 24LC16B emp loys a VCC threshold detector circuit
which disables the internal erase/write logic if the V
is below 1.5V at nominal conditions.
The SCL and SDA inputs have Sch mitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.
CC
FIGURE 7-1:CURRENT ADDRESS READ
S
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
2001 Microchip Technology Inc.DS20070M-page 9
T
A
R
T
SP
CONTROL
BYTE
S
DATA (n)
A
C
K
T
O
P
N
O
A
C
K
Page 10
24LC16B
FIGURE 7-2:RANDOM READ
S
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
T
CONTROL
A
BYTE
R
T
SP
FIGURE 7-3:SE QUENTIAL READ
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
CONTROL
BYTE
DATA (n)DATA (n + 1)DATA (n + 2)DATA (n + X)
A
C
K
WORD
ADDRESS (n)
A
C
K
A
C
K
A
C
K
S
T
A
R
T
S
A
C
K
CONTROL
BYTE
A
C
K
A
C
K
DATA (n)
S
T
O
P
N
O
A
C
K
S
T
O
P
P
N
O
A
C
K
DS20070M-page 10 2001 Microchip Technology Inc.
Page 11
8.0PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 8-1.
This is a bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal. Therefore, t he SDA bus r equires a pullup resistor t o V
400 kHz).
For normal data t ransfer SDA is all owed to change only
during SCL LOW. Changes during SCL HIGH are
reserved for indicating the START and STOP conditions.
CC (typical 10 kΩ for 100 k Hz , 2 kΩ for
24LC16B
8.2Serial Clock (SCL)
This input is u sed t o sy nchron ize the d ata trans fer fro m
and to the device.
8.3Write-Protec t (W P)
This pin must be connected to either VSS or VCC.
If tied to V
(read/write the entire memo ry
If tied to V
entire memory will be w rite-prot ected. Read op erations
are not affected.
This feature allows the user to use the 24LC16B as a
serial ROM when WP is enabled (tied to V
SS normal memory operation is enabled
000-7FF).
CC, WRITE operations are inhibited. The
CC).
8.4A0, A1, A2
These pins are not used by the 24LC16B. The y may be
left floating or tied to either V
SS or VCC.
2001 Microchip Technology Inc.DS20070M-page 11
Page 12
24LC16B
9.0PACKAGING INFORMATION
9.1Package Marking Information
8-Lead PDIP (300 mil)
XXXXXXXX
XXXXXNNN
YYWW
8-Lead SOIC (150 mil)
XXXXXXXX
XXXXYYWW
NNN
8-Lead TSSOP
XXXX
XYWW
NNN
Example:
24LC16B
/PNNN
YYWW
Example:
24LC16B
SNYYWW
NNN
Example:
4L16
YWW
NNN
8-Lead MSOP
XXXXXX
YWWNNN
Legend: XX...X Customer specific information*
YYear code (last digit of calendar year)
YYYear code (last 2 digits of calendar year)
WWWeek code (week of January 1 is week ‘01’)
NNNAlphanumeric traceability code
Note:In the event the full Microchip p art numb er ca nnot be mark ed on one l ine, it w ill
be carried over to the next line thus limiting the number of available cha rac ters
for customer specific information.
*Standard PICmicro device marking consists of Microchip part number, year code, week code, and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
Example:
4L16I
YWWNNN
DS20070M-page 12 2001 Microchip Technology Inc.
Page 13
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
24LC16B
n
E
β
eB
Number of Pins
Pitch
Top to Seating PlaneA.140.155.1703.563.944.32
Molded Package ThicknessA2.115.130.1452.923.303.68
Base to Seating PlaneA1.0150.38
Shoulder to Shoulder WidthE.300.313.3257.627.948.26
Molded Package WidthE1.240.250.2606.106.356.60
Overall LengthD.360.373.3859.149.469.78
Tip to Seating PlaneL.125.130.1353.183.303.43
Lead Thickness
Upper Lead WidthB1.045.058.0701.141.461.78
Lower Lead WidthB.014.018.0220.360.460.56
Overall Row Spacing§eB.310.370.4307.879.4010.92
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
Dimension LimitsMINNOMMAXMINNOMMAX
1
α
A
c
UnitsINCHES*MILLIMETERS
n
p
c
α
β
.008.012.0150.200.290.38
A1
B1
B
88
.1002.54
51015 51015
51015 51015
A2
L
p
2001 Microchip Technology Inc.DS20070M-page 13
Page 14
24LC16B
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
B
Number of Pins
Pitch
Foot Angle
Lead Thickness
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-086
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .010" (0.254mm) per side.
Units
n
p
A
A2
A1
E
E1
D
L
φ
c
B
α
β
MILLIMETERS*
MINMAX
0.81
0.05
2.95
2.95
0.40
0
0.13
0.25
NOM
8
0.65 TYP.
0.86
4.90 TYP.
3.00
3.00
0.55
0.15
0.30
7
7
MAX
1.10
0.91
0.15
3.05
3.05
0.70
1.000.950.90.039
0.18
0.40
6
DS20070M-page 16 2001 Microchip Technology Inc.
Page 17
24LC16B
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip
World Wide Web (WWW) site.
The web site is used b y Mic rochip as a me ans to m ake
files and information easily available to customers. To
view the site, the use r must have access to the Intern et
and a web browser, such as Netscape
Explorer. Files are also available for FTP download
from our FTP site.
Connecting to the Microchip Internet Web Site
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP service to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User’s Guides, Articles and Sample Programs. A variety of Micr ochip specific bu siness informatio n is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for prod ucts, D evelopment Systems,
technical information and more
• Listing of seminars and events
®
or Microsoft
Systems Information and Upgrade Hot Line
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive any currently available upgrade kits.The
®
Hot Line Numbers are:
1-800-755-2345 for U.S. and most of Canada, and
1-480-792-7302 for the rest of the world.
2001 Microchip Technology Inc.DS20070M-page 17
Page 18
24LC16B
READER RESPONSE
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24LC16B
Literature Number:
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DS20070M
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DS20070M-page 18 2001 Microchip Technology Inc.
Page 19
NOTES:
24LC16B
2001 Microchip Technology Inc.DS20070M-page 19
Page 20
24LC16B
NOTES:
DS20070M-page 20 2001 Microchip Technology Inc.
Page 21
NOTES:
24LC16B
2001 Microchip Technology Inc.DS20070M-page 21
Page 22
24LC16B
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.X/XX
Device
PackageTemperature
Range
Device:24LC16B: = 16 Kbit I2C Serial EEPROM
24LC16BT: = 16 Kbit I
Temperature
Range:
Package:P=Plastic DIP (300 mil body), 8-lead
I=-40°C to +85°C
E=-40°C to +125°C
SN=Plastic SOIC (150 mil body), 8-lead
ST=Plastic TSSOP (4.4 mm), 8-lead
MS=Plastic Micro Small Outline (MSOP), 8-lead
2
(Tape and Reel)
C Serial EEPROM
Examples:
a)24LC16B-E/P: Extended Temp.,
PDIP package
b)24LC16B-E/SN: Extended Temp.,
SOIC package
c)24LC16BT - E/SN: Tape and Reel,
Extended Temp., SOIC package
d)24LC16B-I/P: Industrial Temp.,
PDIP package
e)24LC16B-I/SN: Industrial Temp.,
SOIC package
f)24LC16BT-I/SN: Tape and Reel,
Industrial Temp., SOIC package
g)24LC16B-I/ST: Industrial Temp.,
TSSOP package
h)24LC16BT-I/ST: Tape and Reel,
Industrial Temp., TSSOP package
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Data Sheets
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The Microchip name, logo, PIC, PICmicro,
PICMASTER, PICSTART, PRO MATE, K
EELOQ,
SEEV AL, MPLAB and The Embedded Contr ol
Solutions Company are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and
other countries.
Total Endurance, ICSP, In-Circuit Serial Programming,
FilterLab, MXDEV, microID, FlexROM, fuzzyLAB,
MPASM, MPLINK, MPLIB, PICDEM, ICEPIC,
Migratable Memory, FanSense, ECONOMONITOR,
Select Mode and microPort are trademarks of
Microchip Technology Incorporated in the U.S.A.
Serialized Quick Term Programming (SQTP) is a
service mark of Microchip Technology Incorporated in
the U.S.A.
All other trademarks mentioned herein are property of
their respective compa ni es.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
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Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
2001 Microchip Technology Inc.DS20070M-page 23
®
8-bit MCUs, KEELOQ
®
code hopping
Page 24
M
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ASIA/PACIFIC (continued)
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updates. It is your respo nsibilit y to en sure t hat you r app licatio n mee ts with y our sp ecifica tions . No re presen tation or warra nty is given and n o liability is
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DS20070M-page 24 2001 Microchip Technology Inc.
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