• Single supply with operation down to 1.7V for
24AA08 devices, 2.5V for 24LC08B dev i ces
• Low-power CMOS technology:
- Read current 1 mA, typical
- Standby current 1 μA, typical
• 2-wire serial interface, I2C™ compatible
• Schmitt Trigger inputs for noise suppression
• Output slope control to eliminate ground bounce
• 100 kHz and 400 kHz clock compatibility
• Page write time 3 ms, typical
• Self-timed erase/write cycle
• 16-byte page write buffer
• Hardware write-protect
• ESD protection >4,000V
• More than 1 million erase/write cycles
• Data retention >200 years
• Factory programming available
• Packages include 8-lead PDIP, SOIC, TSSOP,
DFN, MSOP and 5-lead SOT-23
• Pb-free and RoHS compliant
• Temperature ranges:
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
Description:
The Microchip Technology Inc. 24AA08/24LC08B
(24XX08*) is a 8 Kbit Elec trically Erasable PROM . The
device is organized as four blocks of 256 x 8-bit
memory with a 2-wire serial interface. Low-voltage
design permits operation down to 1.7V, with standby
and active currents of only 1 μA and 1 mA,
respectively. The 24XX08 also has a page write
capability for up to 16 bytes of data. The 24XX08 is
available in the standard 8-pin PDIP, surface mount
SOIC, TSSOP, 2x3 DFN and MSOP packages, and is
also available in the 5-lead SOT-23 package. All
packages are Pb-free and RoHS compliant.
Block Diagram
HV
Generator
EEPROM
Array
Page
Latches
YDEC
Sense Amp.
R/W Control
Control
Logic
I/O
SDA
V
VSS
CC
I/O
SCL
WP
Memory
Control
Logic
XDEC
Package Types
A0
A1
A2
V
SS
SOIC, TSSOP
1
2
3
4
8
CC
V
7
WP
6
SCL
5
SDA
PDIP, MSOP
1
A0
2
A1
3
A2
SS
4
V
8
VCC
WP
7
SCL
6
SDA
5
SOT-23-5
15
SCL
2
Vss
3
SDA
*24XX08 is used in this document as a generic part
number for the 24AA08/24LC08B devices.
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-40°C to +125°C
ESD protection on all pins ......................................................................................................................................................≥ 4kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at those or any other conditions
above those indica ted in the opera tional li stings of this sp ecification is not i mplied. Ex posure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-1:DC CHARACTERISTICS
DC CHARACTERISTICS
Param.
No.
D1V
D2—High-level input voltage0.7 VCC——V—
D3V
D4VHYSHysteresis of Schmitt
D5V
D6ILIInput leakage current——±1μAVIN = .1V to VCC
D7ILOOutput leakage current——±1μAVOUT = .1V to VCC
D8CIN,
The 24XX08 supports a bidirectional, 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, while a device
receiving data is defined as a receiver. The bus has to
be controlled by a master device which generates the
Serial Clock (SCL), controls the bus access and
generates the Start and Stop conditions, while the
24XX08 works as slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is activated.
3.0BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable wheneve r the c lock lin e is high . Changes i n
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1Bus Not Busy (A)
Both data and clock lines remain high.
3.2Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
3.3Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
3.4Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a S tart condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is
theoretically unlimited, although only the last sixteen
will be stored when doing a write operation. When an
overwrite does occu r it will replac e data in a first-in firstout (FIFO) fashion.
3.5Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The ma ster devi ce m ust gener at e an ex tr a cloc k
pulse which is associated with this Acknowledge bit.
Note:The 24XX08 does not generate any
Acknowledge bits if an internal programming cycle is in progress.
The device that acknowledges, has to pull down the
SDA line during the ackn owledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the sla ve by no t gene rating a n Ack nowl edge b it
on the last byte that has be en c loc ke d ou t of th e sl av e.
In this case, the sl ave (24 XX08) will leave the data lin e
high to enable the master to generate the Stop
condition.
FIGURE 3-1:DATA TRANSFER SEQUENCE ON THE SERIAL BUS
A control byte is the first byte received following the
Start condition from the master device (Figure 3-2).
The control byte co nsi sts of a four-bit control cod e. For
the 24XX08, this is set as ‘
write operations. The ne xt th ree bits of the control byte
are the block-select bits (B2, B1, B0). B2 is a “don’t
care” for the 24XX08. They are used by the master
device to select which of the four 256 word-blocks of
memory are to be access ed. These bits are in effect the
three Most Significant bits of the word address.
The last bit of the control byte defines the operation to
be performed. When set to ‘
selected. When set to ‘
Following the Start condition, the 24XX08 monitors the
SDA bus, checking the device type identifier being
transmitted and, upon receiving a ‘
slave device outputs an Acknowledge signal on the
SDA line. Depending on the state of the R/W bit, the
24XX08 will select a read or write operation.
Following the Start condition from the master, the
device code (4 bits), the block address (3 bits) and the
R/W bit, which is a logic-low, is placed onto the bus by
the master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will
follow once it has generated an Ack nowledge bit d uring
the ninth clock cycl e. Therefore, th e next byte trans mitted by the master is the word address and will be
written into the Address Pointer of the 24XX08. After
receiving another Acknowledge signal from the
24XX08, the master device will transmit the data word
to be written into the addressed memory location. The
24XX08 acknowledges again and the master
generates a Stop condition. This initiates the internal
write cycle and, during this time, the 24XX08 will not
generate Acknowledge signals (Figure 4-1).
4.2Page Write
The write control byte, word address and the first data
byte are transmitted to the 24 XX08 in th e same w ay a s
in a byte write. However, instead of generating a Stop
condition, the master transmits up to 16 data bytes to
the 24XX08, which are temporarily stored in the onchip page buffer and will be written into memory once
the master has transmitted a Stop condition. Upon
receipt of each word, the four lower-order Address
Pointer bits are internally incremented by ‘
higher-order 7 bits of the word address remain
constant. If the master should transmit more than 16
words prior to generating the Stop condition, the
address counter will roll over and the previously
received data will be overwri tten. As w ith the by te writ e
operation, once the Stop condition is received an
internal write cycle will begin (Figure 4-2).
Note:Page write operations are limite d to writin g
bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buf fer size (or
‘page-size’) and end a t ad dresses that a re
integer multiples of [page size – 1]. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page, as might b e
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
command has been issu ed from the mas ter , the device
initiates the int ernally-timed wri te cycle and ACK pol ling
can then be initiated immediately. This involves the
master sending a S tart c ondition fo llowed by t he contro l
byte for a Write c ommand (R/W
busy with the write cycle, no ACK will be returned. If the
cycle is complete, the device will return the ACK and
the master can then proceed with the next Read or
Write command. See Figure 5-1 for a flow diagram of
this operation.
FIGURE 5-1:ACKNOWLEDGE POLLING
FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
= 0). If the device is still
6.0WRITE PROTECTION
The WP pin a llows t he user to wri te-prot ect the entire
array (000-3FF) when the pin is tied to V
tied to V
Read operations are initiated in the same way as write
operations, with the exception that the R/W
slave address is set to ‘
of read operations: current addr ess read , rand om rea d
and sequential read.
1’. There are three basic types
7.1Current Address Read
The 24XX08 contains an address counter that maintains the address of the last word accessed, internally
incremented by ‘
(either a read or write operation) was to address
next current address read operati on would access da ta
from address
with R/W
edge and transmits the 8-b it data w ord. The master will
not acknowledge the tra nsfer , but does generate a Stop
condition and the 24XX08 discontinues transmission
(Figure 7-1).
bit set to ‘1’, the 24XX08 issues an acknowl-
1’. Therefore, if the previous access
n + 1. Upon receipt o f the slave addres s
7.2Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operatio n, th e w ord add ress m us t firs t
be set. This is accomplished by sending the word
address to the 24XX08 as part of a write operation.
Once the word address is sent , the master ge nerates a
Start condition following the acknowledge. This
terminates the write operation, but not before the
internal Address Pointe r is se t. The m aster th en issue s
the control byte again, but with the R/W
The 24XX08 will then i ssue an ack nowledge a nd transmit the 8-bit data word. The master will not acknowledge the transfer, but does generate a Stop condition
and the 24XX08 will discontinue transmission
(Figure 7-2).
bit of the
n, the
bit set to a ‘1’.
7.3Sequential Read
Sequential reads are initiated in the same way as a
random read, except that once the 24XX08 transmits
the first data byte, the master issues an acknowledge
as opposed to a Stop condition in a random read. This
directs the 24XX08 to transmit the next sequentiallyaddressed 8-bit word (Figure 7-3).
To provide se quential read s, the 24XX08 co ntains an
internal Address Pointer that is incremented by one
upon completion of each operation. This Address
Pointer allows the entire memory contents to be serially
read during one operation.
7.4Noise Protection
The 24XX08 employs a VCC threshold detector circuit
which disables the internal erase/write logic if the V
is below 1.5V at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation, even on a noisy bus.
V
SDA555553Serial Address/Data I/O
SCL666661Serial Clock
WP777775Write-Protect Input
CC888884+1.7V to 5.5V Power Supply
V
8.1Serial Address/Data Input/Output
(SDA)
SDA is a bidirectional pin used to transfer addresses
and data into and out of the de vice . Sinc e it i s an opendrain terminal, the SDA bus requires a pull-up resistor
CC (typical 10 kΩ for 100 kHz, 2 kΩ for 400 kHz).
to V
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating Start and Stop conditions.
8.2Serial Clock (SCL)
The SCL input is used to sync hro ni ze th e da t a tra ns fer
to and from the device.
8.3Write-Protect (WP)
The WP pin must be connected to either VSS or VCC.
If tied to V
(read/write the entire memory 000-03FF).
If tied to V
memory will be write-protected. Read operations are
not affected.
This feature allows the user to use the 24XX08 as a
serial ROM when WP is enabled (tied to V
SS, normal memory operation is enabled
CC, write operations are inhibited. The entire
CC).
8.4A0, A1, A2
The A0, A1 and A2 pins are not used by the 24XX08.
They may be left floating or tied to either V
TTemperature (I, E)
YYear code (last digit of calendar year)
YYYear code (last 2 digits of calendar year)
WWWeek code (week of January 1 is week ‘01’)
NNNAlphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC designator for Matte Tin (Sn)
3
e
Note:For very small packages with no room for the Pb-free JEDEC designator
, the marking will only appear on the outer carton or reel label.
3
e
Note:In the event the full Microchip part num ber cann ot be marked on one lin e, it will
be carried over to the next line, thus limiting the number of available
character s for customer-specific information.
SOT-23DFN
I-TempE-TempI-TempE-Temp
*Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.
8-Lead Plastic Dual In-Line (P or PA) – 300 mil Body [PDIP]
N
1
2
3
4
B
Note:For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
N
otes:
. Pin 1 visual index feature may vary, but must be located with the hatched area.
. § Significant Characteristic.
. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
NOTE 1
E1
12
A
A1
b1
b
Number of PinsN8
Pitche.100 BSC
Top to Seating PlaneA––.210
Molded Package ThicknessA2.115.130.195
Base to Seating PlaneA1.015––
Shoulder to Shoulder WidthE.290.310.325
Molded Package WidthE1.240.250.280
Overall LengthD.348.365.400
Tip to Seating PlaneL.115.130.150
Lead Thicknessc.008.010.015
Upper Lead Widthb1.040.060.070
Lower Lead Widthb.014.018.022
Overall Row Spacing §eB––.430
8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP]
N
1
2
3
B
Note:For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
N
E
E1
NOTE 1
12
b
e
c
A
A1
Number of PinsN8
Pitche0.65 BSC
Overall HeightA––1.20
Molded Package ThicknessA20.801.001.05
Standoff A10.05–0.15
Overall WidthE6.40 BSC
Molded Package WidthE14.304.404.50
Molded Package LengthD2.903.003.10
Foot LengthL0.450.600.75
FootprintL11.00 REF
Foot Angleφ0°–8°
Lead Thicknessc0.09–0.20
Lead Widthb0.19–0.30
otes:
. Pin 1 visual index feature may vary, but must be located within the hatched area.
. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
8-Lead Plastic Micro Small Outline Package (MS or UA) [MSOP]
Note:For the most current package drawings, please see the Microchip Packaging Specification located at
B
http://www.microchip.com/packaging
D
N
E
E1
NOTE 1
2
1
e
24AA08/24LC08B
b
A
A1
Number of PinsN8
Pitche0.65 BSC
Overall HeightA––1.10
Molded Package ThicknessA20.750.850.95
Standoff A10.00–0.15
Overall WidthE4.90 BSC
Molded Package WidthE13.00 BSC
Overall LengthD3.00 BSC
Foot LengthL0.400.600.80
FootprintL10.95 REF
Foot Angleφ0°–8°
Lead Thicknessc0.08–0.23
Lead Widthb0.22–0.40
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5-Lead Plastic Small Outline Transistor (OT or CT) [SOT -23]
N
1
2
B
Note:For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
N
1
A
A1
2
e
e1
D
b
E
E1
3
A2
c
L
L1
φ
UnitsMILLIMETERS
Dimension LimitsMINNOMMAX
Number of PinsN5
Lead Pitche0.95 BSC
Outside Lead Pitche11.90 BSC
Overall HeightA0.90–1.45
Molded Package ThicknessA20.89–1.30
StandoffA10.00–0.15
Overall WidthE2.20–3.20
Molded Package WidthE11.30–1.80
Overall LengthD2.70–3.10
Foot LengthL0.10–0.60
FootprintL10.35–0.80
Foot Angleφ0°–30°
Lead Thicknessc0.08–0.26
otes:
. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.127 mm per side.
. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
8-Lead Plastic Dual Flat, No Lead Package (MC) – 2x3x0.9 mm Body [DFN]
N
1
2
3
4
B
Note:For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
N
L
b
K
E
EXPOSED PAD
NOTE 1
2
1
TOP VIEW
A
A3A1
Number of PinsN8
Pitche0.50 BSC
Overall HeightA0.800.901.00
Standoff A10.000.020.05
Contact ThicknessA30.20 REF
Overall LengthD2.00 BSC
Overall WidthE3.00 BSC
Exposed Pad LengthD21.30–1.75
Exposed Pad WidthE21.50–1.90
Contact Widthb0.180.250.30
Contact LengthL0.300.400.50
Contact-to-Exposed PadK0.20––
otes:
. Pin 1 visual index feature may vary, but must be located within the hatched area.
. Package may have one or more exposed tie bars at ends.
. Package is saw singulated.
. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
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Note the following details of the code protection feature on Microchip devices:
•Microchip products meet the specification contained in their particular Microchip Data Sheet.
•Microchip believes that it s family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•Microchip is willing to work with the customer who is concerned about the integrity of their code.
•Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are com mitted to continuously improving the code protect ion f eatures of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digit al Mill ennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
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The Microchip name and logo, the Microchip logo, Accuron,
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EELOQ, KEELOQ logo, microID, MPLAB, PIC,
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