Datasheet 227c256b Datasheet

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Page 1

256 Kbit (32Kb x 8) UV EPROM and OTP EPROM

■ 5V ± 10% SUPPLY VOLTAGE in READ

OPERATION

■ ACCESS TIME: 45ns

■ LOW POWER CONSUMPTION:

– Active Current 30mA at 5MHz – Standby Current 100µA

■ PROGRAMMING VOLTAGE: 12.75V ± 0.25V

■ PROGRAMMING TIME: 100µs/word

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h – Device Code: 8Dh

DESCRIPTION

The M27C256B is a 256 Kbit EPROM offered in the two ranges UV (ultra violet erase) and OTP (one timeprogrammable). Itis ideally suitedformicroprocessor systems and is organized as32,768 by 8 bits.

The FDIP28W (window ceramic frit-seal package) has a transparent lid which allows the user to expose thechipto ultraviolet lightto erase thebitpattern. A new pattern can then be written to the device by following the programmingprocedure.

For applications where the content is programmed only one time and erasure is not required, the M27C256B is offered in PDIP28, PLCC32 and TSOP28 (8 x 13.4 mm) packages.

M27C256B

8 x 13.4 mm

FDIP28W (F) PDIP28 (B)

PLCC32 (C) TSOP28 (N)

Figure 1. Logic Diagram

A0-A14 Q0-Q7

M27C256B

AI00755B

1/16April 2001

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M27C256B

Figure 2A. DIP Connections

A12

7 A2 A1 A0

Q2 SS

M27C256B

28 27 26 25 24 23 22 21 20 19 18 17 16 15

AI00756

A14 A13 A8 A9 A11 G A10 E Q7 Q6 Q5Q1 Q4 Q3V

Figure 2B. LCC Connections

A6 A5 A4 A3 A2 A1 A0

A12

M27C256B

A14

A13

A8 A9 A11 NC G A10 E Q7 Q6

AI00757

Figure 2C. TSOP Connections

A11

A8 A13 A14

A12

M27C256B

AI00614B

15 14

A10 E Q7 Q6 Q5 Q4 Q3 V

Q2 Q1 Q0 A0 A1 A2

Table 1. Signal Names

A0-A14 Address Inputs Q0-Q7 Data Outputs E Chip Enable G Output Enable V

NC Not Connected Internally DU Don’t Use

Program Supply Supply Voltage Ground

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M27C256B

Table 2. Absolute Maximum Ratings

(1)

Symbol Parameter Value Unit

BIAS

STG

(2)

Note: 1. Except for the rating ”Operating Temperature Range”, stressesabove those listed in the Table ”Absolute Maximum Ratings” may

cause permanent damage to the device. These are stress ratings only and operation of the device atthese or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Referalso tothe STMicroelectronics SUREProgram and otherrelevant quality documents.

2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC voltage on Output is V

3. Depends on range.

Ambient Operating Temperature Temperature Under Bias –50 to 125 °C Storage Temperature –65 to 150 °C

Input or Output Voltage (except A9) –2 to 7 V Supply Voltage –2 to 7 V A9 Voltage –2 to 13.5 V Program Supply Voltage –2 to 14 V

+0.5V withpossible overshoot to VCC+2V for a period less than20ns.

(3)

–40 to 125 °C

Table 3. Operating Modes

Mode E G A9

Read Output Disable V Program

V Verify V Program Inhibit Standby Electronic Signature

Note: X = VIHor VIL,VID= 12V ± 0.5V.

Pulse V

X XVCCHi-Z X XVPPData Out X

Data Out

Q7-Q0

Data In

Hi-Z Hi-Z

Codes

Table 4. Electronic Signature

Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data

Manufacturer’s Code Device Code

00100000 20h 10001101 8Dh

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M27C256B

Table 5. AC Measurement Conditions

High Speed Standard

Input Rise and FallTimes ≤ 10ns ≤ 20ns Input Pulse Voltages 0 to 3V 0.4V to 2.4V Input and Output Timing Ref.Voltages 1.5V 0.8V and 2V

Figure 3. AC Testing Input Output Waveform

High Speed

1.5V

Standard

2.4V

0.4V

Table 6. Capacitance

Symbol Parameter Test Condition Min Max Unit

OUT

Note: 1. Sampled only, not 100% tested.

Input Capacitance Output Capacitance

(1)

(TA=25°C, f = 1 MHz)

2.0V

0.8V

AI01822

Figure 4. AC Testing Load Circuit

1.3V

1N914

3.3kΩ

DEVICE UNDER

TEST

CL= 30pF for HighSpeed CL= 100pF for Standard CLincludes JIG capacitance

OUT

=0V

6pF

12 pF

OUT

AI01823B

DEVICE OPERATION

The operating modes of the M27C256B are listed in the Operating Modes. A single power supply is required in the read mode. All inputs are TTL levels except for VPPand 12V on A9 for Electronic Signature.

Read Mode

The M27C256B has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (E) is the power control and should be used for device selection. Output Enable(G) isthe outputcontrol and should be used to gate data to the output pins, independent of device selection. Assuming that the ad-

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dresses are stable, the address access time (t

) is equal to the delay from E to output

AVQV

). Data is available at the output after delay

ELQV

of t

from the falling edge of G, assuming that

GLQV

E has been low andthe addresses have been stable for at least t

AVQV-tGLQV

Standby Mode

The M27C256B has a standby modewhich reduces the supply current from 30mA to 100µA. The M27C256B is placed in the standby mode by applying a CMOS high signalto the E input. When in the standby mode, theoutputs are ina high impedance state,independent of the G input.

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M27C256B

Table 7. Read Mode DC Characteristics

(1)

(TA= 0 to70°C, –40 to 85°C, –40 to 105°C or –40 to 125°C; VCC=5V±5% or 5V ± 10%; VPP=VCC)

Symbol Parameter Test Condition Min Max Unit

CC1

CC2

I V

Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.

Table 8A. Read Mode AC Characteristics

Input Leakage Current 0V ≤ VIN≤ V

(1)

0V ≤ V

E=V

= 0mA, f = 5MHz

OUT

E=V

E>V

PP=VCC

= –100µAV

Output Leakage Current

Supply Current

Supply Current (Standby) TTL Supply Current (Standby) CMOS Program Current

Input Low Voltage –0.3 0.8 V

(2)

Input High Voltage 2 Output Low Voltage

Output High VoltageTTL

Output High VoltageCMOS

2. Maximum DC voltage on Output is V

+0.5V.

≤ V

OUT

,G=VIL,

– 0.2V

= 2.1mA

= –1mA

3.6 V – 0.7V

±10 µA ±10 µA

30 mA

1mA 100 µA 100 µA

0.4 V

(TA= 0 to70°C, –40 to 85°C, –40 to 105°C or –40 to 125°C; VCC=5V±5% or 5V ± 10%; VPP=VCC)

M27C256B

Symbol Alt Parameter Test Condition

AVQVtACC

ELQV

GLQVtOE

(2)

EHQZ

(2)

GHQZ

AXQXtOH

Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.

2. Sampled only, not 100% tested.

3. Speed obtained with High Speed AC measurement conditions.

Address Valid to Output Valid

Chip Enable Low to

Output Valid Output EnableLow to

Output Valid Chip Enable High to

Output Hi-Z Output Enable High

to Output Hi-Z Address Transitionto

Output Transition

E=V

,G=V

G=V

E=V

G=V

E=V

,G=V

-45

(3)

-60 -70 -80

Unit

Min Max Min Max Min Max Min Max

45 60 70 80 ns

25 30 35 40 ns

0 25 0 30 0 30 0 30 ns

0000ns

Two Line Output Control

Because EPROMs are usually used in larger memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows:

a. the lowest possible memory power dissipation, b. complete assurance that output bus contention

will not occur.

For the most efficient use of these two control lines, Eshould be decoded andused as theprimary device selecting function, while G should be made a common connection to all devices in the array and connected to the READ line from the system controlbus. Thisensures that all deselected memorydevices are in their low power standby mode and that the output pins are only active when data is desired from aparticular memorydevice.

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M27C256B

Table 8B. Read Mode AC Characteristics

(1)

(TA= 0 to70°C, –40 to 85°C, –40 to 105°C or –40 to 125°C; VCC=5V±5% or 5V ± 10%; VPP=VCC)

M27C256B

Symbol Alt Parameter Test Condition

Unit-90 -10 -12 -15/-20/-25

Min Max Min Max Min Max Min Max

AVQVtACC

ELQV

GLQVtOE

(2)

EHQZ

(2)

GHQZ

AXQXtOH

Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.

2. Sampled only, not 100% tested.

Address Valid to Output Valid

Chip Enable Low to

Output Valid Output EnableLow to

Output Valid Chip Enable High to

Output Hi-Z Output Enable High

to Output Hi-Z Address Transition to

Output Transition

E=V

G=V

E=V

,G=V

E=V

,G=V

90 100 120 150 ns

40 50 60 65 ns

0 30 0 30 0 40 0 50 ns

0000ns

Figure 5. Read Mode AC Waveforms

A0-A14

Q0-Q7

VALID

tAVQV

tGLQV

tELQV

System Considerations

The power switching characteristics of Advance CMOS EPROMs requirecareful decoupling of the devices. The supply current, ICC, has three segments that are of interest to the system designer: the standby current level, the active current level, and transient current peaks that are produced by the fallingand rising edgesof E. The magnitudeof this transient current peaks is dependent on the capacitive and inductive loading of the device at the output.The associated transient voltagepeaks can be suppressed bycomplying with the two line

VALID

tAXQX

tEHQZ

tGHQZ

Hi-Z

AI00758B

outputcontrol and by properly selected decoupling capacitors.It is recommended thata 0.1µF ceramic capacitorbe used onevery devicebetween V

and VSS. This should be a high frequency capacitor of low inherent inductance and should be placed as close to the device as possible. Inaddition, a 4.7µF bulk electrolytic capacitor should be used between VCCand VSSfor every eight devices. The bulk capacitor should be located near the power supply connectionpoint. The purposeofthe bulk capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces.

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M27C256B

Table 9. Programming Mode DC Characteristics

(1)

(TA=25°C; VCC= 6.25V ± 0.25V; VPP= 12.75V ± 0.25V)

Symbol Parameter Test Condition Min Max Unit

Note: VCCmust be applied simultaneously with orbefore VPPand removed simultaneously or after VPP.

Table 10. Programming Mode AC Characteristics

Input Leakage Current VIL≤ VIN≤ V

±10 µA Supply Current 50 mA Program Current

E=V

50 mA

Input Low Voltage –0.3 0.8 V

Input High Voltage 2

Output Low Voltage Output High Voltage TTL

= 2.1mA

= –1mA

3.6 V

+ 0.5

0.4 V

A9 Voltage 11.5 12.5 V

(1)

(TA=25°C; VCC= 6.25V ± 0.25V; VPP= 12.75V ± 0.25V

Symbol Alt Parameter Test Condition Min Max Unit

AVEL

QVEL

VPHEL

VCHEL

ELEH

EHQX

QXGL

GLQV

GHQZ

GHAX

Note: VCCmust be applied simultaneously with orbefore VPPand removed simultaneously or after VPP.

t t

VPS

VCS

OES

DFP

Address Valid to Chip Enable Low 2 µs

Input Valid to Chip Enable Low 2 µs

VPPHigh to Chip Enable Low VCCHigh to Chip Enable Low Chip Enable Program Pulse Width 95 105 µs

Chip Enable High to Input Transition 2 µs

2 µs 2 µs

Input Transition to Output Enable Low 2 µs Output Enable Low toOutput Valid 100 ns

Output Enable High to Output Hi-Z 0 130 ns Output Enable High to Address Transition 0 ns

Programming

When delivered (and after each erasure for UV EPROM), all bits of the M27C256B are in the ”1” state. Data is introduced by selectively programming ”0”s into the desired bit locations. Although only ”0”s will be programmed, both ”1”s and ”0”s can be present in the data word. The only way to change a’0’to a’1’is by die exposure toultraviolet

light (UV EPROM). The M27C256B is in the programming modewhen VPPinput isat 12.75V, G is at VIHand E is pulsed to VIL. The data to be programmed is applied to 8 bits inparallel to the data output pins. The levels required for the address and data inputs are TTL. VCCis specified to be

6.25V ± 0.25 V.

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M27C256B

Figure 6. Programming and Verify Modes AC Waveforms

A0-A14

tAVEL

Q0-Q7

DATA IN DATA OUT

tQVEL

tVPHEL

tVCHEL

tELEH

Figure 7. Programming Flowchart

VCC= 6.25V, VPP= 12.75V

n=0

E = 100µsPulse

VERIFY

YES

Last

Addr

YES

CHECK ALL BYTES

1st: VCC=6V

2nd: VCC= 4.2V

++ Addr

YES

++n

=25

FAIL

VALID

tEHQX

tGLQV

tQXGL

PROGRAM VERIFY

PRESTO II Programming Algorithm

PRESTO II Programming Algorithm allows to program thewhole array with aguaranteed margin, in a typical time of 3.5 seconds. Programming with PRESTO II involves the applicationof a sequence of 100µs program pulses to each byte until a correct verify occurs (see Figure 7). During programming and verify operation, a MARGIN MODE circuit is automatically activated in order to guarantee that each cell is programmed with enough margin. No overprogram pulse is applied sincethe verify in MARGIN MODE provides necessary margin to each programmed cell.

Program Inhibit

Programming of multiple M27C256Bs in parallel with different data is also easily accomplished. Except for E,all likeinputs including G of theparallel M27C256B may be common. A TTL low level pulse applied to a M27C256B’s E input, with V at 12.75V, will program that M27C256B. A high level E input inhibits the other M27C256Bs from being programmed.

Program Verify

AI00760B

A verify (read) should be performed on the programmed bitsto determine that theywere correctly programmed.The verify is accomplished with G at VIL, E at VIH,VPPat 12.75V and VCCat 6.25V.

tGHQZ

tGHAX

AI00759

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M27C256B

Electronic Signature

The Electronic Signature (ES) mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment to automatically match the device tobe programmed with its corresponding programming algorithm. The ES mode is functional in the 25°C ± 5°C ambient temperaturerange thatis required when programming the M27C256B. To activate the ES mode, the programming equipment must force

11.5V to 12.5V on address line A9 of the M27C256B, with VCC=VPP= 5V. Two identifier bytes maythen be sequenced fromthe device outputs bytoggling address line A0from VILtoVIH. All other address lines must be held at VILduring Electronic Signature mode. Byte 0 (A0 = VIL) represents the manufacturer code and byte 1 (A0 = VIH) the device identifier code. For the STMicroelectronics M27C256B, these two identifier bytes are given in Table 4 and can be read-out on outputs Q7 to Q0.

ERASURE OPERATION (appliesfor UV EPROM)

The erasure characteristics of the M27C256B is such that erasure begins when the cells are exposed to light with wavelengths shorter than approximately 4000 Å. It should be noted that sunlight and some type of fluorescent lamps have wavelengths in the 3000-4000 Å range. Research shows that constant exposure to room level fluorescent lighting could erasea typical M27C256Bin about 3years, while it would takeapproximately 1 week to cause erasure when exposed to direct sunlight. If the M27C256B is to be exposed to these typesof lighting conditions for extended periods oftime, it is suggested that opaque labels be put over the M27C256B window to prevent unintentional erasure.The recommended erasure procedure for the M27C256B is exposure to short wave ultraviolet light which has wavelength 2537Å. Theintegrated dose (i.e. UV intensity x exposure time) for erasure should be a minimum of 15 W-sec/cm2. The erasure time with this dosage is approximately15 to20 minutes using an ultraviolet lamp with 12000 µW/cm2power rating. The M27C256B should be placed within 2.5 cm (1 inch) of the lamp tubes during the erasure. Some lamps have a filter on theirtubes which should be removed before erasure.

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M27C256B

Table 11. Ordering Information Scheme

Example: M27C256B -70 X C 1 TR

Device Type

M27

Supply Voltage

C=5V

Device Function

256B = 256 Kbit (32Kb x 8)

Speed

(1)

=45ns

-45

-60 = 60 ns

-70 = 70 ns

-80 = 80 ns

-90 = 90 ns

-10 = 100 ns

-12 = 120 ns

-15 = 150 ns

-20 = 200 ns

-25 = 250 ns

Tolerance

blank = ± 10% X=±5%

Package

F = FDIP28W B = PDIP28 C = PLCC32 N = TSOP28: 8 x13.4 mm

Temperature Range

1=0to70°C 3 = –40 to 125 °C 6=–40to85°C

Options

X = Additional Burn-in TR = Tape & Reel Packing

Note: 1. High Speed, see AC Characteristics section for further information.

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.

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Table 12. Revision History

Date Revision Details

July 1998 First Issue 09/20/00 AN620 Reference removed 11/29/00 PLCC codification changed (Table 11) 04/02/01 FDIP28W mechanical dimensions changed (Table13)

M27C256B

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M27C256B

Table 13. FDIP28W - 28 pin Ceramic Frit-seal DIP, with window, Package Mechanical Data

Symbol

A 5.72 0.225 A1 0.51 1.40 0.020 0.055 A2 3.91 4.57 0.154 0.180 A3 3.89 4.50 0.153 0.177

B 0.41 0.56 0.016 0.022 B1 1.45 – – 0.057 – –

C 0.23 0.30 0.009 0.012 D 36.50 37.34 1.437 1.470

D2 33.02 – – 1.300 – –

E 15.24 – – 0.600 – – E1 13.06 13.36 0.514 0.526

e 2.54 – – 0.100 – – eA 14.99 – – 0.590 – – eB 16.18 18.03 0.637 0.710

L 3.18 4.10 0.125 0.161

S 1.52 2.49 0.060 0.098

∅ 7.11 – – 0.280 – –

α 4° 11° 4° 11°

N28 28

Typ Min Max Typ Min Max

millimeters inches

Figure 8. FDIP28W - 28 pin Ceramic Frit-seal DIP, with window, Package Outline

B1 B e

A3A1A

∅

Drawing is not to scale.

E1 E

FDIPW-a

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Table 14. PDIP28 - 28 pin Plastic DIP, 600 mils width, Package Mechanical Data

millimeters inches

Symbol

Typ Min Max Typ Min Max

A – 5.08 – 0.200 A1 0.38 – 0.015 – A2 3.56 4.06 0.140 0.160

B 0.38 0.51 0.015 0.020 B1 1.52 – – 0.060 – –

C 0.20 0.30 0.008 0.012 D 36.83 37.34 1.450 1.470

D2 33.02 – – 1.300 – –

E 15.24 – – 0.600 – – E1 13.59 13.84 0.535 0.545

e1 2.54 – – 0.100 – – eA 14.99 – – 0.590 – – eB 15.24 17.78 0.600 0.700

L 3.18 3.43 0.125 0.135 S 1.78 2.08 0.070 0.082 α 0° 10° 0° 10°

M27C256B

N28 28

Figure 9. PDIP28 - 28 pin Plastic DIP, 600 mils width, Package Outline

A2A1A

B1 B e1

E1 E

PDIP

Drawing is not to scale.

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M27C256B

Table 15. PLCC32 - 32lead Plastic Leaded Chip Carrier, Package Mechanical Data

Symbol

A 2.54 3.56 0.100 0.140 A1 1.52 2.41 0.060 0.095 A2 0.38 0.015

B 0.33 0.53 0.013 0.021 B1 0.66 0.81 0.026 0.032

D 12.32 12.57 0.485 0.495 D1 11.35 11.56 0.447 0.455 D2 9.91 10.92 0.390 0.430

e 1.27 0.050

E 14.86 15.11 0.585 0.595 E1 13.89 14.10 0.547 0.555 E2 12.45 13.46 0.490 0.530

F 0.00 0.25 0.000 0.010

R 0.89 0.035

N32 32 Nd 7 7 Ne 9 9

CP 0.10 0.004

Typ Min Max Typ Min Max

millimeters inches

Figure 10. PLCC32 - 32 lead Plastic Leaded Chip Carrier, Package Outline

Ne E1 E

D2/E2

0.51 (.020)

1.14 (.045)

PLCC

Drawing is not to scale.

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M27C256B

Table 16. TSOP28 - 28 lead Plastic Thin Small Outline, 8 x 13.4 mm, Package Mechanical Data

Symbol

Typ Min Max Typ Min Max

A 1.00 1.25 0.039 0.049 A1 0.20 0.008 A2 0.95 1.05 0.037 0.041

B 0.30 0.012

C 0.10 0.21 0.004 0.008 D 13.10 13.70 0.516 0.539

D1 11.70 11.90 0.461 0.469

E 7.90 8.25 0.311 0.325

e 0.55 - - 0.022 - -

L 0.30 0.70 0.012 0.028

α 0° 5° 0° 5°

N28 28

CP 0.10 0.004

millimeters inches

Figure 11. TSOP28 - 28 lead Plastic Thin Small Outline, 8 x 13.4 mm, Package Outline

DIE

TSOP-c

Drawing is not to scale

LA1 α

15/16

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M27C256B

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of useofsuch information nor for any infringement ofpatents orother rightsof third parties which may result from itsuse. Nolicense is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to changewithout notice. This publication supersedes and replaces allinformation previously supplied. STMicroelectronics products arenot authorized for use as critical components in life support devicesor systems without express written approval of STMicroelectronics.

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