Datasheet 227c010 Datasheet

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IS27C010

MM27C010

My-MS

ISSI

131,072 x 8 CMOS EPROM PRELIMINARY INFORMATION

FEATURES

•Fast read access time: 90 ns

•JEDEC-approved pinout

•High-speed write programming — Typically less than 16 seconds

•5V ±10% power supply tolerance available

•Both CMOS and TTL compatible input and output

•Two line control functions

•Industrial and commercial temperature ranges available

FUNCTIONAL BLOCK DIAGRAM

DESCRIPTION

The MM27C010 is a 1 megabit (128K-word by 8-bit) CMOS Programmable Read-Only Memory. It requires only a single 5V power supply in normal read mode operation. Any byte can be accessed in less than 90 ns. The MM27C010 offers separate Output Enable (OE) and Chip Enable (CE) controls, thus eliminating bus contention in a multiple bus microprocessor system.

All signals are TTL levels, including programming signals. Bit locations may be programmed singly, in blocks, or at random.

The MM27C010 uses write programming algorithm. Programming time is typically only 100 µs per byte.

This product is available in One-Time Programmble (OTP) PDIP, PLCC, and TSOP packages over commercial and industrial temperature ranges.

OE CE

PGM

A0-A16

VCC GND VPP

OUTPUT ENABLE

CHIP ENABLE

AND

PROG LOGIC

Y

DECODER

X

DECODER

DQ0-DQ7

OUTPUT

BUFFERS

Y

GATING

1,048,576-BIT

CELL MATRIX

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MM27C010

PIN CONFIGURATIONS

32-Pin DIP

VPP

A16 A15 A12

A7 A6 A5 A4 A3 A2 A1

A0 DQ0 DQ1 DQ2

GND

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

VCC PGM (P) NC A14 A13 A8 A9 A11 OE (G) A10 CE (E) DQ7 DQ6 DQ5 DQ4 DQ3

PIN DESCRIPTIONS

A0-A16 Address Inputs

CE (E

) Chip Enable Input

DQ0-DQ7 Data Inputs/Outputs

OE (G

) Output Enable Input

PGM (P

Vcc Power Supply Voltage VPP Program Supply Voltage GND Ground NC No Internal Connection

) Program Enable Input

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32-Pin PLCC

INDEX

A7 A6 A5 A4 A3 A2 A1 A0

DQ0

A12

4321323130

5 6 7 8 9 10 11 12 13

14 15 16 17 18 19 20

DQ1

A15

DQ2

A16

GND

VPP

DQ3

VCC

DQ4

PGM (P)

29 28 27 26 25 24 23 22 21

DQ5

DQ6

A14 A13 A8 A9 A11 OE (G) A10 CE (E) DQ7

32-Pin TSOP

A9 A8

A7 A6 A5 A4

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

A11

A13 A14

PGM (P)

VCC

VPP

A16 A15 A12

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

OE (G) A10 CE (E) DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2 A3

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MM27C010

FUNCTIONAL DESCRIPTION

Upon delivery, the MM27C010 has 1,048,576 bits in the "ONE", or HIGH state. "ZEROs" are loaded into the MM27C010 through the procedure of programming.

The programming mode is entered when 12.5 ± 0.25V is applied to the V VIH. For programming, the data to be programmed is applied eight bits in parallel to the data output pins.

The write programming algorithm reduces programming time by using 100 µs programming pulses followed by a byte verification to determine whether the byte has been successfully programmed. If the data does not verify, an additional pulse is applied for a maximum of 25 pulses. This process is repeated while sequencing through each address of the EPROM.

The write programming algorithm programs and verifies at V

CC = 6V and VP P = 12.5V. After the final address is

completed, all byte are compared to the original data with V

CC = 5.25V.

Program Inhibit

Programming of multiple MM27C010s in parallel with different data is also easily accomplished. Except fo r CE, all like inputs of the parallel MM27C010 may be common. A TTL low-level program pulse applied to an MY27B01 0 CE input with V

P P = 12.5 ± 0.25V,

program that MM27C010. A high-leve l CE input inhibits the other MM27C010 from being programmed.

PP pin,

and

PGM

is at V IL, and OE is at

PGM

LOW and OE HIGH will

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Byte 0 (A0 = VIL ) represents the manufacturer code, and byte 1 (A0 = VIH), the device identifier code. For the MM27B010, these two identifier bytes are given in the Mode Select table. All identifiers manufacturer and device codes will possess odd parity, with the MSB (DQ7) defined as the parity bit.

Read Mode

The MM27C010 has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Assuming that addresses are stable, address access time ( t fro m CE to output ( t CE). Output Enable (OE) is the output control and should be used to get data to the output pins, independent of device selection. Data is available at the outputs t

OE after the falling edge o f

has been LOW and addresses have been stable for at least t

ACC – tOE.

Standby Mode

The MY27B010 is placed in CMOS standby mode when is at Vcc ± 0.3V and in TTL standby mode when CE is at V

IH. When in standby mode, the outputs are in a high-

impedance state, independent of the OE input.

ACC) is equal to the delay

assuming that

Program Verify

A verify should be performed on the programmed bits to determine that they were correctly programmed. The verify should be performed wit h OE and CE at V

IL,

PGM

VIH, and VPP between 12.25V and 12.75V.

Auto Select Mode

The auto select mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 2 5°C ± 5°C ambient temperature range that is required when programming the MM27C010.

To activate this mode, the programming equipment must force 12. 0 ± 0.5V on address line A9 of the MY27B010. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from V

IL to VIH. All other

address lines must be held at VIL during auto select mode.

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MM27C010

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Output OR-Tieing

To accommodate multiple memory connections, a twoline control function is provided to allow for:

System Applications

During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these

1.Low memory power dissipation, and

2.Assurance that output bus contention will not occur.

It is recommended that CE be decoded and used as the primary device-selecting function, while OE be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low-power standby mode and that the output pins are only

transient current peaks is dependent on the output capacitance loading of the device at a minimum, a 0.1 µF ceramic capacitor (high-frequency, low inherent inductance) should be used on each device between V

CC and GND to mini-

mize transient effects. In addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on EPROM arrays, a 4.7 µF bulk electrolytic capacitor should be used between V

CC and GND for each

eight devices. The location of the capacitor should be close to where the power supply is connected to the array.

active when data is desired from a particular memory device.

TRUTH TABLE

Mode

(1,2)

CECE

OEOE

PGMPGM

PGM

PGMPGM

A0 A9 VPP Outputs

Read VIL VIL XXXVCC DOUT Output Disable VIL VIH XXXVCC Hi-Z Standby VIH XXXXVCC Hi-Z Program VIL VIH VIL XXVPP DIN Program Verify VIL VIL VIH XXVPP DOUT Program Inhibit VIH XXXXVPP Hi-Z Auto Select

(3)

Manufacturer Code VIL VIL XVIL VH VCC D5H

Device Code VIL VIL XVIH VH VCC 0EH

Notes:

1. VH = 12.0V ± 0.5V.

2.X = Either V

3.A1-A8 = A10-A16 = V

4.See DC Programming Characteristics for VPP voltage during programming.

IH or VIL.

IL.

LOGIC SYMBOL

A0-A16

DQ0-DQ7 CE (E) PGM (P) OE (G)

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MM27C010

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ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Parameter Value Unit

TERM Terminal Voltage with Respect to GND

All pins except A9 and V

PP –0.6 to VCC + 0.5

PP VCC – 0.3 to 13.5

A9 –0.6 to 13.5

VCC –0.6 to 7.0

(2,3) (2)

(2)

(2,3)

V V V

V TA Ambient Temperature with Power Applied –65 to +125 °C TSTG Storage Temperature (OTP) –65 to +125 °C TSTG Storage Temperature (All others) –65 to +150 °C

Notes:

1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2.Minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods less than 10 ns. Maximum DC voltage on output pins is Vcc + 0.5V which may overshoot to Vcc + 2.0V for periods less than 10 ns.

3.Maximum DC voltage on A9 or V

PP may overshoot to +13.5V for periods less than 10 ns.

OPERATING RANGE

Range Ambient Temperature VCC

Commercial 0°C to +70°C 5V ± 10% Industrial

(1)

–40°C to +85°C 5V ± 10%

Note:

1. Operating ranges define those limits between which the functionally of the device is guaranteed.

DC ELECTRICAL CHARACTERISTICS

(1,2,3)

(Over Operating Range)

SymbolParameter Test Conditions Min. Max. Unit

VOH Output HIGH Voltage VCC = Min., IOH = –400 µA 2.4 — V VOL Output LOW Voltage VCC = Min., IOL = 2.1 mA — 0.45 V VIH Input HIGH Voltage VIL Input LOW Voltage

(4)

2.0 VCC + 0.5 V

–0.3 0.8 V ILI Input Load Current VIN = 0V to +VCC —10µA ILO Output Leakage Current VOUT = 0V to +VCC —10µA

Notes:

1.VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. Never try to force VPP LOW to 1V below V

2.Caution: the MM27C010 must not be removed from (or inserted into) a socket when V

3.Minimum DC input voltage is –0.5V. During transitions, the inputs may undershoot to –2.0V for periods less than 10 ns. Maximum DC voltage on output pins is V

4.Tested under static DC conditions.

CC. Manufacturer suggests to tie VPP and VCC together during the READ operation.

CC or VPP is applied.

CC + 0.5V which may overshoot to VCC + 2.0V for periods less than 10 ns.

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MM27C010

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POWER SUPPLY CHARACTERISTICS

(1,2,5)

(Over Operating Range)

SymbolParameter Test Conditions Min. Max. Unit

CC1 Vcc Operating VCC = Max.,

Supply Current

(3)

IOUT = 0 mA, f = 5 MHz Industrial — 40

= VIL Commercial — 30 mA

IPP1 VPP Current During VCC = Max., CE = OE = VIL — 100 µA

(4)

Read

VPP = VCC

ICCSB0 Vcc CMOS Standby CE ≥ VCC – 0.3V — 50 µA

Current

CCSB1 Vcc TTL Standby

≥ VIH —1mA

Current Other Inputs = VIH or VIL (TTL Level)

Notes:

CC must be applied simultaneously or before VPP and removed simultaneously or after VPP. Never try to force VPP LOW to 1V

1. V below VCC. Manufacturer suggests to tie VPP and VCC together during the READ operation.

2. Caution: the MM27C010 must not be removed from (or inserted into) a socket when V

CC1 is tested with

3. I

4. Maximum active power usage is the sum of ICC and IPP.

5. Minimum DC input voltage is –0.5V. During transitions, the inputs may undershoot to –2.0V for periods less than 10 ns. Maximum DC voltage on output pins is V

CAPACITANCE

= VIH to simulate open outputs.

CC + 0.5V which may overshoot to VCC + 2.0V for periods less than 10 ns.

(1,2,3)

CC or VPP is applied.

Symbol Parameter Conditions Typ. Max. Unit

CIN Input Capacitance VIN = 0V 7 10 pF COUT Output Capacitance VOUT = 0V 8 12 pF

Notes:

1.Typical values are for nominal supply voltage.

2.This parameter is only sampled, but not 100% tested.

3.Test conditions: T

SWITCHING TEST CIRCUIT

Device

Under

Test

100 pF

A = 25°C, f = 1 MHz.

5.0V

6.2KΩ

2.7KΩ

SWITCHING TEST WAVEFORM

2.4V

0.45V

Notes:

AC Testing:

1.Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0".

2.Input pulse rise and fall times are < 20 ns.

INPUT OUTPUT

2.0V

0.8V

2.0V

0.8V

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MM27C010

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SWITCHING CHARACTERISTICS

(1,2,3,4)

(Over Operating Range)

JEDEC Std. -90 -12 -15

Symbol Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit

tAVQA tACC Address to

= OE = VIL — 90 — 120 — 150 ns

Output Delay

tELQV tCE Chip Enable to

= VIL — 90 — 120 — 150 ns

Output Delay

tGLQV tOE Output Enable to

= VIL —45—50—65ns

Output Delay

tEHOZ, tDF

(2)

Chip Enable HIGH or — 30 — 35 — 35 ns

tGHQZ Output Enable HIGH,

whichever comes first, to Output Float

tAVOX tOH Output Hold from 0 — 0 — 0 — ns

Address, CE or whichever occured first

Notes:

CC must be applied simultaneously or before VPP and removed simultaneously or after VPP.

1.V

2.This parameter is only sampled, not 100% tested.

3.Caution: The MM27C010 must not be removed from (or inserted into) a socket or board when V

4.Output Load: 1 TTL gate and C

Input Rise and Fall times: 20 ns. Input Pulse Levels: 0.45V to 2.4V. Timing Measurement Reference Level: 0.8V to 2V for inputs and outputs.

PP or VCC applied.

L =100 pF.

SWITCHING WAVEFORMS

2.4V

ADDRESS

0.4V

OUTPUT

Notes:

1.OE may be delayed up to t

DF is specified from

2.t

2.0V

0.8V

ACC – tOE after the falling edge of

or CE, whichever occurs first.

ADDRESS VALID

tCE

(1)

tACC

tOE

without impact on tACC.

2.0V

0.8V

tOH

VALID OUTPUT

tDF

(2)

Hi-ZHi-Z

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MM27C010

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DC PROGRAMMING CHARACTERISTICS

SymbolParameter Test Conditions Min. Max. Unit

VOH Output HIGH Voltage During Verify IOH = –400 µA 2.4 — V VOL Output LOW Voltage During Verify IOL = 2.1 mA — 0.45 V VIH Input HIGH Voltage 2.0 VCC + 0.5 V VIL Input LOW Voltage (All Inputs) –0.3 0.8 V VH A9 Auto Select Voltage 11.5 12.5 V ILI Input Current (All Inputs) VIN = VIL or VIH —1µA ICC VCC Supply Current (Program & Verify) — 50 mA IPP VPP Supply Current CE = VIL, OE = VIH —30mA VCC Supply Voltage 5.75 6.25 V VPP Programming Voltage 12.25 12.75 V

SWITCH PROGRAMMING CHARACTERISTICS

JEDEC Std.

Symbol Symbol Parameter Min. Max. Unit

(1,2,3,4)

(TA = +25°C ± 5°C)

(1,2,3,4)

(TA = +25°C ± 5°C)

tAVEL tAS Address Setup Time 2 — µs

tDZGL tOES

Setup Time 2 — µs

tDVEL tDS Data Setup Time 2 — µs

tGHAX tAH Address Hold Time 0 — µs

tEHDX tDH Data Hold Time 2 — µs

tGHQZ tDFP

to Output Float Delay 0 130 ns

tVPS tVPS VPP Setup Time 2 — µs

tELEH1 tPW

PGM

Program Pulse Width 95 105 µs

tVCS tVCS VCC Setup Time 2 — µs

tELPL tCES

tGLQV tOE Data Valid from

Notes:

CC must be applied simultaneously or before VPP and removed simultaneously or after VPP.

1. V

PP must be ≥ VCC during the entire programming and verifying procedure.

2. V

3. When programming MM27C010, a 0.1 µF capacitor is required across VPP and ground to suppress spurious voltage transients

which may damage the device.

4. Programming characteristics are sampled but not 100% tested at worst-case conditions.

Setup Time 2 — µs

— 150 ns

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MM27C010

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PROGRAMMING ALGORITHM WAVEFORM

PROGRAM

ADDRESS

DATA

PGM

≥Vcc–0.3V

5V±10%

DATAIN STABLE

VPS

VCS

CES

12.5V

5.75V-6.25V

(1,2)

OES

Hi-Z

PROGRAM

VERIFY

DATA

OUT

VALID

DFP

Max

Notes:

1. The timing reference level is 0.8V to 2V for inputs and outputs

2. tOE and tDFP are characteristics of the device but must be accommodated by the programmer.

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MM27C010

PROGRAMMING FLOW CHART

Start

Address = First Location

Vcc = 6V

= 12.5V

X = 0

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Interactive

programming

Section

Increment Address

Program One 100 µs Pulse

Increment X

X = 25?

Fail

Verify

Byte

Last

Address?

Yes

Pass

Yes

Verify Section

Vcc = VPP = 5.25V

Verify All

Bytes

Pass

Device Passed

Fail

Device Failed

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MM27C010

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ORDERING INFORMATION Commerical Range: 0°C to +70°C

Speed (ns) Order Part Number Package

90 MM27C010-90W 600-mil Plastic DIP

MM27C010-90PL PLCC – Plastic Leaded Chip Carrier MM27C010-90T TSOP

120 MM27C010-12W 600-mil Plastic DIP

MM27C010-12PL PLCC – Plastic Leaded Chip Carrier MM27C010-12T TSOP

150 MM27C010-15W 600-mil Plastic DIP

MM27C010-15PL PLCC – Plastic Leaded Chip Carrier MM27C010-15T TSOP

ORDERING INFORMATION Industrial Range: –40°C to +85°C

Speed (ns) Order Part Number Package

90 MM27C010-90PLI PLCC – Plastic Leaded Chip Carrier

MM27C010-90TI TSOP

120 MM27C010-12PLI PLCC – Plastic Leaded Chip Carrier

MM27C010-12TI TSOP

150 MM27C010-15PLI PLCC – Plastic Leaded Chip Carrier

MM27C010-15TI TSOP

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Jalan Usahawan, 63000 Cyberjaya, Selangor, Malaysia

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Tel: (603)318-1011 Tel: (603)318-1012

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