Page 1
NM24C65U
64K-Bit Serial EEPROM with Write Protect
2-Wire Bus Interface
NM24C65U 64K-Bit Serial EEPROM with Write Protect 2-Wire Bus Interface
PRELIMINARY
August 1999
General Description:
The NM24C65U is a 64K (65,536) bit serial interface CMOS
EEPROM (Electrically Erasable Programmable Read-Only
Memory). This device fully conforms to the Extended I2C™ 2-wire
protocol which uses Clock (SCL) and Data I/O (SDA) pins to
synchronously clock data between the "master" (for example a
microprocessor) and the "slave" (the EEPROM device). In addition, the serial interface allows a minimal pin count packaging
designed to simplify PC board layout requirements and offers the
designer a variety of low voltage and low power options.
NM24C65U incorporates a hardware "Write Protect" feature, by
which the upper half of the memory can be disabled against
programming by connecting the WP pin to VCC. This section of
memory then effectively becomes a ROM (Read-Only Memory)
and can no longer be programmed as long as WP pin is connected
to VCC.
Fairchild EEPROMs are designed and tested for applications requiring high endurance, high reliability and low power consumption for a
Block Diagram
V
SDA
CC
WP
WRITE
LOCKOUT
START
STOP
LOGIC
continuously reliable non-volatile solution for all markets.
Functions
■ I2C™ compatible interface
■ 65,536 bits organized as 8,192 x 8
■ 100 KHz or 400 KHz operation
■ Extended 2.7V – 5.5V operating voltage
■ Self timed programming cycle (6ms typical)
■ "Programming complete" indicated by ACK polling
■ Memory "Upper Block" Write Protect pin
Features
■ The I2C™ interface allows the smallest I/O pincount of any
EEPROM interface
■ 32 byte page write mode to minimize total write time per byte
■ Low VCC programming lockout (3.8V)
— "H" option (Standard VCC range) parts only
■ Typical 200µA active current (I
■ Typical 1µA standby current (ISB) for "L" devices and 0.1µA
standby current for "LZ" devices
■ Endurance: Up to 1,000,000 data changes
■ Data retention greater than 40 years
START CYCLE
H.V. GENERATION
TIMING &CONTROL
CCA
)
SCL
A2
A1
A0
I2C™ is a registered trademark of Philips Electronics N.V.
© 1999 Fairchild Semiconductor Corporation
NM24C65U Rev. B.1
SLAVE ADDRESS
REGISTER &
COMPARATOR
CONTROL
LOGIC
LOAD INC
WORD
ADDRESS
COUNTER
R/W
D
IN
E2PROM
XDEC
CK
1
ARRAY
YDEC
DATA REGISTER
D
OUT
DS800012-1
www.fairchildsemi.com
Page 2
Connection Diagram
NM24C65U 64K-Bit Serial EEPROM with Write Protect 2-Wire Bus Interface
Dual-In-Line Package (N)
and 8-Pin SO Package (M8)
Pin Names
A0
A1
1
2
V
8
7
CC
WP
NM24C65U
A2
V
SS
3
4
SCL
6
SDA
5
Top View
See Package Number N08E and M08A
A0, A1, A2 Device Address Input
V
SS
SDA Data I/O
SCL Clock Input
WP Write Protect
V
CC
Ground
Power Supply
DS800012-2
Ordering Information
NM 24 C XX U F LZ E XX Letter Description
Package N 8-Pin DIP
M8 8-Pin SOIC
Temp. Range None 0 to 70°C
Voltage Operating Range Blank 4.5V to 5.5V
SCL Clock Frequency Blank 100KHz
Density 65 64K with Write Protect
Interface 24 IIC
V -40 to +125°C
E -40 to +85°C
L 2.7V to 5.5V
LZ 2.7V to 5.5V and
<1µA Standby Current
H 4.5V to 5.5V and VCC Lockout
F 400KHz
Ultralite CS100UL Process
C CMOS
NM Fairchild Non-Volatile
Memory
NM24C65U Rev. B.1
2
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Page 3
Product Specifications
NM24C65U 64K-Bit Serial EEPROM with Write Protect 2-Wire Bus Interface
Absolute Maximum Ratings
Ambient Storage Temperature –65°C to +150°C
All Input or Output Voltages
with Respect to Ground 6.5V to –0.3V
Lead Temperature
(Soldering, 10 seconds) +300°C
ESD Rating 2000V min.
Operating Conditions
Ambient Operating Temperature
NM24C65U 0°C to +70°C
NM24C65UE -40°C to +85°C
NM24C65UV -40°C to +125°C
Positive Power Supply
NM24C65U/NM24C65UH 4.5V to 5.5V
NM24C65UL 2.7V to 5.5V
NM24C65ULZ 2.7V to 5.5V
Standard VCC (4.5V to 5.5V) DC Electrical Characteristics
Symbol Parameter Test Conditions Limits Units
I
V
CCA
I
SB
I
LI
I
LO
V
V
OL
Min
Active Power Supply Current f
Standby Current VIN = GND or V
Input Leakage Current VIN = GND to V
Output Leakage Current V
IL
IH
Input Low Voltage –0.3 VCC x 0.3 V
Input High Voltage VCC x 0.7 VCC + 0.5 V
Output Low Voltage I
= 400 kHz 0.2 1.0 mA
SCL
f
= 100 kHz
SCL
CC
CC
= GND to V
OUT
= 3 mA 0.4 V
OL
CC
Typ (Note 1)
Max
10 50 µA
0.1 1 µA
0.1 1 µA
Low VCC (2.7V to 5.5V) DC Electrical Characteristics
Symbol Parameter Test Conditions Limits Units
Min Typ Max
(Note 1)
I
CCA
I
SB
I
LI
I
LO
V
IL
V
IH
V
OL
Capacitance T
Symbol Test Conditions Max Units
C
I/O
C
IN
Note 1: Typical values are for TA = 25°C and nominal supply voltage (5V).
Note 2: This parameter is periodically sampled and not 100% tested.
Active Power Supply Current f
= 400 KHz 0.2 1.0 mA
SCL
f
= 100 KHz
SCL
Standby Current VIN = GND VCC = 2.7V - 4.5V 1 10 µA
or V
CC
VCC = 2.7V - 4.5V 0.1 1 µA
VCC = 4.5V - 5.5V 10 50 µA
Input Leakage Current VIN = GND to V
Output Leakage Current V
= GND to V
OUT
CC
CC
Input Low Voltage –0.3 V
0.1 1 µA
0.1 1 µA
x 0.3 V
CC
Input High Voltage VCC x 0.7 VCC + 0.5 V
Output Low Voltage IOL = 3 mA 0.4 V
= +25°C, f = 100/400 KHz, VCC = 5V (Note 2)
A
Input/Output Capacitance (SDA) V
= 0V 8 pF
I/O
Input Capacitance (A0, A1, A2, SCL) VIN = 0V 6 pF
NM24C65U Rev. B.1
3
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Page 4
AC Conditions of Test
Input Pulse Levels VCC x 0.1 to VCC x 0.9
Input Rise and Fall Times 10 ns
Input & Output Timing Levels VCC x 0.5
Output Load 1 TTL Gate and CL = 100 pF
Read and Write Cycle Limits (Standard and Low VCC Range - 2.7V-5.5V)
Symbol Parameter 100 KHz 400 KHz Units
Min Max Min Max
f
SCL
T
I
t
AA
t
BUF
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
t
F
t
SU:STO
t
DH
t
WR
(Note 3) - NM24C65UL, NM24C65ULZ 15 15
SCL Clock Frequency 100 400 KHz
Noise Suppression Time Constant at
SCL, SDA Inputs (Minimum V
IN
100 50 ns
Pulse width)
SCL Low to SDA Data Out Valid 0.3 3.5 0.1 0.9 µs
Time the Bus Must Be Free before 4.7 1.3 µs
a New Transmission Can Start
Start Condition Hold Time 4.0 0.6 µs
Clock Low Period 4.7 1.5 µs
Clock High Period 4.0 0.6 µs
Start Condition Setup Time 4.7 0.6 µs
(for a Repeated Start Condition)
Data in Hold Time 0 0 µs
Data in Setup Time 250 100 ns
SDA and SCL Rise Time 1 0.3 µs
SDA and SCL Fall Time 300 300 ns
Stop Condition Setup Time 4.7 0.6 µs
Data Out Hold Time 300 50 ns
Write Cycle Time - NM24C65U 10 10 ms
NM24C65U 64K-Bit Serial EEPROM with Write Protect 2-Wire Bus Interface
Note 3: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the
NM24C65U bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address
4
NM24C65U Rev. B.1
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Page 5
Bus Timing
t
F
t
t
SCL
SDA
SDA
OUT
t
SU:STA
IN
t
HD:STA
LOW
BACKGROUND INFORMATION (IIC Bus)
As mentioned, the IIC bus allows synchronous bidirectional communication between Transmitter/Receiver using the SCL (clock) and
SDA (Data I/O) lines. All communication must be started with a valid
START condition, concluded with a STOP condition and acknowledged by the Receiver with an ACKNOWLEDGE condition.
In addition, since the IIC bus is designed to support other devices
such as RAM, EPROM, etc., the device type identifier string, or
slave address, must follow the START condition. For EEPROMs,
the first 4-bits of the slave address is '1010'. This is then followed
by the device selection bits A2, A1 and A0.The final bit in the slave
address determines the type of operation performed (READ/
WRITE). A "1" signifies a READ while a "0" signifies a WRITE. The
slave address is then followed by two bytes that define the word
address, which is then followed by the data byte.
The EEPROMs on the IIC bus may be configured in any manner
required, providing the total memory addressed does not exceed
4M bits in the Extended IIC protocol. EEPROM memory addressing is controlled by hardware configuring the A2, A1, and A0 pins
(Device Address pins) with pull-up or pull-down resistors. ALL
UNUSED PINS MUST BE GROUNDED (tied to V
SS
Addressing an EEPROM memory location involves sending a
command string with the following information:
[DEVICE TYPE]-[DEVICE ADDRESS]-[PAGE BLOCK ADDRESS]-[BYTE ADDRESS]
Definitions
Word 8 bits (byte) of data
Page 32 sequential addresses (one byte each) that
Master Any IIC device CONTROLLING the transfer
Slave Device being controlled (EEPROMS are
Transmitter Device currently SENDING data on the bus
Receiver Device currently RECEIVING data on the bus
may be programmed during a "Page Write"
programming cycle.
of data (such as a microcontroller).
always considered Slaves).
(may be either a Master or Slave).
(Master or Slave).
HIGH
t
HD:DAT
t
AA
).
t
R
t
LOW
t
t
SU:DAT
t
DH
SU:STO
t
BUF
DS800012-3
Pin Description
SERIAL CLOCK (SCL)
The SCL input is used to clock all data into and out of the device.
SERIAL DATA (SDA)
SDA is a biderectional pin used to transfer data into and out of the
device. It is an open drain output and may be wire-ORed with any
number of open drain or open collector outputs.
Device Address Inputs (A0, A1, A2)
Device address pins A0, A1, and A2 are connected to VCC or VSS to
configure the EEPROM address for multiple device configuration. A
total of eight different devices can be attached to the same SDA bus.
Write Protection (WP)
If WP is tied to VCC, program WRITE operations onto the upper half
of the memory will not be executed. READ operations are always
available.
If WP is tied to VSS, normal memory operation is enabled, READ/
WRITE over the entire bit memory array.
This feature allows the user to assign the upper half of the memory
as ROM which can be protected against accidental programming
writes. When WRITE is disabled, slave address and word address
will be acknowledged but data will not be acknowledged.
Device Operation
The NM24C65Uxxx supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the bus as a
transmitter and the receiving devices as the receiver. The device
controlling the transfer is the master and the device that is controlled
is the slave. The master will always initiate data transfers and
provide the clock for both transmit and receive operations. Therefore, the NM24C65Uxxx is considered a slave in all applications.
CLOCK AND DATA CONVENTIONS
Data states on the SDA line can change only during SCL LOW.
SDA state changes during SCL HIGH and reserved for indicating
start and stop conditions.
START CONDITION
All commands are preceded by the start condition, which is a HIGH to
LOW transition of SDA when SCL is HIGH. The NM24C65Uxxx
continuously monitors the SDA and SCL lines for the start condition and
will not respond to any command until this condition has been met.
Refer to Figures 2 and 3.
NM24C65U 64K-Bit Serial EEPROM with Write Protect 2-Wire Bus Interface
NM24C65U Rev. B.1
STOP CONDITION
All communications are terminated by a stop condition, which is a
LOW to HIGH transition of SDA when SCL is HIGH. The stop
condition is also used by the NM24C65Uxxx to place the device
in the standby power mode.
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NM24C65U 64K-Bit Serial EEPROM with Write Protect 2-Wire Bus Interface
Write Cycle Timing
ACKNOWLEDGE
Acknowledge is a hardware convention used to indicate successful data transfers. The transmitting device, either master or slave,
will release the bus after transmitting eight bits. During the ninth
clock cycle the receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to
The NM24C65Uxxx device will always respond with an acknowledge after recognition of a start condition and its slave address. If
Write Cycle Timing (Figure 1)
SCL
SDA
8th BIT ACK
WORD n
Data Validity (Figure 2)
Figure 4
.
CONDITION
both the device and a WRITE operation have been selected, the
NM24C65Uxxx will respond with an acknowledge after the receipt
of each subsequent eight bit word.
In the READ mode the NM24C65Uxxx slave will transmit eight bits
of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is
generated by the master, the slave will continue to transmit data.
If an acknowledge is not detected, the slave will terminate further
data transmissions and await the stop condition to return to the
standby power mode.
t
WR
STOP
START
CONDITION
DS800012-4
SCL
SDA
DATA STABLE DATA
CHANGE
Definition of Start and Stop (Figure 3)
SCL
SDA
START
CONDITION
Acknowledge Response from Receiver (Figure 4)
SCL FROM
MASTER
DATA OUTPUT
FROM
TRANSMITTER
189
DS800012-5
STOP
CONDITION
DS800012-6
NM24C65U Rev. B.1
DATA OUTPUT
FROM
RECEIVER
START
ACKNOWLEDGE
6
DS800012-7
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Page 7
NM24C65U 64K-Bit Serial EEPROM with Write Protect 2-Wire Bus Interface
DEVICE ADDRESSING
Following a start condition the master must output the address of
the slave it is accessing. The most significant four bits of the slave
address are those of the device type identifier. This is fixed as
1010 for all EEPROM devices.
The next three bits identifies the device address. Address from
000 to 111 are acceptable thus allowing up to eight devices to be
connected to the IIC bus.
The last bit of the slave address defines whether a write or read
condition is requested by the master. A "1" indicates that a READ
operation is to be executed and a "0" initiates the WRITE mode.
A simple review: After the NM24C65Uxxx recognizes the start
condition, the devices interfaced to the IIC bus wait for a slave
address to be transmitted over the SDA line. If the transmitted
slave address matches an address of one of the devices, the
designated slave pulls the line LOW with an acknowledge signal
and awaits further transmissions.
Write Operations
BYTE WRITE
For a WRITE operation, two additional address bytes, with 13
active bits, are required after the SLAVE acknowledge to address
the full memory array. The first byte indicates the high-order byte
of the word address. Only the five least signicant bits can be
changed, the other bits are pre-assigned the value "0". Following
the acknowledgement from the first word address, the next byte
indicates the low-order byte of the word address. Upon receipt of
the word address, the NM24C65Uxxx responds with another
acknowledge and waits for the next eight bits of data, again,
responding with an acknowledge. The master then terminates the
transfer by generating a stop condition, at which time the
NM24C65Uxxx begins the internal write cycle to the nonvolatile
memory. While the internal write cycle is in progress, the device's
inputs are disabled and the device will not respond to any requests
from the master. Refer
Figure 5
for the Byte Write sequence.
PAGE WRITE
The NM24C65Uxxx is capable of thirty-two byte page write
operation. It is initiated in the same manner as the byte write
operation; but instead of terminating the write cycle after the first
data word is transfered, the master can transmit up to thirty-one
more words. After the receipt of each word, the device responds
with an acknowledge.
After the receipt of each word, the internal address counter
increments to the next address and the next SDA data is accepted. If the master should transmit more than thirty-two words
prior to generating the stop condition, the address counter will "roll
over" and the previous written data will be overwritten. As with the
byte write operation, all inputs are disabled until completion of the
internal write cycle. Refer
Figure 6
for the Page Write sequence.
Acknowledge Polling
Once the stop condition is isssued to indicate the end of the host's
write operation, the NM24C65Uxxx initiates the internal write
cycle. ACK polling can be initiated immediately. This involves
issuing the start condition followed by the slave address for a write
operation. If the NM24C65Uxxx is still busy with the write operation, no ACK will be returned. If the device has completed the write
operation, an ACK will be returned and the host can then proceed
with the next read or write operation.
Byte Write (Figure 5)
Bus Activity:
Master
SDA Line
Bus Activity
S
SLAVE
T
ADDRESS
A
R
T
1010 000
A
C
K
WORD
ADDRESS (1)
WORD
ADDRESS (0)
A
C
K
DATA
S
T
O
P
A
C
K
A
C
K
DS800012-8
NM24C65U Rev. B.1
7
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Page 8
NM24C65U 64K-Bit Serial EEPROM with Write Protect 2-Wire Bus Interface
Write Protection
Programming of the upper half of memory will not take place if the
WP pin is connected to V
. The device will accept slave and word
CC
addresses; but if the memory accessed is write protected by the
WP pin, the NM24C65Uxxx will not generate an acknowledge
after the first byte of data has been received, and thus the program
cycle will not be started when the stop condition is asserted.
Low VCC Lockout
NM24C65UxHx (H option) protects against data corruption during
programming by preventing any programming operations if V
drops below approximately 3.8V (VCC Lockout trip level). This is
accomplished by monitoring the "READ/WRITE" (R/W) bit in the
SLAVE address and if the R/W bit is "0," indicating a programming
operation, the VCC Lockout is activated. At that point, if the V
drops below the trip level, programming is inhibited and the device
does not issue an ACK (the output stays high). To restate, the V
Lockout feature is active from the time a WRITE bit is received up
to the time that the Master's STOP condition is received (the STOP
condition turns on the V
internal high voltage). Once program-
PP
ming has begun, the programming cycle cannot be interrupted except by removal of V
corruption.
, which could result in data
CC
Read Operation
Read operations are initiated in the same manner as write
operations, with the exception that the R/W bit of the slave address
is set to "1". There are three basic read operations: current
address read, random read and sequential read.
CURRENT ADDRESS READ
Internally the NM24C65Uxxx contains an address counter that
maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) was to
address n, the next read operation would access data from
address n+1. Upon receipt of the slave address with R/W set to
one, the NM24C65Uxxx issues an acknowledge and transmits the
eight bit word. The master will not acknowledge acknowledge the
transfer but does generate a stop condition, and therefore discontinues transmission. Refer
Figure 7
for the Current Address Read
sequence.
RANDOM READ
Random read operations allow the master to access any memory
location in a random manner. Prior to issuing the slave address
with the R/W bit set to "1", the master must first perform a "dummy"
write operation. The master issues a start condition, slave address
with the R/W bit set to "0" and then the word address it is to read
CC
from. After the word address acknowledge, the master immediately reissues the start condition and the slave address with the
R/W bit set to "1". This will be followed by an acknowledge from the
NM24C65Uxxx and then by the eight bit data. The master will not
CC
acknowledge the transfer but does generate the stop condition,
and therefore the NM24C65Uxxx discontinues transmission. Refer
CC
Figure 8
for the Random Read sequence.
SEQUENTIAL READ
Sequential reads can be initiated as either a current address read
or random access read. The first word is transmitted in the same
manner as the other read modes; however, the master now
responds with an acknowledge, indicating it requires additional
data. The NM24C65Uxxx continues to output data for each
acknowledge received. The read operation is terminated by the
master not responding with an acknowledge or by generating a
stop condition.
The data output is sequential, with the data from address n,
followed by the data n+1. The address counter for read operations
increments all word address bits, allowing the entire memory
contents to be serially read during one operation. After the entire
memory has been read, the counter "rolls over" and the
NM24C65Uxxx continues to output data for each acknowledge
received. Refer
Figure 9
for the Sequential Read sequence.
Page Write (Figure 6)
S
T
Bus Activity:
Master
SDA Line
Bus Activity
A
R
T
1010 000
SLAVE
ADDRESS
WORD
ADDRESS (1)
A
C
K
WORD
ADDRESS (0)
A
C
K
DATA n DATA n+31
A
C
K
S
T
O
P
A
C
K
DS800012-9
NM24C65U Rev. B.1
8
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Page 9
Current Address Read (Figure 7)
NM24C65U 64K-Bit Serial EEPROM with Write Protect 2-Wire Bus Interface
Random Read (Figure 8)
S
T
A
Bus Activity:
Master
SDA Line
Bus Activity
SLAVE
R
ADDRESS
T
1010 101010000
S
T
A
R
T
WORD
ADDRESS (1)
A
C
K
S
T
A
C
K
NO
S
T
A
R
T
O
P
A
C
K
SLAVE
ADDRESS
DS800012-10
S
T
DATA n
A
C
K
O
P
NO
A
C
K
DS800012-11
DATASLAVE ADDRESS
1010
A
C
K
WORD
ADDRESS (0)
A
C
K
Sequential Read (Figure 9)
S
T
Bus Activity:
Master
SDA Line
Bus Activity
A
R
T
SLAVE
ADDRESS
1010
A
C
K
S
DATA n + 1DATA n
DATA n + x
T
O
P
A
C
K
A
C
K
A
C
K
NO
A
C
K
DS800012-12
NM24C65U Rev. B.1
9
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Page 10
Physical Dimensions inches (millimeters) unless otherwise noted
0.189 - 0.197
(4.800 - 5.004)
8765
0.228 - 0.244
(5.791 - 6.198)
1234
Lead #1
IDENT
NM24C65U 64K-Bit Serial EEPROM with Write Protect 2-Wire Bus Interface
0.010 - 0.020
(0.254 - 0.508)
0.0075 - 0.0098
(0.190 - 0.249)
Typ. All Leads
x 45°
0.150 - 0.157
(3.810 - 3.988)
0.04
(0.102)
All lead tips
8° Max, Typ.
All leads
0.016 - 0.050
(0.406 - 1.270)
Typ. All Leads
0.053 - 0.069
(1.346 - 1.753)
0.014
(0.356)
0.050
(1.270)
Typ
Molded Small Out-Line Package (M8)
Order Number NM24C65UxxxM8 or NM24C65UxxxEM8
Package Number M08A
0.004 - 0.010
(0.102 - 0.254)
Seating
Plane
0.014 - 0.020
(0.356 - 0.508)
Typ.
NM24C65U Rev. B.1
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Page 11
Physical Dimensions inches (millimeters) unless otherwise noted
0.373 - 0.400
(9.474 - 10.16)
0.090
(2.286)
8765
1234
0.040
(1.016)
20° ± 1°
0.065
(1.651)
0.050
(1.270)
+
Typ.
0.250 - 0.005
(6.35 ± 0.127)
0.039
(0.991)
0.130 ± 0.005
(3.302 ± 0.127)
0.125 - 0.140
(3.175 - 3.556)
90° ± 4°
Typ
0.018 ± 0.003
(0.457 ± 0.076)
0.100 ± 0.010
(2.540 ± 0.254)
0.060
(1.524)
95° ± 5°
0.009 - 0.015
(0.229 - 0.381)
0.280
MIN
(7.112)
0.300 - 0.320
(7.62 - 8.128)
+0.040
0.325
-0.015
+1.016
8.255
-0.381
0.092
DIA
(2.337)
Pin #1 IDENT
0.030
(0.762)
0.125
(3.175)
DIA
NOM
0.045 ± 0.015
(1.143 ± 0.381)
Option 1
MAX
0.032 ± 0.005
(0.813 ± 0.127)
RAD
Pin #1
IDENT
0.020
(0.508)
Min
NM24C65U 64K-Bit Serial EEPROM with Write Protect 2-Wire Bus Interface
87
1
Option 2
0.145 - 0.200
(3.683 - 5.080)
Molded Dual-In-Line Package (N)
Order Number NM24C65UxxxN or NM24C65UxxxEN
Package Number N08E
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body, or (b) support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor
Americas Europe Hong Kong Japan Ltd.
Customer Response Center Fax: +44 (0) 1793-856858 8/F, Room 808, Empire Centre 4F, Natsume Bldg.
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2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
11
NM24C65U Rev. B.1
www.fairchildsemi.com
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