Page 1
11C90/11C91 650 MHz Prescalers
11C90/11C91
650 MHz Prescalers
General Description
The 11C90 and 11C91 are high-speed prescalers designed
specifically for communication and instrumentation applications. All discussions and examples in this data sheet are
applicable to the 11C91 as well as the 11C90.
The 11C90 will divide by 10 or 11 and the 11C91 by 5 or 6,
both over a frequency range from DC to typically 650 MHz.
The division ratio is controlled by the Mode Control. The
divide-by-10 or -11 capability allows the use of pulse swallowing techniques to control high-speed counting modulos
by lower-speed circuits. The 11C90 may be used with either
ECL or TTL power supplies.
In addition to the ECL outputs Q and Q
an ECL-to-TTL converter and a TTL output. The TTL output
operates from the same V
but a separate pin is used for the TTL circuit V
mizes noise coupling when the TTL output switches and
CC
Logic Symbol
, the 11C90 contains
and VEElevels as the counter,
. This mini-
EE
Not Intended For New Designs
August 1992
also allows power consumption to be reduced by leaving
the separate V
To facilitate capacitive coupling of the clock signal, a 400X
resistor (V
Connecting this resistor to the Clock Pulse input (CP) automatically centers the input about the switching threshold.
Maximum frequency operation is achieved with a 50% duty
cycle.
Each of the Mode Control inputs is connected to an internal
2kXresistor with the other end uncommitted (RM
RM
). An M input can be driven from a TTL circuit operating
2
from the same V
ciated 2 kX resistor to V
from the ECL circuit, the 2 kX resistor can be left open or, if
required, can be connected to V
resistor.
pin open if the TTL output is not used.
EE
) is connected internally to the VBBreference.
REF
by connecting the free end of the asso-
CC
. When an M input is driven
CCA
to act as a pull-down
EE
and
1
Connection Diagram
16-Pin DIP
TL/F/9892– 2
Pin Names Description
CE Count Enable Input (Active LOW)
CP Clock Pulse Input
M
n
MS Asynchronous Master Set Input
Q, Q
QTTL TTL Output
RM
n
V
REF
C
1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.
Count Modulus Control Input
ECL Outputs
2kXResistor to M
400X Resistor to V
TL/F/9892
n
BB
TL/F/9892– 1
Page 2
Absolute Maximum Ratings
Above which the useful life may be impaired
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature
Maximum Junction Temperature (TJ)
Supply Voltage Range
Input Voltage (DC) V
Output Current (DC Output HIGH)
Operating Range
b
65§Ctoa150§C
a
b
7.0V to GND
to GND
EE
b
b
5.7V tob4.7V
150§C
50 mA
Recommended Operating
Conditions
Ambient Temperature (T
Commercial 0
Military
Supply Voltage (V
Commercial
Military
)
A
)
EE
Lead Temperature
(Soldering, 10 sec.) 300
C
§
TTL Input/Output Operation
DC Electrical Characteristics
Over Operating Temperature and Voltage Range unless otherwise noted, Pins 12 and 13eGND
Symbol Parameter Min
V
IH
V
IL
V
OH
V
OL
I
IL
I
SC
Input HIGH Voltage
and M2Inputs Voltage (Note 4), V
M
1
Input LOW Voltage
and M2Inputs Voltage (Note 4), V
M
1
Output HIGH Voltage
QTTL Output I
Output LOW Voltage
QTTL Output I
Input LOW Current
and M2Inputs V
M
1
Output Short Circuit
Current V
2.3 3.3 V
b
20
Typ
(Note 3)
Max Units Conditions
4.1 V
3.3 V
0.2 0.5 V
b
2.3
b
35
b
5.0 mA
b
80 mA
Guaranteed Input HIGH Threshold
Guaranteed Input LOW Threshold
e
V
V
CC
eb
OH
e
V
V
CC
e
20.0 mA
OL
e
V
V
CC
e
0.4V, Pins 6, 7eV
IN
e
V
V
CC
e
OUT
Min Typ Max
C
§
b
55§C
b
5.7Vb5.2V
b
5.7Vb5.2V
CC
CC
e
Min,
CCA
640 mA
e
Min,
CCA
e
Max,
CCA
e
Max,
CCA
0.0V, Pin 14eV
a
e
V
CCA
e
V
CCA
CC
CC
a
125§C
b
b
e
e
75§C
4.7V
4.7V
5.0V
5.0V
AC Electrical Characteristics
e
V
CCA
e
5.0V Nominal, V
V
CC
e
GND, T
EE
A
ea
25§C
Symbol Parameter Min Typ Max Units Conditions
t
PLH
t
PHL
t
PLH
t
s
t
h
t
TLH
t
THL
f
MAX
Propagation Delay, (50% to 50%)
CP to QTTL
Propagation Delay, (50% to 50%)
MS to QTTL
61014 ns
12 17 ns
Mode Control Setup Time 4 2 ns
Mode Control Hold Time 0
Output Rise Time
(20% to 80%)
Output Fall Time
(80% to 20%)
Count Frequency 550 650
600 650 0
b
2ns
10 ns
2ns
MHz
See
Figure 1
b
55§Ctoa125§C
Ctoa75§C
§
Clock Input AC Coupled
350 mV Peak-to-Peak
Sinewave (Note 5)
2
Page 3
ECL OperationÐCommercial Version
DC Electrical Characteristics
e
V
CC
e
V
GND, V
CCA
Symbol Parameter Min Typ Max Units T
V
OH
V
OL
V
IH
V
IL
I
IH
Output HIGH Voltage
Q and Q
Output LOW Voltage
Q and Q
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current V
CP Input (Note 1) 400
MS Input 400 mA
M
and M2Input 250
1
I
IL
I
EE
V
EE
V
REF
Input LOW Current 0.5 mA
Power Supply Current
Operating Supply
Voltage Range
Reference Voltage
EE
eb
5.2V
b
b
b
b
b
b
b
b
b
b
b
b
b
b
1060
1025
980
1820
1135
1095
1035
1870
1850
1830
110
119
5.7
1550
b
995
b
960
b
910
b
1705
b
75 mA
b
5.2
b
905 0§C Loade50X tob2V
b
880 mV
b
805
b
1620 mV
b
840 0§C Guaranteed Input HIGH
b
810 mV
b
720
b
1500 0§C Guaranteed Input LOW
b
1485 mV
b
1460
b
4.7 V
b
1150 mV
a
a
0
a
a
a
a
a
a
a
a
a
0
a
0
a
a
A
Conditions
25§C
75§C
Cto
§
75§C
25§C Signal (Note 6)
75§C
25§C Signal
75§C
e
V
IN
25§C
IHA
25§C
25§C
25§CV
C to Pins 6, 7, 13 not connected
§
e
V
IN
ILB
75§C
Cto
§
75§C
e
eb
25§C
V
I
N
RM
eb
1
V
RM
10.0 mA
5.2V
2
AC Electrical Characteristics
e
T
A
0§Cto
a
75§C, V
CC
e
e
V
GND, V
CCA
Symbol Parameter
t
t
t
t
t
t
t
f
PLH
PHL
PLH
s
h
TLH
THL
MAX
Propagation Delay,
(50% to 50%) CP to Q R
Propagation Delay,
(50% to 50%) MS to Q
Setup Time, M to CP 2.0 4.0 2.0 2.0 ns (20% to 80%)
Hold Time, M to CP
b
Output Rise Time
(20% to 80%)
Output Fall Time
(80% to 20%)
Maximum Clock Frequency AC Coupled Input 350 mV
eb
5.2V
EE
0
Typ
C
§
a
25§C
Min Typ Max
1.8 1.3 2.0 3.0 2.5 ns
a
75§C
Typ
Units Conditions
Output:
L
3.7 4.0 6.0 4.5 ns Input:
t
ri
2.0 0.0
b
2.0
b
2.0 ns
See
1.0 1.0 2.0 1.0 ns
1.0 1.0 2.0 1.0 ns
650 600 650 625 MHz
Peak-to-Peak. f
Guaranteed to be 575 MHz
Min at 0
3
e
50X tob2.0V
e
e
t
fi
Figure 1
Ctoa75§C.
§
2.0g0.1 ns
MAX
is
Page 4
ECL OperationÐMilitary Version
DC Electrical Characteristics
e
V
CC
e
V
GND, V
CCA
Symbol Parameter Min Typ Max Units T
V
OH
V
OL
V
IH
V
IL
I
IH
Output HIGH Voltage
Q and Q
Output LOW Voltage
Q and Q
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current V
CP Input (Note 1) 400
MS Input 400 mA
M
and M2Input 250
1
I
IL
I
EE
V
EE
V
REF
Input LOW Current 0.5 mA
Power Supply Current
Operating Supply
Voltage Range
Reference Voltage
EE
eb
5.2V
b
b
b
b
b
b
b
b
b
b
b
b
b
1100
980
910
1820
1190
1095
975
1890
1850
1800
110
5.7
1550
b
1030
b
910
b
820
b
1705
b
b
119 mA
b
5.2
b
900
b
820 mV
b
670
b
1620 mV
b
905
b
810 mV
b
690
b
1525
b
1485 mV
b
1435
75 mA
b
4.7 V
b
1150 mV
b
a
a
b
55§Cto
a
b
a
a
b
a
a
a
a
a
a
a
b
55§Cto
a
b
55§Cto
a
a
A
Conditions
55§C Loade100X tob2V
25§C
125§C
125§C
55§C Guaranteed Input HIGH
25§C Signal (Note 6)
125§C
55§C Guaranteed Input LOW
25§C Signal
125§C
e
V
IN
25§C
IHA
25§C
25§C
25§CV
e
V
IN
ILB
25§C Pins 6, 7, 13 not connected
125§C
125§C
e
25§C
V
I
RM
N
1
eb
V
RM
10.0 mA
2
eb
5.2V
AC Electrical Characteristics
eb
T
55§Ctoa125§C, V
A
Symbol Parameter
t
PLH
t
PHL
t
PLH
t
s
t
h
t
TLH
t
THL
f
MAX
Note 1: Conditions for testing, not shown in the Table, are chosen to guarantee operation under ‘‘worst case’’ conditions.
Note 2: The specified limits represent the ‘‘worst case’’ value for the parameter. Since these ‘‘worst case’’ values normally occur at the temperature and supply
voltage extremes, additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges.
Note 3: Typical limits are at V
Note 4: The M
reference, as in normal TTL practice, effectively makes the threshold vary directly with V
signal swing about threshold of
required V
Note 5: TTL Output Signal swing is guaranteed at f
Note 6: M
Propagation Delay,
(50% to 50%) CP to Q R
Propagation Delay,
(50% to 50%) MS to Q
Setup Time, M to CP 2.0 4.0 2.0 2.0 ns
Hold Time, M to CP
Output Rise Time
(20% to 80%)
Output Fall Time
(80% to 20%)
Maximum Clock Frequency AC Coupled Input 350 mV
and M2threshold specifications are normally referenced to the VCCpotential, as shown in the ECL operation tables. Using VEE(GND) as the
1
range, as discussed in the Functional Description and shown in
IH
or M2can be tied to VCCfor fixed divide-by-ten operation.
1
e
CC
e
V
GND, V
CCA
b
55§C
Typ
1.5 1.3 2.0 3.0 3.0 ns
3.5 4.0 6.0 5.0 ns
b
2.0 0.0
eb
5.2V
EE
a
25§C
Min Typ Max
b
2.0
a
125§C
Typ
b
2.0 ns
Units Conditions
Output:
e
50X tob2.0V
L
Input:
e
e
t
t
2.0g0.1 ns
ri
fi
(20% to 80%)
See
Figure 1
1.0 1.0 2.0 1.0 ns
1.0 1.0 2.0 1.0 ns
700 600 650 600 MHz
Peak-to-Peak. f
Guaranteed to be 550 MHz
Min at
e
5.0V and T
CC
g
0.4V is adequate, which gives the state VIHand VILvalues. The internal 2 kX resistors are intended to pull TTL outputs up to the
ea
25§C.
A
over temperature range.
MAX
Figure 5.
. Threshold is typically 1.3V below VCC(e.g.,a3.7V at V
CC
MAX
b
55§Ctoa125§C.
ea
CC
is
5V). A
4
Page 5
TL/F/9892– 3
Conditions:
ea
V
2.0V
CC
eb
3.2V
V
EE
e
50X (scope input impedance)
R
T
e
Jig and stray capacitancek5.0 pF
C
L
e
e
L
equal 50X impedance lines
I
1
2
e
0.1 pF
C
Note 7: Use high impedance to test QTTL.
Connect pin 13 to V
Note 8: For High frequency test use AC coupled input as in
Adjust input amplitude to 350 mV peak-to-peak.
.
EE
Figure 3
.
FIGURE 1. AC Test Circuit
5
TL/F/9892– 4
Page 6
Functional Description
The 11C90 contains four ECL Flip-Flops, an ECL to TTL
converter and a Schottky TTL output buffer with an active
pull-up. Three of the Flip-Flops operate as a synchronous
shift counter driving the fourth Flip-Flop operating as an
asynchronous toggle. The internal feedback logic is such
that the TTL output and the Q ECL output are HIGH for six
clock periods and LOW for five clock periods. The Mode
Control (M) inputs can modify the feedback to make the
output HIGH for five clock periods and LOW for five clock
periods, as indicated in the Count Sequence Table.
The feedback logic is such that the instant the output goes
HIGH, the circuit is already committed as to whether the
output period will be 10 or 11 clock periods long. This
means that subsequent changes in an M input signal, including decoding spikes, will have no effect on the current
output period. The only timing restriction for an M input signal is that it be in the desired state at least a setup time
before the clock that follows the HHLL state shown in the
table. The allowable propagation delay through external logic to an M input is maximized by designing it to use the
positive transition of the 11C90 output as its active edge.
This gives an allowable delay of ten clock periods, minus
the CP to Q delay of the 11C90 and the M to CP setup time.
If the external logic uses the negative output transition as its
active edge, the allowable delay is reduced to five clock
periods minus the previously mentioned delay and setup
time.
Capacitively coupled triggering is simplified by the 400X resistor which connects pin 15 to the internal V
By connecting this to the CP input, as shown in
clock is automatically centered about the input threshold. A
clock duty cycle of 50% provides the fastest operation,
since the Flip-Flops are Master-Slave types with offset clock
thresholds between master and slave. This feature ensures
that the circuit will operate with clock waveforms having
very slow rise and fall times, and thus, there is no maximum
frequency restriction. Recommended minimum and maximum clock amplitude as a function of a frequency and temperature are shown in the graph labeled
CP or any other input is driven from another ECL circuit,
normal ECL termination methods are recommended. One
method is indicated in
Figure 4
. Other ECL termination
methods are discussed in the F100K ECL Design Guide
(Section 5 of Databook).
BB
Figure 2
reference.
Figure 3
. When the
, the
FIGURE 3. Capacitively Coupled Clocking
TL/F/9892– 10
TL/F/9892– 11
ZOX 50 75 100
R1X 80.6 121 162
R2X 130 196 261
eb
V
EE
5.2V, V
e
eb
0V, V
CC
2.0V
TT
FIGURE 4. Clocking by ECL Source via Terminated Line
When an M input is to be driven from a TTL output operating
from the same V
resistor can be used to pull the TTL output up as shown in
Figure 5
. Some types of TTL outputs will only pull up to
within two diode drops of V
11C90 inputs. The resistor will pull the signal up through the
and ground (VEE), the internal 2 kX
CC
, which is not high enough for
CC
threshold region, although this final rise may be somewhat
slow, depending on wiring capacitance. A resistor network
that gives faster rise and also lower impedance is shown in
Figure 6
.
FIGURE 2. AC Coupled Triggering Characteristics
TL/F/9892– 5
FIGURE 5. Using Internal Pull-Up with TTL Source
TL/F/9892– 12
TL/F/9892– 13
FIGURE 6. Faster Low Impedance TTL to ECL Interface
6
Page 7
Functional Description (Continued)
The ECL outputs have no pull-down resistors and can drive
series or parallel terminated transmission lines. For short
interconnections that do not require impedance matching, a
270X to 510X resistor to V
V
level. Both VCCpins must always be used and should
OL
can be used to establish the
EE
Logic Diagram 11C90
be connected together as close to the package as possible.
Pin 12 must always be connected to the V
supply, while pin 13 is required only if the TTL output is
used. Low impedance V
pass capacitors are recommended to prevent crosstalk.
and VEEdistribution and RF by-
CC
side of the
EE
Note: This diagram is provided for understanding of logic operation only. It should not be used for evaluation of propagation delays as many internal functions are
achieved more efficiently than shown.
Count Sequence Table 11C90
Operating Mode Table 11C90
TL/F/9892– 6
Inputs Output
MS CE M
M
1
2
Response
H X X X Set HIGH
L H X X Hold
d
11
d
10
d
10
Note: A HIGH on MS forces all Qs HIGH.
TL/F/9892– 7
LLLL
LLHX
LLXH
HeHIGH Voltage Level
e
LOW Voltage Level
L
e
Don’t Care
X
7
Page 8
Logic Diagram 11C91
TL/F/9892– 8
Count Sequence Table 11C91
Operating Mode Table 11C91
Inputs Output
MS CE M
M
1
2
Response
H X X X Set HIGH
L H X X Hold
d
6
d
5
d
5
Note: A HIGH on MS forces all Qs HIGH.
TL/F/9892– 9
LLLL
LLXH
LLHX
e
H
HIGH Voltage Level
e
LOW Voltage Level
L
e
Don’t Care
X
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
11C90/91 D C QR
Device Number Special Variations
(basic) QR
Package Code
DeCeramic Dual In-Line Temperature Range
e
Commercial grade device
with burn-in
e
C
Commercial (0§Ctoa85§C)
8
Page 9
9
Page 10
Physical Dimensions inches (millimeters)
11C90/11C91 650 MHz Prescalers
16 Lead Ceramic Dual-In-Line Package (D)
NS Package Number J16A
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
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Corporation Europe Hong Kong Ltd. Japan Ltd.
1111 West Bardin Road Fax: (
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Tel: 1(800) 272-9959 Deutsch Tel: (
Fax: 1(800) 737-7018 English Tel: (
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
Fran3ais Tel: (
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a
49) 0-180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2309
a
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