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100397QI

Datasheet 100397QIX, 100397QI, 100397QCX, 100397QC, 100397PC Datasheet (Fairchild Semiconductor)

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© 2000 Fairchild Semiconductor Corporation DS010971 www.fairchildsemi.com
January 1992 Revised August 2000
100397 Quad Differential ECL/TTL Translating Transceiver with Latch
100397 Quad Differential ECL/TTL Translating Transceiver
with Latch
General Description
Ω ECL load with cutoff capabil-
ity, and will sink a 64 mA TTL load. The 100397 is ideal for mixed technology applications utilizing either an ECL or TTL backplane.
The direction of translat ion is set by the direction control pin (DIR). The DIR pin on the 100397 accepts F 100K E CL logic levels. An ECL LOW on DI R sets u p the ECL pi ns as inputs and TTL pins as outputs. An EC L HIGH on D IR sets up the TTL pins as inputs and ECL pins as outputs.
A LOW on the outp ut en able inp ut pi n (OE) hol ds the ECL output in a cut-off state and the TTL outputs at a high impedance level. A HIGH on the latch enable input (LE) latches the data at both inputs even though only one output is enabled at the time. A LOW on LE makes the latch trans­parent.
The cut-off state is designe d to be more negative than a normal ECL LOW level. This allows the output emitterfol­lowers to turn off when the termination supply is
−2.0V, pre-
senting a high impedance to the data bus. This high impedance reduces termination power and prevents loss of low state noise margin when several loads share the bus.
The 100397 is designed with FAST
TTL output buffers,
featuring optimal DC drive an d capabl e of quickly cha rging and discharging highly capacitive loads. All inputs have 50 K
Ω pull-down resistors.
Features
■ Differential ECL input/output structure
■ 64 mA FAST TTL outputs
■ 25
Ω differential ECL outputs with cut-off
■ Bi-directional translation
■ 2000V ESD protection
■ Latched outputs
■ 3-STATE outputs
■ Voltage compensated operating range
= −4.2V to −5.7V
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
FAST is a registered trademark of Fairc hild Semiconductor Corporation.
Order Number Package Number Package Description
100397PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 100397QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 100397QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (
−40°C to +85°C)
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100397
Logic Symbol
Connection Diagrams
24-Pin DIP
28-Pin PLCC
Pin Descriptions
All pins function at 100K ECL levels except for T0–T3.
Tr uth Table
H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance
Note 1: ECL input to TTL out put mode. Note 2: TTL input to ECL output mode. Note 3: Retains data present before LE set HIGH. Note 4: Latch is transparent.
Pin Names Description
E
0–E3
ECL Data I/O
E
0–E3
Complementary ECL Data I/O
T
0–T3
TTL Data I/O OE Output Enable Input (ECL Levels) LE Latch Enable Input (ECL Levels) DIR Direction Control Input (ECL levels) GNDECL ECL Ground GNDECLO ECL Output Ground GNDS ECL Ground-to-Substrate V
EE
ECL Quiescent Power Supply V
EED
ECL Dynamic Power Supply GNDTTL TTL Quiescent Ground GNDTTLD TTL Dynamic Ground V
TTL
TTL Quiescent Power Supply V
TTLD
TTL Dynamic Power Supply
LE DIR OE
ECL TTL
Notes
Port Port
000LOWZ
(Cut-Off) 0 0 1 Input Output (Note 1)(Note 4) 010LOWZ
(Cut-Off) 0 1 1 Output Input (Note 2)(Note 4) 1 0 0 Input Z (Note 1)(Note 3) 1 0 1 Latched X (Note 1)(Note 3) 1 1 0 LOW Input (Note 2)(Note 3)
(Cut-Off) 1 1 1 Latched X (Note 2)(Note 3)
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Functional Diagram
Note: LE, DIR, and OE use ECL logic levels
Detail
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100397
Absolute Maximum Ratings(Note 5) Recommended Operating
Conditions
Note 5: The “Absolute Maximum Ratings” are those values beyon d which
the safety of the dev ice cannot be guaranteed. T he device sh ould not be operated at these limit s. The parametric values defin ed in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recomme nded O peratin g Cond itions ” table will defin e the condition s for actual device operation.
Note 6: ESD testing conf orm s t o M I L-STD-883, Method 3015. Note 7: Either voltage lim it or c urrent limit is sufficient to protect inputs.
Commercial Version TTL-to-ECL DC Electrical Characteristics
(Note 8)
V
EE
= −4.2V to −5.7V, GND = 0V, TC = 0°C to +85°C, V
TTL
= +4.5V to +5.5V
Note 8: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the all owable syste m opera ti ng r ange s. Co ndi ti ons fo r t est ing shown in the ta ble s are cho­sen to guarantee operation under “worst case” conditions.
Storage Temperature (T
STG
) −65°C to +150°C
Maximum Junction Temperature
(T
J
) +150°C
V
EE
Pin Potential to Ground Pin −7.0V to +0.5V
V
TTL
Pin Potential to Ground Pin −0.5V to +6.0V
ECL Input Voltage (DC) V
EE
to +0.5V
ECL Output Current
(DC Output HIGH)
−50 mA
TTL Input Voltage (Note 7)
−0.5V to +7.0V
TTL Input Current (Note 7)
−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State 3-STAT E Outp ut
−0.5V to +5.5V
Current Applied to TTL
Output in LOW State (Max) twice the Rated I
OL
(mA)
ESD (Note 6)
≥2000V
Case Temperature (T
C
)
Commercial 0
°C to +85°C
Industrial
−40°C to +85°C
ECL Supply Voltage (V
EE
) −5.7V to −4.2V
TTL Supply Voltage (V
TTL
) +4.5V to +5.5V
Symbol Parameter Min Typ Max Units Conditions
V
OH
Output HIGH Voltage −1025 −955 −870 mV VIN = V
IH(Max)
or V
IL(Min)
V
OL
Output LOW Voltage −1830 −1705 −1620 mV Loading with 50Ω to − 2V Cutoff Voltage OE and LE Low, DIR High
−2000 −1950 mV V
IN
= V
IH(Max)
or VIL(Min),
Loading with 50Ω to −2V
V
OHC
Output HIGH Voltage
−1035 mV
Corner Point High VIN = V
IH(Min)
or V
IL(Max)
V
OLC
Output LOW Voltage
−1610 mV
Loading with 50Ω to −2V
Corner Point Low
V
IH
Input HIGH Voltage 2.0 5.0 V Over V
TTL
, VEE, TC Range
V
IL
Input LOW Voltage 0 0.8 V Over V
TTL
, VEE, TC Range
I
IH
Input HIGH Current 5.0 µAVIN = +2.7V
I
BVIT
Input HIGH Current
0.5 mA V
IN
= 5.5V
Breakdown (I/O)
I
IL
Input LOW Current −1.0 mA VIN = +0.5V
V
FCD
Input Clamp
−1.2 V IIN = −18 mA
Diode Voltage
I
EE
VEE Supply Current −99 −50 LE Low, OE and DIR HIGH
Inputs Open
I
EEZ
VEE Supply Current −159 −90 LE and OE Low, Dir HIGH
Inputs Open
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Commercial Version (Continued) ECL-to-TTL DC Electrical Characteristi cs (Note 9)
V
EE
= −4.2V to −5.7V, GND = 0V, TC = 0°C to +85°C, CL = 50 pF, V
TTL
= +4.5V to +5.5V
Note 9: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasin g the al l owable syste m opera ti ng ran ge s. Cond it i ons fo r t estin g sho w n in the tabl es are cho­sen to guarantee operation under “worst case” conditions.
DIP and PCC TTL-to-ECL AC Electrical Characteristics
V
EE
= −4.2V to −5.7V, V
TTL
= +4.5V to +5.5V
Symbol Parameter Min Typ Max Units Conditions
V
OH
Output HIGH Voltage 2.7 3.1 V IOH = −3 mA, V
TTL
= 4.75V
2.4 2.9 V IOH = −3 mA, V
TTL
= 4.50V
V
OL
Output LOW Voltage 0.3 0.5 V IOL = 24 mA, V
TTL
= 4.50V
V
IH
Input HIGH Voltage −1165 −870 mV Guaranteed HIGH Signal for All Inputs
V
IL
Input LOW Voltage −1830 −1475 mV Guaranteed LOW Signal for All Inputs
V
DIFF
Input Voltage Differential 150 mV Required for Full Output Swing
V
CM
Common Mode Voltage GNDECL − 2.0 GNDECL − 0.5 V
I
IH
Input HIGH Current E
0–E3
, E0–E
3
240 µAVIN = V
IH(Max)
OE, LE, DIR 35
I
CEX
Output HIGH
50 µAV
OUT
= V
TTL
Leakage Current
I
ZZ
Bus Drainage Test 500 µAV
OUT
= 5.25V
V
TTL
= 0.0V
I
IL
Input LOW Current 0.5 0 µAVIN = V
IL(Min)
I
OZHT
3-STATE Current
70 µAV
OUT
= +2.7V
Output High
I
OZLT
3-STATE Current
−650 µAV
OUT
= +0.5V
Output Low
I
OS
Output Short-Circuit
−100 −225 mA V
OUT
= 0.0V, V
TTL
= +5.5V
Current
I
TTL
V
TTL
Supply Current 39 mA TTL Outputs LOW
27 mA TTL Outputs HIGH 39 mA TTL Outputs in 3-STATE
Symbol Parameter
TC = 0°CT
C
= 25°CT
C
= 85°C
Units Conditions
MinMaxMinMaxMinMax
f
MAX
Maximum Clock Frequency 180 180 180 MHz
t
PLH
Tn to En, E
n
0.9 2.1 0.8 2.2 0.7 2.5 ns Figures 1, 3
t
PHL
(Transparent)
t
PLH
LE to En, E
n
1.2 2.3 1.3 2.4 1.4 2.5 ns Figures 1, 3
t
PHL
t
PZH
OE to En, E
n
2.5 4.5 2.5 4.5 2.5 4.6 ns Figures 1, 3
(Cutoff to HIGH)
t
PHZ
OE to En, E
n
2.1 3.8 2.3 4.0 2.5 4.5 ns Figures 1, 3
(HIGH to Cutoff)
t
PHZ
DIR to En, E
n
2.0 3.5 2.1 3.7 2.3 4.2 ns Figures 1, 3
(HIGH to Cutoff)
t
S
Tn to LE 0.8 0.8 0.8 ns Figures 1, 3
t
H
Tn to LE 0.6 0.6 0.6 ns Figures 1, 3
t
TLH
Transition Time
0.8 2.8 0.8 2.8 0.8 2.8 ns Figures 1, 3
t
THL
20% to 80%, 80% to 20%
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Commercial Version (Continued) DIP and PCC ECL-to-TTL AC Electrical Characteristics
V
EE
= −4.2V to −5.7V, V
TTL
= +4.5V to +5.5V, C
L
= 50 pF
Industrial Version TTL-to-ECL DC Electrical Characteristics
(Note 10)
V
EE
= −4.2V to −5.7V, GND = 0V, TC = −40°C to +85°C, V
TTL
= +4.5V to +5.5V
Note 10: The specified limits repres ent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the all owable syste m opera ti ng r ange s. Co ndi ti ons fo r t est ing shown in the ta ble s are cho­sen to guarantee operation under “worst case” conditions.
Symbol Parameter
TC = 0°CT
C
= 25°CT
C
= 85°C
Units Conditions
Min Max Min Max Min Max
f
MAX
Maximum Clock Frequency 75 75 75 MHz
t
PLH
En, En to T
n
1.7 4.9 1.7 5.1 1.8 5.8 ns Figures 2, 4
t
PHL
(Transparent)
t
PLH
LE to T
n
2.2 4.0 2.2 4.0 2.3 4.1 ns Figures 2, 4
t
PHL
3.3 5.2 3.4 5.4 3.8 6.1
t
PZH
OE to T
n
3.2 5.6 3.3 5.7 3.6 6.3 ns Figures 2, 5
t
PZL
(Enable Time) 4.9 8.3 5.1 8.5 5.6 9.2
t
PHZ
OE to T
n
3.6 8.6 3.5 8.3 3.5 7.5 ns Figures 2, 5
t
PLZ
(Disable Time) 3.4 6.9 3.5 6.7 3.6 6.7
t
PHZ
DIR to T
n
3.5 8.1 3.5 8.1 3.5 7.6 ns Figures 2, 6
t
PLZ
(Disable Time) 3.4 6.8 3.4 6.7 3.6 6.7
t
S
En, En to LE 0.6 0.6 0.6 ns Figures 2, 4
t
H
En, En to LE 0.7 0.7 0.7 ns Figures 2, 4
tPW(L) Pulse Width LE 2.0 2.0 2.0 ns Figures 2, 4
Symbol Parameter Min Typ Max Units Conditions
V
OH
Output HIGH Voltage −1085 −955 −870 mV VIN = V
IH(Max)
or V
IL(Min)
V
OL
Output LOW Voltage −1830 −1705 −1575 mV Loading with 50Ω to −2V Cutoff Voltage OE and LE LOW, DIR HIGH
−2000 −1900 mV V
IN
= V
IH(Max)
or V
IL(Min)
,
Loading with 50Ω to −2V
V
OHC
Output HIGH Voltage
−1095 mV
Corner Point HIGH V
IN
= V
IH(Min)
or V
IL(Max)
V
OLC
Output LOW Voltage
−1565 mV
Loading with 50Ω to −2V
Corner Point LOW
V
IH
Input HIGH Voltage 2.0 5.0 V Over V
TTL
, VEE, TC Range
V
IL
Input LOW Voltage 0 0.8 V Over V
TTL
, VEE, TC Range
I
IH
Input HIGH Current 5.0 µAVIN = +2.7V
I
BVIT
Input HIGH Current
0.5 mA V
IN
= 5.5V
Breakdown (I/O)
I
IL
Input LOW Current −1.0 mA VIN = +0.5V
V
FCD
Input Clamp
−1.2 V IIN = −18 mA
Diode Voltage
I
EE
VEE Supply Current −99 −40 LE Low, OE and DIR HIGH
Inputs Open
I
EEZ
VEE Supply Current −159 −90 LE and OE LOW, Dir HIGH
Inputs Open
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Industrial Version (Con tinu ed) ECL-to-TTL DC Electrical Characteristi cs (Note 11)
V
EE
= −4.2V to −5.7V, GND = 0V, TC = −40°C to +85°C, CL = 50 pF, V
TTL
= +4.5V to +5.5V
Note 11: The specified limits represen t the “worst case” value for the param ete r. Since these valu es nor mally occur at the tem perat ure ex treme s, ad ditio nal noise immunity and guardbanding can be achieved by decreasin g the al l owable syste m opera ti ng ran ge s. Cond it i ons fo r t estin g sho w n in the tabl es are cho­sen to guarantee operation under “worst case” conditions.
PCC TTL-to-ECL AC Electrical Characteristics
V
EE
= −4.2V to −5.7V, V
TTL
= +4.5V to +5.5V
Symbol Parameter Min Typ Max Units Conditions
V
OH
Output HIGH Voltage 2.7 3.1 V IOH = −3 mA, V
TTL
= 4.75V
2.4 2.9 V IOH = −3 mA, V
TTL
= 4.50V
V
OL
Output LOW Voltage 0.3 0.5 V IOL = 24 mA, V
TTL
= 4.50V
V
IH
Input HIGH Voltage −1170 −870 mV Guaranteed HIGH Signal for All Inputs
V
IL
Input LOW Voltage −1830 −1480 mV Guaranteed LOW Signal for All Inputs
V
DIFF
Input Voltage Differential 150 mV Required for Full Output Swing
V
CM
Common Mode Voltage GNDECL − 2.0 GNDECL − 0.5 V
I
IH
Input HIGH Current VIN = V
IH(Max)
E0–E3, E0–E
3
300 µA
OE, LE, DIR 35
I
CEX
Output HIGH
50 µAV
OUT
= V
TTL
Leakage Current
I
ZZ
Bus Drainage Test 500 µAV
OUT
= 5.25V
V
TTL
= 0.0V
I
IL
Input LOW Current 0.5 0 µAVIN = V
IL(Min)
I
OZHT
3-STATE Current
70 µAV
OUT
= +2.7V
Output HIGH
I
OZLT
3-STATE Current
−650 µA
V
OUT
= +0.5V
Output LOW
I
OS
Output Short-Circuit Current −100 −225 mA V
OUT
= 0.0V, V
TTL
= +5.5V
I
TTL
V
TTL
Supply Current 39 mA TTL Outputs LOW
27 mA TTL Outputs HIGH 39 mA TTL Outputs in 3-STATE
Symbol Parameter
TC = −40°CT
C
= +25°CT
C
= +85°C
Units Conditions
MinMaxMinMaxMinMax
f
MAX
Maximum Clock Frequency 180 180 180 MHz
t
PLH
Tn to En, E
n
0.9 2.4 0.8 2.2 0.7 2.5 ns Figures 1, 3
t
PHL
(Transparent)
t
PLH
LE to En, E
n
1.2 2.3 1.3 2.4 1.4 2.5 ns Figures 1, 3
t
PHL
t
PZH
OE to En, E
n
1.9 3.8 2.5 4.5 2.5 4.6 ns Figures 1, 3
(Cutoff to HIGH)
t
PHZ
OE to En, E
n
2.5 4.7 2.3 4.0 2.5 4.5 ns Figures 1, 3
(HIGH to Cutoff)
t
PHZ
DIR to En, E
n
1.8 3.5 2.1 3.7 2.3 4.2 ns Figures 1, 3
(HIGH to Cutoff)
t
S
Tn to LE 0.8 0.8 0.8 ns Figures 1, 3
t
H
Tn to LE 0.6 0.6 0.6 ns Figures 1, 3
t
TLH
Transition Time
0.8 2.8 0.8 2.8 0.8 2.8 ns Figures 1, 3
t
THL
20% to 80%, 80% to 20%
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100397
Industrial Version (Continued) PCC ECL-to-TTL AC Electrical Characteristics
V
EE
= −4.2V to −5.7V, V
TTL
= +4.5V to +5.5V, C
L
= 50 pF
Symbol Parameter
TC = −40°CT
C
= +25°CT
C
= +85°C
Units Conditions
Min Max Min Max Min Max
f
MAX
Maximum Clock Frequency 75 75 75 MHz
t
PLH
En, En to T
n
1.7 4.9 1.7 5.1 1.8 5.8 ns Figures 2, 4
t
PHL
(Transparent)
t
PLH
LE to T
n
2.2 4.3 2.2 4.0 2.3 4.1 ns Figures 2, 4
t
PHL
3.3 5.2 3.4 5.4 3.8 6.1
t
PZH
OE to T
n
3.1 5.6 3.3 5.7 3.6 6.3 ns Figures 2, 5
t
PZL
(Enable Time) 4.8 8.3 5.1 8.5 5.6 9.2
t
PHZ
OE to T
n
3.5 9.2 3.5 8.3 3.5 7.5 ns Figures 2, 5
t
PLZ
(Disable Time) 3.2 7.3 3.5 6.7 3.6 6.7
t
PHZ
DIR to T
n
3.5 8.8 3.5 8.1 3.5 7.6 ns Figures 2, 6
t
PLZ
(Disable Time) 3.2 7.2 3.4 6.7 3.6 6.7
t
S
En, En to LE 0.6 0.6 0.6 ns Figures 2, 4
t
H
En, En to LE 0.7 0.7 0.7 ns Figures 2, 4
tPW(L) Pulse Width LE 2.0 2.0 2.0 ns Figures 2, 4
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Test Circuitry (TTL-to-ECL)
Notes:
R
t
= 50Ω termination . When an input or ou tpu t is b eing m oni tored by a sc ope, Rt is supplied by the scope ’s 50Ω resist anc e. Wh en an inp ut or ou tput is not
being monit ored, and external 50Ω resistance must be applied to serve as R
t
. TTL and ECL force sig nals are brought to the DUT v ia 50Ω coax lines. V
TTL
is decoupled to ground with 0.1 µF to ground, VEE is decoupled to ground w it h 0.01 µF and GND is connected to ground.
For ECL input pins, the equivalent force/sense circuitry is optional.
FIGURE 1. TTL-to-ECL AC Test Circuit
Switching Waveforms (T TL-to-ECL)
FIGURE 2. TTL to ECL Transition—Propagation Delay and Transition Times
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100397
Test Circuitry (ECL-to-TTL)
Notes:
R
t
= 50Ω termina tion. Wh en an inp ut o r outp ut is b ein g mo nito red by a s cope , Rt is supplied by the scope’s 50Ω resis tan ce. W h en an i np ut or outp ut is no t
being monitored , a nd external 50Ω resistance must be applied to serve as R
t
.
The TTL 3-STATE pull up switch is connected to +7V only for ZL and LZ tes ts. TTL and ECL force s ignals are brought to the DUT via 50Ω coax lines. V
TTL
is decoupled to ground with 0.1 µF to ground, VEE is decoupled to ground with 0.01 µF and GND is co nnected to ground.
FIGURE 3. ECL-to-TTL AC Test Circuit
Note:
DIR is LOW, and OE is HIGH
FIGURE 4. ECL-to-TTL Transition—Propagation Delay and Transition Times
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Test Circuitry (ECL-to-TTL) (Continued)
Note:
DIR is LOW, LE is HIGH
FIGURE 5. ECL-to-TTL Transition, OE to TTL Output,
Enable and Disable Times
Note:
OE is HIGH, LE is HIGH
FIGURE 6. ECL-to-TTL Transition, DIR to TTL Output,
Disable Time
Applications
FIGURE 7. Applications Diagram—MOS/TTL SRAM Interface Using 100397 ECL–TTL Latched Translator
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100397
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
Package Number N24E
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100397 Quad Differential ECL/TTL Translating Transceiver with Latch
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Package Number V28A
Fairchild does not assume any responsibility for use of any circuitry described , no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or syste ms
which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provide d in the labe l ing, can be re a­sonably expected to result in a significant injury to the user.
2. A critical component in any compo nent o f a li fe supp ort device or system whose failure to perform can be rea­sonably expected to cause the failure of the l ife support device or system, or to affect its safety or effectiveness.
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