Datasheet 100371SCX, 100371SC, 100371QIX, 100371QI, 100371QCX Datasheet (Fairchild Semiconductor)

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October 1989 Revised August 2000

100371 Low Power Tri p le 4-Input Multiplexer with Enable

100371 Low Power Triple 4-Input Multiplexer with Enable

General Description

The 100371 contains three 4-input multiplexers which share a common decoder (inputs S

and S1). Output buffer

gates provide true and complement outputs. A HIGH on the Enable input (E

) forces all true outputs L OW (see Truth

Table). All inputs have 50 k

Ω pull-down resistors.

Features

■ 35% power reduction of the 100171

■ 2000V ESD protection

■ Pin/function compatible with 100171

■ Voltage compensated operating range

= −4.2V to −5.7V

■ Available to industrial grade temperature range

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Logic Symbol

Pin Descriptions

Connection Diagrams

24-Pin DIP/SOIC

28-Pin PLCC

Order Number Package Number Package Description

100371SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 100371PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 10371QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 10371QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

Industrial Temperature Range (

−40°C to +85°C)

Pin Names Description

0x–I3x

Data Inputs

, S1Select Inputs E

Enable Input (Active LOW)

a–Zc

Data Outputs

a–Zc

Complementary Data Outputs

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100371

Truth Table

H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care

Logic Diagram

Inputs Outputs

LLLI

LHLI

LLHI

LHHI

HXXL

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100371

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: The “Absolute Maximum Ratings” are those value s beyond which

the safety of the dev ice cannot b e guaranteed . The device sh ould not be operated at these limit s. The parametric values defi ned in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recomm ended O peratin g Cond itions ” table will defin e the condition s for actual device operation.

Note 2: ESD testing conforms to MIL-STD-883, Method 3015.

Commercial Version DC Electrical Characteristics

(Note 3)

= −4.2V to −5.7V, VCC = V

CCA

= GND, T

= 0°C to +85°C

Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasin g the al l owable syste m opera ti ng ran ge s. Cond it i ons fo r t estin g sho w n in the tabl es are chosen to guarantee operation under “worst case” conditions.

DIP AC Electrical Characteristics

= −4.2V to −5.7V, VCC = V

CCA

= GND

Note 4: The propagation delay s pec ified is for single output swit c hing. Delays may vary up to 300 ps with multiple outpu ts s witching.

Storage Temperature (T

STG

) −65°C to +150°C

Maximum Junction Temperature (T

) +150°C

Pin Potential to Ground Pin −7.0V to +0.5V

Input Voltage (DC) V

to +0.5V

Output current (DC Output HIGH)

−50 mA

ESD (Note 2)

≥2000V

Case Temperature (T

)

Commercial 0

°C to +85°C

Industrial

−40°C to +85°C

Supply Voltage (V

) −5.7V to −4.2V

Symbol Parameter Min Typ Max Units Conditions

Output HIGH Voltage −1025 −955 −870 mV VIN =VIH (Max) Loading with

Output LOW Voltage −1830 −1705 −1620 mV or VIL (Min) 50Ω to −2.0V

OHC

Output HIGH Voltage −1035 mV VIN = VIH (Min) Loading with

OLC

Output LOW Voltage −1610 mV or VIL (Max) 50Ω to −2.0V

Input HIGH Voltage −1165 −870 mV Guaranteed HIGH Signal

for All Inputs

Input LOW Voltage −1830 −1475 mV Guaranteed LOW Signal

for All Inputs

Input LOW Current 0.50 µAVIN = VIL (Min)

Input HIGH Current

0X–I3X

340 µAVIN = VIH (Max)

S0, S1, E 300

Power Supply Current −75 −39 mA Inputs Open

Symbol Parameter

TC = 0°CT

= +25°CT

= +85°C

Units Conditions

Min Max Min Max Min Max

PLH

Propagation Delay

0.45 1.50 0.45 1.50 0.45 1.60 ns

PHL

I0x–I3x to Output

PLH

Propagation Delay

0.90 2.40 0.90 2.40 1.00 2.60 ns

Figures 1, 2

PHL

S0, S1 to Output (Note 4)

PLH

Propagation Delay

0.65 2.30 0.65 2.30 0.75 2.40 ns

PHL

E to Output

TLH

Transition Time

0.35 1.20 0.35 1.20 0.35 1.20 ns Figures 1, 2

THL

20% to 80%, 80% to 20%

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100371

Commercial Version (Continued) SOIC and PLCC AC Electrical Characteristics

= −4.2V to −5.7V, VCC = V

CCA

= GND

Note 5: The propagation dela y sp ec if ied is for single output swit c hing. Delays may vary up to 300 ps with multiple outpu ts s w it c hing. Note 6: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same pack-

aged device. Th e specif ications apply to any out puts s witchin g in the sa me dire ction e ither HI GH-to-LO W ( t

OSHL

), or LOW-to-HIGH ( t

OSLH

), or in opposite

directions both HL and LH (t

OST

). Parameters t

OST

and tPS guaranteed by design.

Symbol Parameter

TC = 0°CT

= +25°CT

= +85°C

Units Conditions

Min Max Min Max Min Max

PLH

Propagation Delay

0.45 1.30 0.45 1.30 0.45 1.40 ns

PHL

I0x–I3x to Output

PLH

Propagation Delay

0.90 2.20 0.90 2.20 1.00 2.40 ns

Figures 1, 2

PHL

S0, S1 to Output (Note 5)

PLH

Propagation Delay

0.65 2.10 0.65 2.10 0.75 2.20 ns

PHL

E to Output

TLH

Transition Time

0.35 1.10 0.35 1.10 0.35 1.10 ns Figures 1, 2

THL

20% to 80%, 80% to 20%

OSHL

Maximum Skew Common Edge PLCC only Output-to-Output Variation 400 400 400 ps (Note 6) Data to Output Path

OSLH

Maximum Skew Common Edge PLCC only Output-to-Output Variation 490 490 490 ps (Note 6) Data to Output Path

OST

Maximum Skew Opposite Edge PLCC only Output-to-Output Variation 490 490 490 ps (Note 6) Data to Output Path

Maximum Skew PLCC only Pin (Signal) Transition Variation 430 430 430 ps (Note 6) Data to Output Path

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100371

Industrial Version PLCC DC Electrical Characteristics

(Note 7)

= −4.2V to −5.7V, VCC = V

CCA

= GND, T

= −40°C to +85°C

Note 7: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasin g the al l owable syste m opera ti ng ran ge s. Cond it i ons fo r t estin g sho w n in the tabl es are chosen to guarantee operation under “worst case” conditions.

PLCC AC Electrical Characteristics

= −4.2V to −5.7V, VCC = V

CCA

= GND

Note 8: The propagation delay s pec ified is for single output swit c hing. Delays may vary up to 300 ps with multiple outpu ts s witching.

Symbol Parameter

= −40°CTC = 0°C to +85°C

Units Conditions

Min Max Min Max

Output HIGH Voltage −1085 −870 −1025 −870 mV VIN =VIH (Max) Loading with

Output LOW Voltage −1830 −1575 −1830 −1620 mV or VIL(Min) 50Ω to −2.0V

OHC

Output HIGH Voltage −1095 −1035 mV VIN = VIH (Min) Loading with

OLC

Output LOW Voltage −1565 −1610 mV or VIL(Max) 50Ω to −2.0V

Input HIGH Voltage −1170 −870 −1165 −870 mV Guaranteed HIGH Signal

for All Inputs

Input LOW Voltage −1830 −1480 −1830 −1475 mV Guaranteed LOW Signal

for All Inputs

Input LOW Current 0.50 0.50 µAVIN = VIL (Min)

Input HIGH Current

I0X–I

340 340 µAVIN = VIH (Max)

S0, S1, E 300 300

Power Supply Current −75 −35 −75 −39 mA Inputs Open

Symbol Parameter

= −40°CT

= +25°CT

= +85°C

Units Conditions

Min Max Min Max Min Max

PLH

Propagation Delay

0.40 1.30 0.45 1.30 0.45 1.40 ns

PHL

I0x–I3x to Output

PLH

Propagation Delay

0.70 2.20 0.90 2.20 1.00 2.40 ns

Figures 1, 2

PHL

S0, S1 to Output (Note 8)

PLH

Propagation Delay

0.65 2.10 0.65 2.10 0.75 2.20 ns

PHL

E to Output

TLH

Transition Time

0.20 1.60 0.35 1.10 0.35 1.10 ns Figures 1, 2

THL

20% to 80%, 80% to 20%

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100371

Test Circuitry

Notes:

, V

CCA

= +2V, VEE = −2.5V L1 and L2 = equal length 50Ω impedance lines R

= 50Ω terminator internal to scope

Decoupling 0.1 µF from GND to V

and V

All unused outputs are loaded with 50Ω to G ND C

= Fixture and stray capacitance ≤ 3 pF

FIGURE 1. AC Test Circuit

Switching Waveforms

FIGURE 2. Propagation Delay and Transition Times

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100371

Physical Dimensions inches (millimeters) unless otherwise noted

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

Package Number M24B

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide

Package Number N24E

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100371 Low Power Triple 4-Input Multiplexer with Enable

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

Package Number V28A

Fairchild does not assume any responsibility for use of any circuitr y described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or syste ms

which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the user.

2. A critical component in any compon ent of a lif e supp ort device or system whose failure t o perform can be reasonably expected to ca use the failure of the life supp ort device or system, or to affect its safety or effectiveness.

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