Datasheet 100354QIX, 100354QI, 100354QCX, 100354QC, 100354PC Datasheet (Fairchild Semiconductor)

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Page 1

October 1989 Revised August 2000

100354 Low Power 8-Bit Register with Cut-Off Drivers

General Description

The 100354 contains eight D -type edge trigg ered, master/ slave flip-flops with individual inputs (D

), true outputs (Qn),

a clock input (CP), an output enable pin (OEN

), and a com-

mon clock enable pin (CEN

). Data enters th e ma ster w h en CP is LOW and transfers to the slave when CP goes HIGH. When the CEN

input goes HIGH it overrides all other inputs, disables the clock, and the Q ou tputs maintain the last state.

A Q output follows its D input when the OEN

pin is LOW. A

HIGH on OEN

holds the outputs in a cut- off stat e. Th e cu toff state is designed to be more ne gative than a normal ECL LOW level. This allows the output emitter-followers to turn off when the termination supply is

−2.0V, presenting a

high impedance to the data bus. This high impedance

reduces termination p ower and prevent s loss of low state noise margin when several loads share the bus.

The 100354 outputs are design ed to drive a doubly terminated 50

Ω transmission line (25Ω load impedance). All

inputs have 50 k

Ω pull-down resistors.

Features

■ Cut-off drivers

■ Drives 25

Ω load

■ Low power operation

■ 2000V ESD protection

■ Voltage compensated operating range

= −4.2V to −5.7V

■ Available to industrial grade temperature range

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Logic Symbol

Pin Descriptions

Connection Diagrams

24-Pin DIP

28-Pin PLCC

Order Number Package Number Package Description

100354PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 100354QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 100354QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

Industrial Temperature Range (

−40°C to +85°C)

Pin Names Description

0–D7

Data Inputs

CEN

Clock Enabl e Input CP Clock Input (Active Rising Edge) OEN Output Enable Input Q

0–Q7

Data Outputs

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100354

Truth Table

H = HIGH Voltage Level L = LOW Voltage Level NC = No Change X = Don’t Care Cutoff = Lower-than-LOW State



= LOW-to-HIGH Transition

Logic Diagram

Inputs Outputs

CEN CP OEN



LH XXLLNC XXHLNC XHXLNC XXXHCutoff

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100354

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: The “Absolute Maximum Ratings” are those value s beyond which

the safety of the dev ice cannot b e guaranteed . The device sh ould not be operated at these limit s. The parametric values defi ned in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recomm ended O peratin g Cond itions ” table will defin e the condition s for actual device operation.

Note 2: ESD testing conforms to MIL-STD-883, Method 3015.

Commercial Version DC Electrical Characteristics

(Note 3)

= −4.2V to −5.7V, VCC = V

CCA

= GND, T

= 0°C to +85°C

Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasin g the al l owable syste m opera ti ng ran ge s. Cond it i ons fo r t estin g sho w n in the tabl es are chosen to guarantee operation under “worst case” conditions.

Storage Temperature (T

STG

) −65°C to +150°C

Maximum Junction Temperature (T

) +150°C

Pin Potential to Ground Pin −7.0V to +0.5V

Input Voltage (DC) V

to +0.5V

Output Current (DC Output HIGH)

−100 mA

ESD (Note 2)

≥2000V

Case Temperature (T

)

Commercial 0

°C to +85°C

Industrial

−40°C to +85°C

Supply Voltage (V

) −5.7V to −4.2V

Symbol Parameter Min Typ Max Units Conditions

Output HIGH Voltage −1025 −955 −870

VIN =V

IH (Max)

Loading with

Output LOW Voltage −1830 −1705 −1620 or V

IL (Min)

25Ω to −2.0V

OHC

Output HIGH Voltage −1035

VIN = V

IH (Min)

Loading with

OLC

Output LOW Voltage −1610 or V

IL (Max)

25Ω to −2.0V

OLZ

Cutoff LOW Voltage −1950 mV VIN = VIH (Min) OEN = HIGH

or V

(Max)

Input HIGH Voltage −1165 −870 mV Guaranteed HIGH Signal for All Inputs

Input LOW Voltage −1830 −1475 mV Guaranteed LOW Signal for All Inputs

Input LOW Current 0.50 µAVIN = V

IL (Min)

Input HIGH Current 240 µAVIN = V

IH (Max)

Power Supply Current Inputs Open

−202 −105 mA V

= −4.2V to −4.8V

−209 −105 V

= −4.2V to −5.7V

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Commercial Version (Continued) DIP AC Electrical Characteristics

= −4.2V to −5.7V, VCC = V

CCA

= GND

Note 4: The propagation dela y sp ec if ied is for single output swit c hing. Delays may vary up to 300 ps with multiple outpu ts s w it c hing.

PLCC AC Electrical Characteristics

= −4.2V to −5.7V, VCC = V

CCA

= GND

Note 5: The propagation dela y sp ec if ied is for single output swit c hing. Delays may vary up to 300 ps with multiple outpu ts s w it c hing. Note 6: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same pack-

aged device. Th e specif ications apply to any out puts s witchin g in the sa me dire ction e ither HI GH-to-LO W ( t

OSHL

), or LOW-to-HIGH ( t

OSLH

), or in opposite

directions both HL and LH (t

OST

). Parameters t

OST

and tPS guaranteed by design.

Symbol Parameter

TC = 0°CT

= +25°CT

= +85°C

Units Conditions

Min Max Min Max Min Max

MAX

Toggle Frequency 250 250 250 MHz Figures 1, 4

PLH

Propagation Delay

1.40 3.00 1.40 3.00 1.50 3.10 ns

Figures 1, 4

PHL

CP to Output (Note 4)

PZH

Propagation Delay 1.60 4.20 1.60 4.20 1.60 4.20

Figures 3, 7

PHZ

OEN to Output 1.00 2.70 1.00 2.70 1.00 2.70 (Note 4)

TLH

Transition Time

0.45 2.00 0.45 2.00 0.45 2.00 ns Figures 1, 4

THL

20% to 80%, 80% to 20%

Setup Time

1.10 1.10 1.10

CEN

(Disable Time) 0.40 0.40 0.40 ns Figures 2, 5

CEN (Release Time) 1.10 1.10 1.10

Hold Time

0.10 0.10 0.10 ns Figures 1, 6

tPW(H) Pulse Width HIGH

2.00 2.00 2.00 ns Figures 1, 4

Symbol Parameter

TC = 0°CT

= +25°CT

= +85°C

Units Conditions

Min Max Min Max Min Max

MAX

Toggle Frequency 250 250 250 MHz Figures 1, 4

PLH

Propagation Delay

1.40 2.80 1.40 2.80 1.50 2.90 ns

Figures 1, 4

PHL

CP to Output (Note 5)

PZH

Propagation Delay 1.60 4.00 1.60 4.00 1.60 4.00

Figures 3, 7

PHZ

OEN to Output 1.00 2.50 1.00 2.50 1.00 2.50 (Note 5)

TLH

Transition Time

0.45 1.90 0.45 1.90 0.45 1.90 ns Figures 1, 4

THL

20% to 80%, 80% to 20%

Setup Time

1.00 1.00 1.00 CEN (Disable Time) 0.30 0.30 0.30 ns Figures 2, 5 CEN

(Release Time) 1.00 1.00 1.00

Hold Time

0.00 0.00 0.00 ns Figures 1, 6

tPW(H) Pulse Width HIGH

2.00 2.00 2.00 ns Figures 1, 4

OSHL

Maximum Skew Common Edge Output-to-Output Variation 280 280 280 ps (Note 6) Clock to Output Path

OSLH

Maximum Skew Common Edge Output-to-Output Variation 340 340 340 ps (Note 6) Clock to Output Path

OST

Maximum Skew Opposite Edge Output-to-Output Variation 340 340 340 ps (Note 6) Clock to Output Path

Maximum Skew Pin (Signal) Transition Variation 250 250 250 ps (Note 6) Clock to Output Path

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Industrial Version PLCC DC Electrical Characteristics

(Note 7)

=−4.2V to −5.7V, VCC= V

CCA

= GND, T

=−40°C to +85°C

Note 7: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasin g the al l owable syste m opera ti ng ran ge s. Cond it i ons fo r t estin g sho w n in the tabl es are chosen to guarantee operation under “worst case” conditions.

PLCC AC Electrical Characteristics

= −4.2V to −5.7V, VCC = V

CCA

= GND

Note 8: The propagation delay s pec ified is for single output swit c hing. Delays may vary up to 300 ps with multiple outpu ts s witching.

Symbol Parameter

TC = −40°CTC = 0° to +85°C

Units Conditions

Min Max Min Max

Output HIGH Voltage −1085 −870 −1025 −870

VIN =VIH (Max) Loading with

Output LOW Voltage −1830 −1575 −1830 −1620 or VIL (Min) 50Ω to −2.0V

OHC

Output HIGH Voltage −1095 −1035

VIN = VIH (Min) Loading with

OLC

Output LOW Voltage −1565 −1610 or VIL (Max) 50Ω to −2.0V

OLZ

Cutoff LOW Voltage −1900 −1950 mV VIN = VIH (Min) OEN = HIGH

or V

(Max)

Input HIGH Voltage −1170 −870 −1165 −870 mV Guaranteed HIGH Signal

for All Inputs

Input LOW Voltage −1830 −1480 −1830 −1475 mV Guaranteed LOW Signal

for All Inputs

Input LOW Current 0.50 0.50 µAVIN = VIL (Min)

Input HIGH Current 240 240 µAVIN = VIH (Max)

Power Supply Current Inputs Open

−202 −105 −202 −105 mA VEE = −4.2V to −4.8V

−209 −105 −209 −105 VEE = −4.2V to −5.7V

Symbol Parameter

TC = −40°CT

= +25°CT

= +85°C

Units Conditions

Min Max Min Max Min Max

MAX

Toggle Frequency 250 250 250 MHz Figures 1, 4

PLH

Propagation Delay

1.40 2.80 1.40 2.80 1.50 2.90 ns

Figures 1, 4

PHL

CP to Output (Note 8)

PZH

Propagation Delay 1.50 4.10 1.60 4.00 1.60 4.00

Figures 3, 5

PHZ

OEN to Output 1.00 2.50 1.00 2.50 1.00 2.50 (Note 8)

TLH

Transition Time

0.45 1.90 0.45 1.90 0.45 1.90 ns Figures 1, 4

THL

20% to 80%, 80% to 20%

Setup Time

1.00 1.00 1.00

CEN

(Disable Time) 0.30 0.30 0.30 ns Figures 2, 5

CEN (Release Time) 1.00 1.00 1.00

Hold Time

0.00 0.00 0.00 ns Figures 1, 6

tPW(H) Pulse Width High

2.00 2.00 2.00 ns Figures 1, 4

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Test Circuitry

FIGURE 1. Toggle Frequency Test Circuit

FIGURE 2. AC Test Circuit

FIGURE 3. AC Test Circuit

Notes:

, V

CCA

= +2V, VEE = −2.5V L1 and L2 = equal length 50Ω impedance lines R

= 50Ω terminator internal to scope

Decoupling 0.1 µF from GND to V

and V

All unused outputs are loaded with 25Ω to G ND C

= Fixture and stray capacitance ≤ 3 pF

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Switching Waveforms

FIGURE 4. Propagation Delay (Clock) and Transition Times

FIGURE 5. Setup and Pulse Width Times

Notes:

is the minimum time bef ore the transition of the c loc k th at inf ormation must be pres ent at t he data input.

is the minimum time after the transition of the cl oc k th at inf ormation must remain unc hanged at the data input .

FIGURE 6. Data Setup and Hold Time

Note:

The output AC measu rement point for cut-off prop agation delay testing = the 50% voltage point between active V

and VOH.

FIGURE 7. Cutoff Times

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Physical Dimensions inches (millimeters) unless otherwise noted

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide

Package Number N24E

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100354 Low Power 8-Bit Register with Cut-Off Drivers

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

Package Number V28A

Fairchild does not assume any responsibility for use of any circuitry described , no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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