Datasheet 100352QIX, 100352QI, 100352QCX, 100352QC, 100352PC Datasheet (Fairchild Semiconductor)

© 2000 Fairchild Semiconductor Corporation DS010248 www.fairchildsemi.com

October 1989
Revised August 2000

100352 Low Power 8-Bit Buffer with Cut-Off Drivers

100352
Low Power 8-Bit Buffer with Cut-Off Drivers

General Description

The 100352 contains an 8-b it bu ffer, individual inputs ( Dn),
outputs (Q

n

), and a data output enable pin (OEN). A Q out-

put follows its D input when the OEN

pin is LOW. A HIGH

on OEN

holds the outputs in a cut-off state. The cut-off
state is designed to be m ore negative than a n ormal ECL
LOW level. This allows the output emitter-followers to turn
off when the termin atio n s upp l y is

−2.0V, presenting a high

impedance to the data bus . This high impedan ce reduces
termination power and prevents loss of low state noise
margin when several loads share the bus.

The 100352 outpu ts are designe d to drive a doubly term i­nated 50

Ω transmission line (25Ω load impedance). All

inputs have 50 k

Ω pull-down resistors.

Features

■ Cut-off drivers

■ Drives 25

Ω load

■ Low power operation

■ 2000V ESD protection

■ Voltage compensated operating range

= −4.2V to −5.7V

■ Available to industrial grade temperature range

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Logic Symbol

Pin Descriptions

Connection Diagrams

24-Pin DIP

28-Pin PLCC

Order Number Package Number Package Description

100352PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100352QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100352QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

Industrial Temperature Range (

−40°C to +85°C)

Pin Names Description

D

0–D7

Data Inputs

OEN

Output Enable Input

Q

0–Q7

Data Outputs

NC No Connect

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100352

Truth Table

H = HIGH Voltage Level
L = LOW Voltage Level
Cutoff = Lower-than-LOW State
X = Don’t Care

Logic Diagram

Inputs Outputs

D

n

OEN Q

n

LL L
HL H
XHCutoff

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100352

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: The “Absolute Maximum Ratings” are those value s beyond which

the safety of the dev ice cannot b e guaranteed . The device sh ould not be
operated at these limit s. The parametric values defi ned in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recomm ended O peratin g Cond itions ” table will defin e the condition s
for actual device operation.

Note 2: ESD testing conforms to MIL-STD-883, Method 3015.

Commercial Version
DC Electrical Characteristics

(Note 3)

V

EE

= −4.2V to −5.7V, VCC = V

CCA

= GND, T

C

= 0°C to +85°C

Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasin g the al l owable syste m opera ti ng ran ge s. Cond it i ons fo r t estin g sho w n in the tabl es are cho­sen to guarantee operation under “worst case” conditions.

DIP AC Electrical Characteristics

V

EE

= −4.2V to −5.7V, VCC = V

CCA

= GND

Note 4: The propagation delay s pec ified is for single output swit c hing. Delays may vary up to 300 ps with multiple outpu ts s witching.

Storage Temperature (T

STG

) −65°C to +150°C

Maximum Junction Temperature (T

J

) +150°C

V

EE

Pin Potential to Ground Pin −7.0V to +0.5V

Input Voltage (DC) V

EE

to +0.5V

Output Current (DC Output HIGH)

−100 mA

ESD (Note 2)

≥2000V

Case Temperature (T

C

)

Commercial 0

°C to +85°C

Industrial

−40°C to +85°C

Supply Voltage (V

EE

) −5.7V to −4.2V

Symbol Parameter Min Typ Max Units Conditions

V

OH

Output HIGH Voltage −1025 −955 −870

mV

VIN =V

IH (Max)

Loading with

V

OL

Output LOW Voltage −1830 −1705 −1620 or V

IL (Min)

25Ω to −2.0V

V

OHC

Output HIGH Voltage −1035

mV

VIN = V

IH (Min)

Loading with

V

OLC

Output LOW Voltage −1610 or V

IL (Max)

25Ω to −2.0V

V

OLZ

Cut-Off LOW Voltage −1950 mV VIN = V

IH (Min)

OEN = HIGH

or V

IL (Max)

V

IH

Input HIGH Voltage −1165 −870 mV Guaranteed HIGH Signal

for All Inputs

V

IL

Input LOW Voltage −1830 −1475 mV Guaranteed LOW Signal

for All Inputs

I

IL

Input LOW Current 0.50 µAVIN = V

IL (Min)

I

IH

Input HIGH Current 240 µAVIN = V

IH (Max)

I

EE

Power Supply Current Inputs Open

−138 −70 mA VEE = −4.2V to −4.8V

−143 −70 V

EE

= −4.2V to −5.7V

Symbol Parameter

T

C

= 0°CT

C

= +25°CT

C

= +85°C

Units Conditions

Min Max Min Max Min Max

t

PLH

Propagation Delay

0.70 2.00 0.70 2.00 0.70 2.20 ns

Figures 1, 2

t

PHL

Dn to Output (Note 4)

t

PZH

Propagation Delay 1.60 4.20 1.60 4.20 1.60 4.20

ns

Figures 1, 2

t

PHZ

OEN to Output 1.00 2.70 1.00 2.70 1.00 2.70 (Note 4)

t

TLH

Transition Time

0.45 2.00 0.45 2.00 0.45 2.00 ns Figures 1, 2

t

THL

20% to 80%, 80% to 20%

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100352

Commercial Version (Continued)
PLCC AC Electrical Characteristics

V

EE

= 4.2V to −5.7V, VCC = V

CCA

= GND

Note 5: The propagation dela y sp ec if ied is for single output swit c hing. Delays may vary up to 300 ps with multiple outpu ts s w it c hing.
Note 6: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same pack-

aged device. Th e specif ications apply to any out puts s witchin g in the sa me dire ction e ither HI GH-to-LO W ( t

OSHL

), or LOW-to-HIGH ( t

OSLH

), or in opposite

directions both HL and LH (t

OST

). Parameters t

OST

and tPS guaranteed by design.

Symbol Parameter

TC = 0°CT

C

= +25°CT

C

= +85°C

Units Conditions

Min Max Min Max Min Max

t

PLH

Propagation Delay

0.70 1.80 0.70 1.80 0.70 2.00 ns

Figures 1, 2

t

PHL

Dn to Output (Note 5)

t

PZH

Propagation Delay 1.60 4.00 1.60 4.00 1.60 4.00

ns

Figures 1, 2

t

PHZ

OEN to Output 1.00 2.50 1.00 2.50 1.00 2.50 (Note 5)

t

TLH

Transition Time

0.45 1.90 0.45 1.90 0.45 1.90 ns Figures 1, 2

t

THL

20% to 80%, 80% to 20%

t

OSHL

Maximum Skew Common Edge PLCC only
Output-to-Output Variation 230 230 230 ps (Note 6)
Data to Output Path

t

OSLH

Maximum Skew Common Edge PLCC only
Output-to-Output Variation 240 240 240 ps (Note 6)
Data to Output Path

t

OST

Maximum Skew Opposite Edge PLCC only
Output-to-Output Variation 350 350 350 ps (Note 6)
Data to Output Path

t

PS

Maximum Skew PLCC only
Pin (Signal) Transition Variation 350 350 350 ps (Note 6)
Data to Output Path

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100352

Industrial Version
PLCC DC Electrical Characteristics

(Note 7)

V

EE

= −4.2V to −5.7V, VCC = V

CCA

= GND, T

C

= −40°C to +85°C

Note 7: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasin g the al l owable syste m opera ti ng ran ge s. Cond it i ons fo r t estin g sho w n in the tabl es are cho­sen to guarantee operation under “worst case” conditions.

PLCC AC Electrical Characteristics

V

EE

= 4.2V to −5.7V, VCC = V

CCA

= GND

Note 8: The propagation delay s pec ified is for single output swit c hing. Delays may vary up to 300 ps with multiple outpu ts s witching.

Symbol Parameter

TC = −40°CTC = 0°C to +85°C

Units Conditions

Min Max Min Max

V

OH

Output HIGH Voltage −1085 −870 −1025 −870

mV

VIN = V

IH(Max)

Loading with

V

OL

Output LOW Voltage −1830 −1575 −1830 −1620 or V

IL(Min)

25Ω to −2.0V

V

OHC

Output HIGH Voltage −1095 −1035

mV

VIN = V

IH(Min)

Loading with

V

OLC

Output LOW Voltage −1565 −1610 or V

IL(Max)

25Ω to −2.0V

V

OLZ

Cut-Off LOW Voltage −1950 −1950 mV VIN = V

IH(Min)

OEN = HIGH

or V

IL

(Max)

V

IH

Input HIGH Voltage −1170 −870 −1165 −870 mV Guaranteed HIGH Signal

for All Inputs

V

IL

Input LOW Voltage −1830 −1480 −1830 −1475 mV Guaranteed LOW Signal

for All Inputs

I

IL

Input LOW Current 0.50 0.50 µA VIN = V

IL(Min)

I

IH

Input HIGH Current 340 240 µAVIN = V

IH(Max)

I

EE

Power Supply Current Inputs OPEN

−138 −60 −138 −70 mA VEE = −4.2V to −4.8V

−143 −60 −143 −70 VEE = −4.2V to −5.7V

Symbol Parameter

TC = −40°CT

C

= +25°CT

C

= +85°C

Units Conditions

Min Max Min Max Min Max

t

PLH

Propagation Delay

0.60 1.80 0.70 1.80 0.70 2.00 ns

Figures 1, 2

t

PHL

Dn to Output (Note 8)

t

PZH

Propagation Delay 1.40 4.40 1.60 4.00 1.60 4.00

ns

Figures 1, 2

t

PHZ

OEN to Output 1.00 2.5 0 1.00 2.50 1.00 2.50 (Not e 8)

t

TLH

Transition Time

0.40 2.50 0.45 1.90 0.45 1.90 ns Figures 1, 2

t

THL

20% to 80%, 80% to 20%

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100352

Test Circuitry

Notes:

V

CC

, V

CCA

= +2V, VEE = −2.5V

L1 and L2 = equal length 50Ω impedance lines
R

T

= 50Ω terminator internal to scope

Decoupling 0.1 µF from GND to V

CC

and V

EE

All unused outputs are loaded with 25Ω to G ND
C

L

= Fixture and stray capacitance ≤ 3 pF

FIGURE 1. AC Test Circuit

Switching Waveforms

Note:

The output AC meas urement point for cut-o ff propagation delay
testing = the 50% voltage point between active V

OL

and VOH.

FIGURE 2. Propagation Delay, Cut-Off and Transition Times

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100352

Physical Dimensions inches (millimeters) unless otherwise noted

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide

Package Number N24E

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100352 Low Power 8-Bit Buffer with Cut-Off Drivers

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

Package Number V28A

Fairchild does not assume any responsibility for use of any circuitr y described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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