Datasheet 100351SCX, 100351SC, 100351QIX, 100351QI, 100351QCX Datasheet (Fairchild Semiconductor)

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July 1988 Revised August 2000

100351 Low Power Hex D-Type Flip-Flop

General Description

The 100351 contains six D-type edge-triggered, master/ slave flip-flops with true and compl emen t outputs , a pair of common Clock inputs (CP

and CPb) and common Master

Reset (MR) input. Data enters a master when both CP

and CPb are LOW and transfers to the slave when CPa and CP

(or both) go HIGH. The MR input override s all other

inputs and makes the Q outputs LOW. All inputs have 50 k

Ω pull-down resistors.

Features

■ 40% power reduction of the 100151

■ 2000V ESD protection

■ Pin/function compatible with 100151

■ Voltage compensated operating range:

−4.2V to −5.7V

■ Available to industrial grade temperature range

Ordering Code:

Devises also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Logic Symbol

Pin Descriptions

Connection Diagrams

24-Pin DIP/SOIC

28-Pin PLCC

Order Number Package Number Package Description

100351SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 100351PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 100351QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 100351QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

Industrial Temperature Range (

−40°C to +85°C)

Pin Names Description

0–D5

Data Inputs

, CP

Common Clock Inputs MR Asynchronous Master Reset Input Q

0–Q5

Data Outputs Q

0–Q5

Complementary Data Outputs

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100351

Truth Tables

(Each Flip-flop)

Synchronous Operation

H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care

t = Time before CP positive transition

t+1 = Time after CP positive transiti on



= LOW-to-HIGH transition

Asynchronous Operati on

Logic Diagram

Inputs Outputs

MR Qn(t+1)



LL L



LL H



(t)



HL Q

(t)

XL LL Q

(t)

Inputs Outputs

MR Qn(t+1)

XXXH L

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100351

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: The “Absolute Maximum Ratings” are those value s beyond which

the safety of the dev ice cannot b e guaranteed . The device sh ould not be operated at these limit s. The parametric values defi ned in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recomm ended O peratin g Cond itions ” table will defin e the condition s for actual device operation.

Note 2: ESD testing conforms to MIL-STD-883, Method 3015.

Commercial Version DC Electrical Characteristics

(Note 3)

= −4.2V to −5.7V, VCC = V

CCA

= GND, T

= 0°C to +85°C

Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasin g the al l owable syste m opera ti ng ran ge s. Cond it i ons fo r t estin g sho w n in the tabl es are chosen to guarantee operation under “worst case” conditions.

DIP AC Electrical Characteristics

= −4.2V to −5.7V, VCC = V

CCA

= GND

Storage Temperature (T

STG

) −65°C to +150°C

Maximum Junction Temperature (T

) +150°C

Pin Potential to Ground Pin −7.0V to +0.5V

Input Voltage (DC) V

to +0.5V

Output Current (DC Output HIGH)

−50 mA

ESD (Note 2)

≥2000V

Case Temperature (T

)

Commercial 0

°C to +85°C

Industrial

−40°C to +85°C

Supply Voltage (V

) −5.7V to −4.2V

Symbol Parameter Min Typ Max Units Conditions

Output HIGH Voltage −1025 −955 −870

VIN =VIH (Max) Loading with

Output LOW Voltage −1830 −1705 −1620 or VIL (Min) 50Ω to −2.0V

OHC

Output HIGH Voltage −1035

VIN = VIH (Min) Loading with

OLC

Output LOW Voltage −1610 or VIL (Max) 50Ω to −2.0V

Input HIGH Voltage −1165 −870 mV Guaranteed HIGH Signal for All Inputs

Input LOW Voltage −1830 −1475 mV Guaranteed LOW Signal for All Inputs

Input LOW Current 0.50 µAVIN = VIL (Min)

Input HIGH Current

MR 350

0–D5

240 µAVIN = VIH (Max)

, CP

350

Power Supply Current −129 −62 mA Inputs OPEN

Symbol Parameter

TC = 0°CT

= +25°CT

= +85°C

Units Conditions

Min Max Min Max Min Max

MAX

Toggle Frequency 375 375 375 MHz Figures 2, 3

PLH

Propagation Delay

0.80 2.00 0.80 2.0 0.90 2.10 ns Figures 1, 3

PHL

CPa, CPb to Output

PLH

Propagation Delay

1.10 2.30 1.10 2.30 1.20 2.40 ns Figures 1, 4

PHL

MR to Output

TLH

Transition Time

0.35 1.20 0.35 1.20 0.35 1.20 ns Figures 1, 3

THL

20% to 80%, 80% to 20%

Setup Time D0–D

0.40 0.40 0.40 ns Figure 5

MR (Release Time) 1.60 1.60 1.60 Figure 4

Hold Time

0.80 0.80 0.80 ns Figure 5

D0–D

tPW(H) Pulse Width HIGH

2.00 2.00 2.00 ns Figures 3, 4

CPa, CPb, MR

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Commercial Version (Continued) SOIC and PLCC AC Electrical Characteristics

= −4.2V to −5.7V, VCC = V

CCA

= GND

Note 4: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. Th e specif ications apply to any out puts s witchin g in the sa me dire ction e ither HI GH-to-LO W ( t

OSHL

), or LOW-to-HIGH ( t

OSLH

), or in opposite

directions both HL and LH (t

OST

). Parameters t

OST

and tPS guaranteed by design.

Symbol Parameter

TC = 0°CT

= +25°CT

= +85°C

Units Conditions

Min Max Min Max Min Max

MAX

Toggle Frequency 375 375 375 MHz Figures 2, 3

PLH

Propagation Delay

0.80 1.80 0.80 1.80 0.90 1.90 ns Figures 1, 3

PHL

CPa, CPb to Output

PLH

Propagation Delay

1.10 2.10 1.10 2.10 1.20 2.20 ns Figures 1, 4

PHL

MR to Output

TLH

Transition Time

0.45 1.70 0.45 1.60 0.45 1.70 ns Figures 1, 3

THL

20% to 80%, 80% to 20%

Setup Time D

0–D5

0.30 0.30 0.30 ns Figure 5

MR (Release Time) 1.50 1.50 1.50 Figure 4

Hold Time

0.80 0.80 0.80 ns Figure 5

0–D5

tPW(H) Pulse Width HIGH

2.00 2.00 2.00 ns Figures 3, 4

CPa, CPb, MR

OSHL

Maximum Skew Common Edge PLCC only Output-to-Output Variation 220 220 220 ps (Note 4) Clock to Output Path

OSLH

Maximum Skew Common Edge PLCC only Output-to-Output Variation 210 210 210 ps (Note 4) Clock to Output Path

OST

Maximum Skew Opposite Edge PLCC only Output-to-Output Variation 240 240 240 ps (Note 4) Clock to Output Path

Maximum Skew PLCC only Pin (Signal) Transition Variation 230 230 230 ps (Note 4) Clock to Output Path

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100351

Industrial Version PLCC DC Electrical Characteristics

=−4.2V to −5.7V, VCC=V

CCA

= GND, TC= 0°C to +85°C (Note 5)

Note 5: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasin g the al l owable syste m opera ti ng ran ge s. Cond it i ons fo r t estin g sho w n in the tabl es are chosen to guarantee operation under “worst case” conditions.

PLCC AC Electrical Characteristics

= −4.2V to −5.7V, VCC = V

CCA

= GND

Symbol Parameter

TC = −40°CTC = 0° to +85°C

Units Conditions

Min Max Min Max

Output HIGH Voltage −1085 −870 −1025 −870

VIN =VIH (Max) Loading with

Output LOW Voltage −1830 −1575 −1830 −1620 or VIL (Min) 50Ω to −2.0V

OHC

Output HIGH Voltage −1095 −1035

VIN = VIH (Min) Loading with

OLC

Output LOW Voltage −1565 −1610 or VIL (Max) 50Ω to −2.0V

Input HIGH Voltage −1170 −870 −1165 −870 mV Guaranteed HIGH Signal

for All Inputs

Input LOW Voltage −1830 −1480 −1830 −1475 mV Guaranteed LOW Signal

for All Inputs

Input LOW Current 0.50 0.50 µAVIN = VIL (Min)

Input HIGH Current

MR 350 350

D0–D

240 240 µAVIN = VIH (Max)

CPa, CP

350 350

Power Supply Current −129 −62 −129 −62 mA Inputs OPEN

Symbol Parameter

= −40°CT

= +25°CT

= +85°C

Units Conditions

Min Max Min Max Min Max

MAX

Toggle Frequency 375 375 375 MHz Figures 2, 3

PLH

Propagation Delay

0.80 1.80 0.80 1.80 0.90 1.90 ns Figures 1, 3

PHL

CPa, CPb to Output

PLH

Propagation Delay

1.10 2.10 1.10 2.10 1.20 2.20 ns Figures 1, 4

PHL

MR to Output

TLH

Transition Time

0.45 1.70 0.45 1.60 0.45 1.70 ns Figures 1, 3

THL

20% to 80%, 80% to 20%

Setup Time D

0–D5

0.60 0.30 0.30 ns Figure 5

MR (Release Time) 2.20 1.50 1.50 Figure 4

Hold Time

0.60 0.90 0.90 ns Figure 5

D0–D

tPW(H) Pulse Width HIGH

2.00 2.00 2.00 ns Figures 3, 4

CPa, CPb, MR

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Test Circuitry

Notes:

, V

CCA

= +2V, VEE = −2.5V

L1 and L2 = equal length 50Ω impedance lines R

= 50Ω terminator internal to scope

Decoupling 0.1 µF from GND to V

and V

All unused outputs are loaded with 50Ω to G ND C

= Fixture and stray capacitance ≤ 3 pF

FIGURE 1. AC Test Circuit

Notes:

, V

CCA

= +2V, VEE = −2.5V L1 and L2 = equal length 50Ω impedance lines R

= 50Ω terminator internal to scope

Decoupling 0.1 µF from GND to V

and V

All unused outputs are loaded with 50Ω to G ND C

= Jig and stray capacitance ≤ 3 pF

FIGURE 2. Toggle Frequency Test Circuit

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Switching Waveforms

FIGURE 3. Propagation Delay (Clock) and Transition Times

FIGURE 4. Propagation Delay (Reset)

Notes:

is the minimum time bef ore the transition of the c loc k th at inf ormation must be pres ent at t he data input.

is the minimum time after the transition of the cl oc k th at inf ormation must remain unc hanged at the data input .

FIGURE 5. Setup a nd Hold Time

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Physical Dimensions inches (millimeters) unless otherwise noted

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

Package Number M24B

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide

Package Number N24E

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100351 Low Power Hex D-Type Flip-Flop

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

Package Number V28A

Fairchild does not assume any responsibility for use of any circuitry described , no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are dev ic es or syste ms which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provide d in the labe l ing, can be re asonably expected to result in a significant injury to the user.

2. A critical compo nent in any com ponen t of a life s upp ort device or system whose failure to perform can be reasonably expected to cause the failure of the l ife support device or system, or to affect its safety or effectiveness.

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