Datasheet 100350QI, 100350QCX, 100350QC, 100350PC, 100350DC Datasheet (Fairchild Semiconductor)

© 2000 Fairchild Semiconductor Corporation DS009884 www.fairchildsemi.com

July 1988
Revised August 2000

100350 Low Power Hex D-Type Latch

100350
Low Power Hex D-Type Latch

General Description

The 100350 contains six D-type latches with true and com­plement outputs, a pa ir of common Enables (E

a

and Eb),

and a common Master Reset (MR). A Q output follows its D
input when both E

a

and Eb are LOW. When either Ea or E

b

(or both) are HIGH, a latch stores the last valid data
present on its D i npu t b efo re E

a

or Eb went HIGH. The MR

input overrides all o ther inputs and makes the Q outputs
LOW. All inputs have 50 k

Ω pull-down resistors.

Features

■ 20% power reduction of the 100150

■ 2000V ESD protection

■ Pin/function compatible with 100150

■ Voltage compensated operating range

= −4.2V to −5.7V

Ordering Code:

Devises also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Logic Symbol

Pin Descriptions

Connection Diagrams

24-Pin DIP

28-Pin PLCC

Order Number Package Number Package Description

100350PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100350QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

Pin Names Description

D

0–D5

Data Inputs

E

a

, E

b

Common Enable Inputs (Active LOW)
MR Asynchronous Master Reset Input
Q

0–Q5

Data Outputs
Q

0–Q5

Complementary Data Output s

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100350

Truth Tables

(Each Latch)

Latch Operation

H = HIGH Voltage Level
L = LOW Voltage Level

X = Don’t Care
Note 1: Retains data present before E

positive transition

Asynchronous Operati on

Logic Diagram

Inputs Outputs

D

n

E

a

E

b

MR Q

n

LLLL L
HLLL H
X H X L Latched (Note 1)
X X H L Latched (Note 1)

Inputs Outputs

D

n

E

a

E

b

MR Q

n

XXXH L

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100350

Absolute Maximum Ratings(Note 2)

Above which the useful life may be impaired.

Recommended Operating
Conditions

Note 2: The “Absolute Maximum Ratings” are those value s beyond which

the safety of the dev ice cannot b e guaranteed . The device sh ould not be
operated at these limit s. The parametric values defi ned in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recomm ended O peratin g Cond itions ” table will defin e the condition s
for actual device operation.

Note 3: ESD testing conforms to MIL-STD-883, Method 3015.

DC Electrical Characteristics (Note 4)

V

EE

= −4.5V to −5.7V, VCC = V

CCA

= GND, T

C

= 0°C to +85°C

Note 4: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guard banding ca n be a chie ve d by decr easi ng the allowable system operating ranges. Conditions for testing shown in the tables are cho­sen to guarantee operation under “worst case” conditions.

DIP AC Electrical Characteristics

V

EE

= −4.2V to −5.7V, VCC = V

CCA

= GND

Storage Temperature (T

STG

) −65°C to +150°C

Maximum Junction Temperature (T

J

) +150°C

V

EE

Pin Potential to Ground Pin −7.0V to +0.5V

Input Voltage (DC) V

EE

to +0.5V

Output Current (DC Output HIGH)

−50 mA

ESD (Note 3)

≥2000V

Case Temperature (T

C

)0°C to +85°C

Supply Voltage (V

EE

) −5.7V to −4.2V

Symbol Parameter Min Typ Max Units Conditions

V

OH

Output HIGH Voltage −1025 −955 −870

mV

VIN =V

IH (Max)

Loading with

V

OL

Output LOW Voltage −1830 −1705 −1620 or V

IL (Min)

50Ω to −2.0V

V

OHC

Output HIGH Voltage −1035

mV

VIN = V

IH (Min)

Loading with

V

OLC

Output LOW Voltage −1610 or V

IL (Max)

50Ω to −2.0V

V

IH

Input HIGH Voltage −1165 −870 mV Guaranteed HIGH Signal for All Inputs

V

IL

Input LOW Voltage −1830 −1475 mV Guaranteed LOW Signal for All Inputs

I

IL

Input LOW Current 0.50 µAVIN = V

IL (Min)

I

IH

Input HIGH Current MR 240

D

n

240 µAVIN = V

IH (Max)

Ea, E

b

240

I

EE

Power Supply Inputs Open
Current −89 −44 mA VEE = −4.2V to −4.8V

−93 −44 V

EE

= −4.2V to −5.7V

Symbol Parameter

TC = 0°CT

C

= +25°CT

C

= +85°C

Units Conditions

Min Max Min Max Min Max

t

PLH

Propagation Delay

Figures 1, 2

t

PHL

Dn to Output 0.50 1.40 0.50 1.40 0.50 1.50 ns
(Transparent Mode)

t

PLH

Propagation Delay

0.75 1.85 0.75 1.85 0.75 2.05 ns

t

PHL

Ea, Eb to Output

t

PLH

Propagation Delay

0.90 2.10 0.90 2.10 0.90 2.10 ns Figures 1, 3

t

PHL

MR to Output

t

TLH

Transition Time

0.35 1.30 0.35 1.30 0.35 1.30 ns Figures 1, 2

t

THL

20% to 80%, 80% to 20%

t

S

Setup Time

Figures 3, 4D0–D

5

1.00 1.00 1.00 ns

MR (Release Time) 1.60 1.60 1.60

t

H

Hold Time, D0–D

5

0.40 0.40 0.40 ns Figure 4

tPW(L) Pulse Width LOW

2.00 2.00 2.00 ns Figure 2

Ea, E

b

tPW(H) Pulse Width HIGH, MR 2.00 2.00 2.00 ns Figure 3

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100350

PLCC AC Electrical Characteristics

V

EE

= −4.2V to −5.7V, VCC = V

CCA

= GND

Test Circuit

Note:

• V

CC

, V

CCA

= +2V, VEE = −2.5V

• L1 and L2 = equal length 50Ω impedance lines

• R

T

= 50Ω terminator internal to scope

• Decoupling 0.1 µF from GND to V

CC

and V

EE

• All unused outputs are loaded with 50Ω to GND

• C

L

= Fixture and stray capacitance ≤ 3 pF

FIGURE 1. AC Test Circuit

Symbol Parameter

T

C

= 0°CT

C

= +25°CT

C

= +85°C

Units Conditions

Min Max Min Max Min Max

t

PLH

Propagation Delay

Figures 1, 2

t

PHL

Dn to Output 0.50 1.20 0.50 1.20 0.50 1.30 ns
(Transparent Mode)

t

PLH

Propagation Delay

0.75 1.65 0.75 1.65 0.75 1.85 ns

t

PHL

Ea, Eb to Output

t

PLH

Propagation Delay

0.90 1.90 0.90 1.90 0.90 1.90 ns Figures 1, 3

t

PHL

MR to Output

t

TLH

Transition Time

0.35 1.10 0.35 1.10 0.35 1.10 ns Figures 1, 2

t

THL

20% to 80%, 80% to 20%

t

S

Setup Time

Figures 3, 4D

0–D5

0.90 0.90 0.90 ns

MR (Release Time) 1.50 1.50 1.50

t

H

Hold Time, D0–D

5

0.30 0.30 0.30 ns Figure 4

tPW(L) Pulse Width LOW

2.00 2.00 2.00 ns Figure 2

Ea, E

b

tPW(H) Pulse Width HIGH, MR 2.00 2.00 2.00 ns Figure 3

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100350

Switching Waveforms

FIGURE 2. Enable Timing

FIGURE 3. Reset Timing

Notes:

t

S

is the minimum time before the transition of the enable that information must be present at the data input.

t

H

is the minimum time after the transition of the ena ble that information mu st remain unchanged at th e data input.

FIGURE 4. Data Setup and Hold Time

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100350

Physical Dimensions inches (millimeters) unless otherwise noted

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide

Package Number N24E

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100350 Low Power Hex D-Type Latch

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

Package Number V28A

Fairchild does not assume any responsibility for use of any circuitry described , no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are dev ic es or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provide d in the labe l ing, can be re a­sonably expected to result in a significant injury to the
user.

2. A critical compo nent in any com ponen t of a life s upp ort
device or system whose failure to perform can be rea­sonably expected to cause the failure of the l ife support
device or system, or to affect its safety or effectiveness.

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