Datasheet 100344QIX, 100344QI, 100344QCX, 100344QC, 100344PC Datasheet (Fairchild Semiconductor)

© 2000 Fairchild Semiconductor Corporation DS009883 www.fairchildsemi.com

July 1988
Revised August 2000

100344 Low Power 8-Bit Latch with Cut-Off Drivers

100344
Low Power 8-Bit Latch with Cut-Off Drivers

General Description

The 100344 contains eight D-type latches, individual inputs
(D

n

), outputs (Qn), a common enable pin (E ), latch enable

(LE

), and output enable pin (OEN). A Q output follows its D

input when both E

and LE are LOW. When either E or LE
(or both) are HIGH, a latch stores the last valid data
present on its D input prior to E

or LE going HIGH.

A HIGH on OE N

holds the outputs in a cut-off state. The
cut-off state is designed to be more negative than a normal
ECL LOW level. This allows the output emitter-followers to
turn off when the termination supply is

−2.0V, presenting a

high impedance to the data bus. This high impedance
reduces termination pow er and prevents loss of l ow state
noise margin when several loads share the bus.

The 100344 outpu ts are designe d to drive a doubly term i­nated 50

Ω transmission line (25Ω load impedance). All

inputs have 50 k

Ω pull-down resistors.

Features

■ Cut-off drivers

■ Drives 25

Ω load

■ Low power operation

■ 2000V ESD protection

■ Voltage compensated operating range

= −4.2V to −5.7V

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Connection Diagrams

24-Pin DIP 28-Pin PLCC

Logic Symbol

Order Number Package Number Package Description

100344PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100344QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100344QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

Industrial Temperature Range (

−40°C to +85°C)

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100344

Pin Descriptions Tr uth Table

H = HIGH Voltage level
L = LOW Voltage level
Cutoff = lower-than-LOW state
X = Don’t Care

Note 1: Retains data pr esent before ei t her LE

or E go HIGH.

Logic Diagram

Pin Names Description

D

0–D7

Data Inputs

E

Enable Input

LE

Latch Enabl e Input

OEN

Output Enable Input

Q

0–Q7

Data Outputs

Inputs Outputs

D

n

E LE OEN Q

n

LLL L L
HLL L H
X H X L Latched (Note 1)
X X H L Latched (Note 1)
X X X H Cutoff

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100344

Absolute Maximum Ratings(Note 2) Recommended Operating

Conditions

Note 2: The “Absolute Maximum Ratings” are those value s beyond which

the safety of the dev ice cannot b e guaranteed . The device sh ould not be
operated at these limit s. The parametric values defi ned in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recomm ended O peratin g Cond itions ” table will defin e the condition s
for actual device operation.

Note 3: ESD testing conforms to MIL-STD-883, Method 3015.

Commercial Version
DC Electrical Characteristics

(Note 4)

V

EE

= −4.2V to −5.7V, VCC = V

CCA

= GND, T

C

= 0°C to +85°C

Note 4: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasin g the al l owable syste m opera ti ng ran ge s. Cond it i ons fo r t estin g sho w n in the tabl es are cho­sen to guarantee operation under “worst case” conditions.

AC Electrical Characteristics

V

EE

= −4.2V to −5.7V, VCC = V

CCA

= GND

Note 5: The propagation delay s pec ified is for single output swit c hing. Delays may vary up to 300 ps with multiple outpu ts s witching.

Storage Temperature (T

STG

) −65°C to +150°C

Maximum Junction Temperature (T

J

) +150°C

V

EE

Pin Potential to Ground Pin −7.0V to +0.5V

Input Voltage (DC) V

EE

to +0.5V

Output Current (DC Output HIGH)

−100 mA

ESD (Note 3)

≥2000V

Case Temperature (T

C

)

Commercial 0

°C to +85°C

Industrial

−40°C to +85°

Supply Voltage (VEE) −5.7V to −4.2V

Symbol Parameter Min Typ Max Units Conditions

V

OH

Output HIGH Voltage −1025 −955 −870 mV VIN = VIH (Max) Loading with

V

OL

Output LOW Voltage −1830 −1705 −1620 mV or VIL (Min) 25Ω to −2.0V

V

OHC

Output HIGH Voltage −1035 mV VIN = VIH (Min) Loading with

V

OLC

Output LOW Voltage −1610 mV or VIL (Max) 25Ω to −2.0V

V

OLZ

Cutoff LOW Voltage −1950 mV VIN = VIH (Min) OEN = HIGH

or VIL (Max)

V

IH

Input HIGH Voltage −1165 −870 mV Guaranteed HIGH Signal for All Inputs

V

IL

Input LOW Voltage −1830 −1475 mV Guaranteed LOW Signal for All Inputs

I

IL

Input LOW Current 0.50 µAVIN = VIL (Min)

I

IH

Input HIGH Current 240 µAVIN = VIH (Max)

I

EE

Power Supply Current Inputs Open

−178 −85 mA V

EE

= −4.2V to −4.8V

−185 −85 VEE = −4.2V to −5.7V

Symbol Parameter

TC = 0°CT

C

= +25°CT

C

= +85°C

Units Conditions

Min Max Min Max Min Max

t

PLH

Propagation Delay

0.90 2.10 0.90 2.10 1.00 2.30 ns

Figures 1, 2

t

PHL

Dn to Output (Note 5)

t

PLH

Propagation Delay

1.60 3.10 1.60 3.10 1.80 3.40 ns

Figures 1, 4

t

PHL

LE, E to Output (Note 5)

t

PZH

Propagation Delay 1.60 4.20 1.60 4.20 1.60 4.20

ns

Figures 1, 2

t

PHZ

OEN to Output 1.00 2.70 1.00 2.70 1.00 2.70 (Note 5)

t

TLH

Transition Time

0.45 2.00 0.45 2.00 0.45 2.00 ns Figures 1, 3

t

THL

20% to 80%, 80% to 20%

t

S

Setup Time D0–D

7

1.00 1.00 1.10 ns Figures 1, 3

t

H

Hold Time D0–D

7

0.10 0.10 0.10 ns Figures 1, 3

tPW(H) Pulse Width HIGH

2.00 2.00 2.00 ns Figures 1, 3

LE, E

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100344

Commercial Version (Continued)
PLCC AC Electrical Characteristics

V

EE

= −4.2V to −5.7V, VCC = V

CCA

= GND

Note 6: The propagation dela y sp ec if ied is for single output swit c hing. Delays may vary up to 300 ps with multiple outpu ts s w it c hing.
Note 7: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same pack-

aged device. Th e specif ications apply to any out puts s witchin g in the sa me dire ction e ither HI GH-to-LO W ( t

OSHL

), or LOW-to-HIGH ( t

OSLH

), or in opposite

directions both HL and LH (t

OST

). Parameters t

OST

and tps guaranteed by design.

Symbol Parameter

TC = 0°CT

C

= +25°CT

C

= +85°C

Units Conditions

Min Max Min Max Min Max

t

PLH

Propagation Delay

0.90 1.90 0.90 1.90 1.00 2.10 ns

Figures 1, 2

t

PHL

Dn to Output (Note 6)

t

PLH

Propagation Delay

1.60 2.90 1.60 2.90 1.80 3.20 ns

Figures 1, 4

t

PHL

LE, E to Output (Note 6)

t

PZH

Propagation Delay 1.60 4.00 1.60 4.00 1.60 4.00

ns

Figures 1, 2

t

PHZ

OEN to Output 1.00 2.50 1.00 2.50 1.00 2.50 (Note 6)

t

TLH

Transition Time

0.45 1.90 0.45 1.90 0.45 1.90 ns Figures 1, 3

t

THL

20% to 80%, 80% to 20%

t

S

Setup Time D0–D70.90 0.90 1.00 ns Figures 1, 3

t

H

Hold Time D0–D70.00 0.00 0.00 ns Figures 1, 3

tPW(H) Pulse Width HIGH

2.00 2.00 2.00 ns Figures 1, 3

LE, E

t

OSHL

Maximum Skew Common Edge PLCC Only
Output-to-Output Variation 330 330 330 ps (Note 7)
Data to Output Path

t

OSLH

Maximum Skew Common Edge PLCC Only
Output-to-Output Variation 330 330 330 ps (Note 7)
Data to Output Path

t

OST

Maximum Skew Opposite Edge PLCC Only
Output-to-Output Variation 330 330 330 ps (Note 7)
Data to Output Path

t

PS

Maximum Skew PLCC Only
Pin (Signal) Transition Variation 230 230 230 ps (Note 7)
Data to Output Path

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100344

Test Circuitry

Note:

• V

CC

, V

CCA

= +2V, VEE = −2.5V

• L1 and L2 = equal length 50Ω impedance lines

• R

T

= 50Ω terminator internal to scope

• Decoupling 0.1 µF from GND to V

CC

and V

EE

• All unused outputs are loaded with 25Ω to G ND

• C

L

= Fixture and stray capacitance ≤ 3 pF

FIGURE 1. AC Test Circuit

Switching Waveforms

FIGURE 2. Propagation Delay and Cutoff Times FIGURE 3. Setup, Hold and Pulse Width Times

FIGURE 4. Propagation Delay LE

, E to Q

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100344

Physical Dimensions inches (millimeters) unless otherwise noted

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide

Package Number N24E

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100344 Low Power 8-Bit Latch with Cut-Off Drivers

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

Package Number V28A

Fairchild does not assume any responsibility for use of any circuitry described , no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or syste ms

which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provide d in the labe l ing, can be re a­sonably expected to result in a significant injury to the
user.

2. A critical component in any com ponen t of a life s uppor t
device or system whose failure to perform can be rea­sonably expected to cause the failure of the l ife support
device or system, or to affect its safety or effectiveness.

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