Datasheet 100336SCX, 100336SC, 100336QIX, 100336QI, 100336QCX Datasheet (Fairchild Semiconductor)

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August 1989 Revised August 2000

100336 Low Power 4-Stage Counter/Shift Register

General Description

The 100336 operates as either a modulo-16 up/down counter or as a 4-bit bidirectional shift register. Three Select (S

) inputs determine the mode of operation, as

shown in the Function Select table. Two Count Enable (CEP

, CET) inputs are provided for ease of cascading in

multistage counters. One Co unt Enable (CET

) input also

doubles as a Serial Data ( D

) input for shift-up operatio n.

For shift-down operation, D

is the Serial Data input. In

counting operations t he Terminal Count (TC

) output goes LOW when the counter reaches 15 in the count/up mode or 0 (zero) in the count/down mode. In the shift modes, the TC output repeats the Q3 output. The dual nature of this TC/Q

output and the D0/CET input means that one interconnection from one stage to th e next highe r stage serves as the

link for multistage counting or shift-up operation. The indi-

vidual Preset (P

) inputs are used to en ter data in para llel

or to preset the coun ter in program mable counter applications. A HIGH signal on the Mas ter Reset (M R) inp ut overrides all other inputs and async hronously clears the flipflops. In addition, a synchronou s clear is provided, as well as a complement fu nction wh ich s ynchron ously inverts the contents of the flip-flo ps. All inputs have 50 k

Ω pull-down

resistors.

Features

■ 40% power reduction of the 100136

■ 2000V ESD protection

■ Pin/function compatible with 100136

■ Voltage compensated operating range

= −4.2V to −5.7V

■ Available to industrial grade temperature range

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Connection Diagrams

24-Pin DIP/SOIC 28-Pin PLCC

Logic Symbol

Order Number Package Number Package Description

100336SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 100336PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 100336QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 100336QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

Industrial Temperature Range (

−40°C to +85°C)

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100336

Function Select Table Pin Descriptions

Truth Table

Q0 = LSB

1 = L if Q0–Q3 = LLLL

H if Q

0–Q3

≠ LLLL

2 = L if Q

0–Q3

= HHHH

H if Q

0–Q3

≠ HHHH

H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care



= LOW-to-HIGH Transition

Note 1: Before the clock, TC

is Q

After the clock, TC is Q

Function

L L L Parallel Load L L H Complement L H L Shift Left

L H H Shift Right H L L Count Down HLHClear H H L Count Up HHHHold

Pin Names Description

CP Clock Pulse Input CEP

Count Enable Parallel Input (Active LOW)

/CET Serial Data Input/Count Enable

Trickle Input (Active LOW)

0–S2

Select Inputs MR Master Reset Input P

0–P3

Preset Inputs D

Serial Data Input TC

Terminal Count Output Q

0–Q3

Data Outputs Q

0–Q3

Complementary Data Outputs

Inputs Outputs

MR S

2S1S0

CEP D0/CET D3CP Q3Q2Q1Q

TC Mode

LLLL X X X



P3P2P1P

L Preset (Parallel Load)

LLLHX X X



Q3Q2Q1Q

LInvert

LLHL X X X



D3Q3Q2Q

Shift to LSB

LLHH X X X



Q2Q1Q0D0Q3 (Note 1) Shift to MSB

LHLL L L X



0–3

) minus 1 1 Count Down

LHLL H L XXQ

3Q2Q1Q0

1 Count Down with CEP not active

LHLL X H XXQ

3Q2Q1Q0

H Count Down with CET not active

LHLHX X X



LLLL H Clear

LHHL L L X



0–3

) plus 1 2 Cou nt Up

LHHL H L XXQ

3Q2Q1Q0

2 Count Up with CEP not active

LHHL X H XXQ

3Q2Q1Q0

H Count Up with CET not active

L HHH X X X XQ

3Q2Q1Q0

HHold HLLL X X XX LLL L L HLLH X X XXLLLL L HLHL X X XXLLLL L H L H H X X X X L L L L L Asynchronous H H L L X L X X L L L L L Master Reset HHLL X H XXLLLL H HHLH X X XXLLLL H HHHL X X XXLLLL H H HHH X X X X L L L L H

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100336

Logic Diagram

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100336

Absolute Maximum Ratings(Note 2) Recommended Operating

Conditions

Note 2: Absolute maximum ratings are those values beyond which the

device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.

Note 3: ESD testing conf orm s t o M I L-STD-883, Method 3015.

Commercial Version DC Electrical Characteristics

(Note 4)

= −4.2V to −5.7V, VCC = V

CCA

= GND, T

= 0°C to +85°C

Note 4: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the all owable syste m opera ti ng r ange s. Co ndi ti ons fo r t est ing shown in the ta ble s are chosen to guarantee operation under “worst case” conditions.

Storage Temperature (T

STG

) −65°C to +150°C

Maximum Junction Temperature (T

) +150°C

Pin Potential to Ground Pin −7.0V to +0.5V

Input Voltage (DC) V

to +0.5V

Output Current (DC Output HIGH)

−50 mA

ESD (Note 3)

≥ 2000V

Case Temperature (T

)

Commercial 0

°C to +85°C

Industrial

−40°C to +85°C

Supply Voltage (V

) −5.7V to −4.2V

Symbol Parameter Min Typ Max Units Conditions

Output HIGH Voltage −1025 −955 −870 mV VIN =V

IH (Max)

Loading with

Output LOW Voltage −1830 −1705 −1620 mV or V

IL (Min)

50Ω to −2.0V

OHC

Output HIGH Voltage −1035 mV VIN = V

IH(Min)

Loading with

OLC

Output LOW Voltage −1610 mV or V

IL (Max)

50Ω to −2.0V

Input HIGH Voltage −1165 −870 mV Guaranteed HIGH Signal

for All Inputs

Input LOW Voltage −1830 −1475 mV Guaranteed LOW Signal

for All Inputs

Input LOW Current 0.50 µAVIN = VIL (Min)

Input HIGH Current 240 µAVIN = VIH (Max)

Power Supply Current −165 −80 Inputs Open

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100336

Commercial Version (Con tinu ed) DIP AC Characteristics

= −4.2V to −5.7V, VCC = V

CCA

= GND

Note 5: The propagation delay s pec ified is for single output swit c hing. Delays may vary up to 250 ps with multiple outpu ts s witching.

Symbol Parameter

TC = 0°CT

= +25°CT

= +85°C

Units Conditions

MinMaxMinMaxMinMax

SHIFT

Shift Frequency 300 300 300 MHz Figures 2, 3

PLH

Propagation Delay

1.00 2.00 1.00 2.00 1.00 2.00 ns

Figures 1, 3

PHL

CP to Qn, Q

(Note 5)

PLH

Propagation Delay

2.10 3.50 2.10 3.50 2.10 3.70 ns

Figures 1, 7, 8

PHL

CP to TC (Shift) (Note 5)

PLH

Propagation Delay

2.40 4.40 2.40 4.40 2.60 4.70 ns

Figures 1, 9

PHL

CP to TC (Count) (Note 5)

PLH

Propagation Delay

1.40 2.50 1.40 2.50 1.50 2.60 ns

Figures 1, 4

PHL

MR to Qn, Q

(Note 5)

PLH

Propagation Delay

2.80 5.10 2.90 5.20 3.10 5.50 ns

Figures 1, 12

PHL

MR to TC (Count) (Note 5)

PHL

Propagation Delay

2.40 4.00 2.40 4.00 2.50 4.10 ns

Figures 1, 10, 11

MR to TC (Shift) (Note 5)

PLH

Propagation Delay

1.80 3.10 1.80 3.10 1.90 3.30 ns

PHL

D0/CET to TC Figures 1, 5

PLH

Propagation Delay

1.90 4.10 1.90 4.10 2.10 4.40 ns

(Note 5)

PHL

Sn to TC

TLH

Transition Time

0.35 1.20 0.35 1.20 0.35 1.20 ns Figures 1, 3

THL

20% to 80%, 80% to 20%

Setup Time

1.00 1.00 1.00

1.50 1.50 1.50

D0/CET 1.30 1.30 1.30

ns Figures 6, 4

CEP 1.40 1.40 1.40 S

3.40 3.40 3.40

MR (Release Time) 2.60 2.60 2.60

Hold Time

0.40 0.40 0.40

0.30 0.30 0.30 ns Figure 6

D0/CET 0.30 0.30 0.30 CEP 0.20 0.20 0.20 S

0.10 0.10 0.10

tPW(H) Pulse Width HIGH

2.00 2.00 2.00 ns Figures 3, 4

CP, MR

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100336

SOIC and PLCC AC Electrical Characteristics

= −4.2V to −5.7V, VCC = V

CCA

= GND

Note 6: The propagation dela y sp ec if ied is for single output swit c hing. Delays may vary up to 250 ps with multiple outpu ts s w it c hing. Note 7: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same pack-

aged device. Th e specif ications apply to any out puts s witchin g in the sa me dire ction e ither HI GH-to-LO W ( t

OSHL

), or LOW-to-HIGH ( t

OSLH

), or in opposite

directions both HL and LH (t

OST

). Parameters t

OST

and tps guaranteed by design

Symbol Parameter

= 0°CT

= +25°CT

= +85°C

Units Conditions

MinMaxMinMaxMinMax

SHIFT

Shift Frequency 350 350 350 MHz Figures 2, 3

PLH

Propagation Delay

1.00 1.80 1.00 1.80 1.00 1.80 ns

Figures 1, 2

PHL

CP to Qn, Q

(Note 6)

PLH

Propagation Delay

2.10 3.30 2.10 3.30 2.10 3.50 ns

Figures 1, 7, 8

PHL

CP to TC (Shift) (Note 6)

PLH

Propagation Delay

2.40 4.20 2.40 4.20 2.60 4.50 ns

Figures 1, 9

PHL

CP to TC (Count) (Note 6)

PLH

Propagation Delay

1.40 2.30 1.40 2.30 1.50 2.40 ns

Figures 1, 4

PHL

MR to Qn, Q

(Note 6)

PLH

Propagation Delay

2.80 4.90 2.90 5.00 3.10 5.30 ns

Figures 1, 12

PHL

MR to TC (Count) (Note 6)

PHL

Propagation Delay

2.40 3.80 2.40 3.80 2.50 3.90 ns

Figures 1, 10, 11

MR to TC (Shift) (Note 6)

PLH

Propagation Delay

1.80 2.90 1.80 2.90 1.90 3.10 ns

PHL

D0/CET to TC Figures 1, 5

PLH

Propagation Delay

1.90 3.90 1.90 3.90 2.10 4.20 ns

(Note 6)

PHL

Sn to TC

TLH

Transition Time

0.35 1.10 0.35 1.10 0.35 1.10 ns Figures 1, 3

THL

20% to 80%, 80% to 20%

Setup Time

0.90 0.90 0.90

1.40 1.40 1.40

ns Figures 4, 6

D0/CET 1.20 1.20 1.20 CEP 1.30 1.30 1.30 S

3.30 3.30 3.30

MR (Release Time) 2.50 2.50 2.50

Hold Time

0.30 0.30 0.30

0.20 0.20 0.20 ns

Figure 6

D0/CET 0.20 0.20 0.20 CEP 0.10 0.10 0.10 S

0.00 0.00 0.00

tPW(H) Pulse Width HIGH

2.00 2.00 2.00 ns Figures 3, 4

CP, MR

OSHL

Maximum Skew Common Edge PLCC Only Output-to-Output Variation 200 200 200 ps (Note 7) Clock to Output Path

OSLH

Maximum Skew Common Edge PLCC Only Output-to-Output Variation 200 200 200 ps (Note 7) Clock to Output Path

OST

Maximum Skew Opposite Edge PLCC Only Output-to-Output Variation 230 230 230 ps (Note 7) Clock to Output Path

Maximum Skew PLCC Only Pin (Signal) Transition Variation 245 245 245 ps (Note 7) Clock to Output Path

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100336

Industrial Version PLCC DC Electrical Characteristics

(Note 8)

= −4.2V to −5.7V, VCC = V

CCA

= GND, T

= −40°C to +85°C

Note 8: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasin g the al l owable syste m opera ti ng ran ge s. Cond it i ons fo r t estin g sho w n in the tabl es are chosen to guarantee operation under “worst case” conditions.

PLCC AC Electrical Characteristics

= −4.2V to −5.7V, VCC = V

CCA

= GND

Note 9: The propagation delay s pec ified is for single output swit c hing. Delays may vary up to 250 ps with multiple outpu ts s witching.

Symbol Parameter

= −40°CTC = 0°C to +85°C

Units Conditions

Min Max Min Max

Output HIGH Voltage −1085 −870 −1025 −870 mV VIN =V

IH (Max)

Loading with

Output LOW Voltage −1830 −1575 −1830 −1620 mV or V

IL (Min)

50Ω to −2.0V

OHC

Output HIGH Voltage −1095 −1035 mV VIN = V

IH(Min)

Loading with

OLC

Output LOW Voltage −1565 −1610 mV or V

IL (Max)

50Ω to −2.0V

Input HIGH Voltage −1170 −870 −1165 −870 mV Guaranteed HIGH Signal for All Inputs

Input LOW Voltage −1830 −1480 −1830 −1475 mV Guaranteed LOW Signal for All Inputs

Input LOW Current 0.50 0.50 µAVIN = VIL (Min)

Input HIGH Current 240 240 µAVIN = VIH (Max)

Power Supply Current −165 −75 −165 −80 mA Inputs Open

Symbol Parameter

TC = −40°CT

= +25°CT

= +85°C

Units Conditions

MinMaxMinMaxMinMax

SHIFT

Shift Frequency 325 350 350 MHz Figures 2, 3

PLH

Propagation Delay

1.00 1.80 1.00 1.80 1.00 1.80 ns

Figures 1, 3

PHL

CP to Qn, Q

(Note 9)

PLH

Propagation Delay

2.00 3.30 2.10 3.30 2.10 3.50 ns

Figures 1, 7, 8

PHL

CP to TC (Shift) (Note 9)

PLH

Propagation Delay

2.40 4.20 2.40 4.20 2.60 4.50 ns

Figures 1, 9

PHL

CP to TC (Count) (Note 9)

PLH

Propagation Delay

1.40 2.30 1.40 2.30 1.50 2.40 ns

Figures 1, 4

PHL

MR to Qn, Q

(Note 9)

PLH

Propagation Delay

2.80 4.90 2.90 5.00 3.10 5.30 ns

Figures 1, 12

PHL

MR to TC (Count) (Note 9)

PHL

Propagation Delay

2.40 3.80 2.40 3.80 2.50 3.90 ns

Figures 1, 10, 11

MR to TC

(Shift) (Note 9)

PLH

Propagation Delay

1.70 2.90 1.80 2.90 1.90 3.10 ns

PHL

D0/CET to TC Figures 1, 5

PLH

Propagation Delay

1.80 3.90 1.90 3.90 2.10 4.20 ns

(Note 9)

PHL

Sn to TC

TLH

Transition Time

0.20 1.90 0.35 1.10 0.35 1.10 ns Figures 1, 3

THL

20% to 80%, 80% to 20%

Setup Time

1.40 0.90 0.90

1.70 1.40 1.40

ns Figure 6

D0/CET 1.80 1.20 1.20 CEP 1.80 1.30 1.30 S

3.30 3.30 3.30

MR (Release Time) 2.60 2.50 2.50

Hold Time

0.90 0.30 0.30

1.00 0.20 0.20 ns Figure 6D0/CET 0.70 0.20 0.20

CEP 0.60 0.10 0.10 S

0.00 0.00 0.00

tPW(H) Pulse Width HIGH CP, MR 2.20 2.00 2.00 ns Figures 3, 4

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100336

Test Circuitry

Notes:

, V

CCA

= +2V, VEE = −2.5V L1, L2 and L3 = equal length 50Ω impedance lines R

= 50Ω terminator internal to scope

Decoupling 0.1 µF from GND to V

and V

All unused outputs are loaded with 50Ω to G ND C

= Fixture and stray capacitance ≤ 3 pF

FIGURE 1. AC Test Circuit

Notes:

For shift right mode, +1.05V is applied at S

The feedback path from output to input should be as short as possible.

FIGURE 2. Shift Frequency Test Circuit (Shift Left)

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Switching Waveforms

FIGURE 3. Propagation Delay (Clock) and Transition Times

FIGURE 4. Propagation Delay (Reset)

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Switching Waveforms (C ontinued)

FIGURE 5. Propagation Delay (Serial Data, Selects)

Notes:

is the minimum time before the transition of the clock that information must be present at the data input.

is the minimum time after the transition of the clock that information must remain unchanged at the data input.

FIGURE 6. Setup and Hold Time

Note: Shift Right Mode; S0 = H, S1 = H, S2 = L.

FIGURE 7. Propagation Delay, Clock to Terminal Count (Shift Right Mode)

Note: Shift Left Mode; S0 = L, S1 = H, S2 = L.

FIGURE 8. Propagation Delay, Clock to Terminal Count (Shift Left Mode)

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Switching Waveforms (Continued)

Note:

*Decimal representation of binary outputs. Count Up: S

= L, S1 = H, S2 = H; Count Down: S0 = L, S1 = L, S2 = H.

Measurement take n at 50% point of waveform.

FIGURE 9. Propagation Delay, Clock to Terminal Count (Count Up and Count Down Modes)

Note: Shift Right Mode; S0 = H, S1 = H, S2 = L.

FIGURE 10. Propagation Delay, Master Reset to Terminal Count (Shift Right Mode)

Note: Shift Left Mode; S0 = L, S1 = H, S2 = L.

FIGURE 11. Propagation Delay, Master Reset to Terminal Count (Shift Left Mode)

Note:

*Decimal representation of binary outputs. Count Up Mode: S

= L, S1 = H, S2 = H.

Note:

*Decimal representation of binary outputs. Count Down Mode: S

= L, S1 = L, S2 = H.

FIGURE 12. Propagation Delay, Master Reset to Terminal Count (Count Up and Count Down Modes)

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100336

Applications

3-Stage Divider, Preset Count D own Mode

Note: If S0 = S1 = S2 = LOW, then TC = LOW

Slow Expansion Scheme

Fast Expansion Scheme

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100336

Physical Dimensions inches (millimeters) unless otherwise noted

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

Package Number M24B

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide

Package Number N24E

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100336 Low Power 4-Stage Counter/Shift Register

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

Package Number V28A

Fairchild does not assume any responsibility for use of any circuitr y described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are device s or syste ms

which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the user.

2. A critical component in any compon ent of a life supp ort device or system whose failure t o perform can be reasonably expected to ca use the failure of the life supp ort device or system, or to affect its safety or effectiveness.

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