Datasheet 5962-9153601VXA, 5962-9153601VYA, 5962-9153601MYA, 5962-9153601MXA, 100331MW8 Datasheet (NSC)

100331
Low Power Triple D Flip-Flop

General Description

The 100331 contains three D-type, edge-triggered master/
slave flip-flops with true and complement outputs, a Com­mon Clock (CP

C

), and Master Set (MS) and Master Reset

(MR) inputs. Each flip-flophas individual Clock (CP

n

), Direct

Set (SD

n

) and Direct Clear (CDn) inputs. Data enters a mas-

ter when both CP

n

and CPCare LOW and transfers to a

slave when CP

n

or CPC(or both) go HIGH. The Master Set,

Master Reset and individual CD

n

and SDninputs override

the Clock inputs. All inputs have 50 kΩ pull-down resistors.

Features

n 35%power reduction of the 100131
n 2000V ESD protection
n Pin/function compatible with 100131
n Voltage compensated operating range=−4.2V to −5.7V
n Available to industrial grade temperature range
n Available to Standard Microcircuit Drawing (SMD)

5962-9153601

Logic Symbol

Pin Names Description

CP

0

–CP

2

Individual Clock Inputs

CP

C

Common Clock Input

D

0–D2

Data Inputs

CD

0

–CD

2

Individual Direct Clear Inputs

SD

n

Individual Direct Set Inputs
MR Master Reset Input
MS Master Set Input
Q

0-Q2

Data Outputs
Q

0–Q2

Complementary Data Outputs

Connection Diagrams

DS100300-1

24-Pin DIP

DS100300-2

24-Pin Quad Cerpak

DS100300-3

August 1998

100331 Low Power Triple D Flip-Flop

© 1998 National Semiconductor Corporation DS100300 www.national.com

Logic Diagram

Truth Tables
Synchronous Operation

(Each Flip-Flop)

Inputs Outputs

D

n

CPnCPCMS MR Qn(t+1)

SD

n

CD

n

L

N

LLL L

H

N

LLL H

LL

N

LL L

HL

N

LL H
XLLLL Qn(t)
X H X L L Qn(t)
X X H L L Qn(t)

H=HIGH Voltage Level
L=LOW Voltage Level
X=Don’t Care
U=Undefined
t=Time before CP Positive Transition
t+1=Time after CP Positive Transition

N

=

LOW to HIGH Transition

Asynchronous Operation

(Each Flip-Flop)

Inputs Outputs

D

n

CPnCPCMS MR Qn(t+1)

SD

n

CD

n

XX XH L H
XX X L H L
XX XHH U

DS100300-5

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Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Above which the useful life may be impaired

Storage Temperature (T

STG

) −65˚C to +150˚C

Maximum Junction Temperature (T

J

)

Ceramic +175˚C

Pin Potential to

Ground Pin (V

EE

) −7.0V to +0.5V

Input Voltage (DC) V

EE

to +0.5V

Output Current

(DC Output HIGH) −50 mA

ESD (Note 2) ≤ 2000V

Recommended Operating
Conditions

Case Temperature (TC)

Military −55˚C to +125˚C

Supply Voltage (V

EE

) −5.7V to −4.2V

Note 1: Absolute maximum ratings are those values beyond which the de­vice may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.

Note 2: ESD testing conforms to MIL-STD-883, Method 3015.

Military Version

DC Electrical Characteristics

V

EE

=

−4.2V to −5.7V, V

CC

=

V

CCA

=

GND, T

C

=

−55˚C to +125˚C

Symbol Parameter Min Max Units T

C

Conditions Notes

V

OH

Output HIGH Voltage −1025 −870 mV 0˚C to V

IN

=

V

IH

(Max)

or V

IL

(Min)

Loading with

50Ω to −2.0V

(Notes 3,

4, 5)

+125˚C

−1085 −870 mV −55˚C

V

OL

Output LOW Voltage −1830 −1620 mV 0˚C to

+125˚C

−1830 −1555 mV −55˚C

V

OHC

Output HIGH Voltage −1035 mV 0˚C to V

IN

=

V

IH

(Min)

or V

IL

(Max)

Loading with

50Ω to −2.0V

(Notes 3,

4, 5)

+125˚C

−1085 mV −55˚C

V

OLC

Output LOW Voltage −1610 mV 0˚C to

+125˚C

−1555 mV −55˚C

V

IH

Input HIGH Voltage −1165 −870 mV −55˚C to Guaranteed HIGH Signal

(Notes 3,

4, 5, 6)

+125˚C for all Inputs

V

IL

Input LOW Voltage −1830 −1475 mV −55˚C to Guaranteed LOW Signal

(Notes 3,

4, 5, 6)

+125˚C for all Inputs

I

IL

Input LOW Current 0.50 µA −55˚C to V

EE

=

−4.2V

(Notes 3,

4, 5)

+125˚C V

IN

=

V

IL

(Min)

I

IH

Input HIGH Current 240 µA 0˚C to V

EE

=

−5.7V

V

IN

=

V

IH

(Max)

(Notes 3,

4, 5)

+125˚C

340 µA −55˚C

I

EE

Power Supply Current −130 −50 mA −55˚C to Inputs Open

(Notes 3,

4, 5)

+125˚C

Note 3: F100K 300 Series cold temperature testing is performed by temperature soaking (toguaranteejunctiontemperatureequals−55˚C),thentestingimmediately
without allowing for the junction temperature to stabilize due toheatdissipationafterpower-up.Thisprovides“coldstart”specswhichcanbeconsideredaworstcase
condition at cold temperatures.

Note 4: Screen tested 100%on each device at −55˚C, +25˚C, and +125˚C, Subgroups, 1, 2, 3, 7 and 8.
Note 5: Sampled tested (Method 5005, Table I) on each manufactured lot at −55˚C, +25˚C, and +125˚C, Subgroups A1, 2, 3, 7 and 8.
Note 6: Guaranteed by applying specified input condition and testing V

OH/VOL

.

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AC Electrical Characteristics

V

EE

=

−4.2V to −5.7V, V

CC

=

V

CCA

=

GND

Symbol Parameter T

C

=

−55˚C T

C

=

+25˚C T

C

=

+125˚C Units Conditions Notes

Min Max Min Max Min Max

f

max

Toggle Frequency 400 400 400 MHz

Figures 2, 3

(Note

10)

t

PLH

Propagation Delay 0.50 2.20 0.60 2.00 0.50 2.40 ns

t

PHL

CPCto Output

Figures 1, 3

t

PLH

Propagation Delay 0.50 2.20 0.60 2.00 0.50 2.40 ns

t

PHL

CPnto Output

t

PLH

Propagation Delay 0.50 2.20 0.60 2.00 0.50 2.40 CPn,CP

C

=

L

Figures

1, 4

(Notes

7, 8,

9)

t

PHL

CDn,SDnto Output ns

t

PLH

0.50 2.40 0.60 2.10 0.50 2.50 CPn,CP

C

=

H

t

PHL

t

PLH

Propagation Delay 0.70 2.70 0.80 2.60 0.80 2.90 CPn,CP

C

=

L

t

PHL

MS, MR to Output ns

t

PLH

0.70 2.90 0.80 2.80 0.80 3.10 CPn,CP

C

=

H

t

PHL

t

TLH

Transition Time 0.20 1.40 0.20 1.40 0.20 1.40 ns

Figures 1, 3, 4

t

THL

20%to 80%,80%to 20

%

t

s

Setup Time

Figure 5

(Note

10)

D

n

1.00 0.80 0.90

CD

n

,SDn(Release Time) 1.50 1.30 1.60 ns

Figure 4

MS, MR (Release Time) 2.50 2.30 2.50

t

h

Hold Time D

n

1.50 1.30 1.60 ns

Figure 5

tpw(H) Pulse Width HIGH

CP

n

,CPC,CDn, 2.00 2.00 2.00 ns

Figures 3, 4

SDn, MR, MS

Note 7: F100K 300 Series cold temperature testing is performed by temperature soaking (toguaranteejunctiontemperatureequals−55˚C),thentestingimmediately
without allowing for the junction temperature to stabilize due toheatdissipationafterpower-up.Thisprovides“coldstart”specswhichcanbeconsideredaworstcase
condition at cold temperatures.

Note 8: Screen tested 100%on each device at +25˚C. Temperature only, Subgroup A9.
Note 9: Sample tested (Method 5005, Table I) on each Mfg. lot at +25˚C, Subgroup A9, and at +125˚C, and −55˚C Temp., Subgroups A10 and A11.
Note 10: Not tested at +25˚C, +125˚C and −55˚C Temperature (design characterization data).

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Test Circuits

DS100300-6

FIGURE 1. AC Test Circuit

DS100300-7

Notes:

V

CC,VCCA

=

+2V, V

EE

=

−2.5V
L1 and L2=Equal length 50Ω impedance lines
R

T

=

50Ω terminator internal to scope

Decoupling 0.1 µF from GND to V

CC

and V

EE

All unused outputs are loaded with 50Ω to GND
C

L

=

Fixture and stray capacitance ≤ 3pF

FIGURE 2. Toggle Frequency Test Circuit

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Switching Waveforms

Note 11: tsis the minimum time before the transition of the clock that information must be present at the data input.
Note 12: t

h

is the minimum time after the transition of the clock that information must remain unchanged at the data input.

DS100300-8

FIGURE 3. Propagation Delay (Clock) and Transition Times

DS100300-9

FIGURE 4. Propagation Delay (Resets)

DS100300-10

FIGURE 5. Data Setup and Hold Time

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Physical Dimensions inches (millimeters) unless otherwise noted

24-Lead Ceramic Dual-In-Line Package (0.400" Wide) (D)

NS Package Number J24E

24-Lead Quad Cerpak (F)

NS Package Number W24B

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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE­VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI­CONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or sys­tems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and whose fail­ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.

2. A critical component in any component of a life support
device or system whose failure to perform can be rea­sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.

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Corporation

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100331 Low Power Triple D Flip-Flop

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.