Datasheet 100325SCX, 100325SC, 100325QIX, 100325QI, 100325QCX Datasheet (Fairchild Semiconductor)

© 2000 Fairchild Semiconductor Corporation DS009879 www.fairchildsemi.com

July 1988
Revised August 2000

100325 Low Power Hex ECL-to-TTL Translator

100325
Low Power Hex ECL-to-TTL Translator

General Description

The 100325 is a he x translato r for convert ing F100K logic
levels to TTL logic levels. Differential inputs a llow each cir­cuit to be used as an inverting, no n-inverting or differential
receiver. An internal reference voltage generator p rovides
V

BB

for single-ended operation, or for use in Schmitt trigger

applications. All inputs have 50k

Ω pull-down resistors.

When the inputs are either un connected or at the same
potential the outputs will go LOW.

When used in sin gle-ended operation the apparent input
threshold of the true inputs is 20mV to 40mV higher (posi­tive) than the threshold of the com plementary inputs. The
V

EE

and V

TTL

power may be applied in either order.

Features

■ Pin/function compatible with 100125

■ Meets 100125 AC specifications

■ 50% power reduction of the 100125

■ Differential inputs with built in offset

■ Standard FAST

 outputs

■ 2000V ESD protection

■

−4.2V to −5.7V operating range

■ Available to industrial grade temperature range

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Connection Diagrams

24-Pin DIP/SOIC 28-Pin PLCC

Pin Descriptions

FAST is a registered trademark of Fairc hild Semiconductor Corporation.

Order Number Package Number Package Description

100325SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
100325PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100325QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100325QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

Industrial Temperature Range (

−40°C to +85°C)

Pin Names Description

D

0–D5

Data Inputs

D

0–D5

Inverting Data Inputs

Q

0–Q5

Data Outputs

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100325

Truth Table

H = HIGH Voltage Level
L = LOW Voltage Level

Logic Diagram

Inputs Outputs

D

n

D

n

Q

n

LHL
HLH
LLL
HHL

OPEN OPEN L

V

EE

V

EE

L

LV

BB

L

HV

BB

H

V

BB

LH

V

BB

HL

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100325

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: The “Absolute Maximum Ratings” are those value s beyond which

the safety of the dev ice cannot b e guaranteed . The device sh ould not be
operated at these limit s. The parametric values defi ned in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recomm ended O peratin g Cond itions ” table will defin e the condition s
for actual device operation.

Note 2: ESD testing conforms to MIL-STD-883, Method 3015.

Commercial Version
DC Electrical Characteristics

V

EE

= −4.2V to −5.7V, VCC = GND, V

TTL

= +4.5V to 5.5V, TC = 0°C to +85°C (Note 3)

Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasin g the al l owable syste m opera ti ng ran ge s. Cond it i ons fo r t estin g sho w n in the tabl es are cho­sen to guarantee operation under “worst case” conditions.

Note 4: Test one output at a time.

DIP AC Electrical Characteristics

V

EE

= −4.2V to −5.7V, VCC = GND, V

TTL

= +4.5V to +5.5V

Storage Temperature (T

STG

) −65°C to +150°C

Maximum Junction Temperature (T

J

) +150°C

V

EE

Pin Potential to Ground Pin −7.0V to +0.5V

V

TTL

Pin Potential to Ground Pin −0.5V to +6.0V

Input Voltage (DC) V

EE

to +0.5V

Voltage Applied to Output

in HIGH State (with V

CC

= 0V) −0.5V to V

CC

Current Applied to Output

in LOW State (Max) twice the rated I

OL

(mA)

ESD (Note 2)

≥2000V

Case Temperature (T

C

)

Commercial 0

°C to +85°C

Industrial

−40°C to +85°C

Supply Voltage (V

EE

) −5.7V to −4.2V

Symbol Parameter Min Typ Max Units Conditions

V

BB

Output Reference Voltage −1380 −1320 −1260 mV I

VBB

= −2.1 mA

V

IH

Single-Ended Input

−1165 −870 mV

Guaranteed HIGH Signal for All Inputs

HIGH Voltage (with One Input Tied to V

BB

)

V

IL

Single-Ended Input

−1830 −1475 mV

Guaranteed LOW Signal for All Inputs

LOW Voltage (with One Input Tied to VBB)

V

OH

Output HIGH Voltage 2.5 V IOH = −2.0 mA VIN = V

IH (Max)

V

OL

Output LOW Voltage 0.5 V IOL = 20 mA or V

IL (Min)

V

DIFF

Input Voltage Differential 150 mV Required for Full Output Swing

V

CM

Common Mode Voltage VCC − 2.0 VCC − 0.5 V

I

IH

Input HIGH Current 350 µAVIN = V

IH (Max)

, D0–D5 = VBB,

D0–D5 = V

IL (Min)

I

IL

Input LOW Current 0.5 µAVIN = V

IL (Min)

, D0–D5 = V

BB

I

OS

Output Short-Circuit Current −150 −60 mA V

OUT

= GND (Note 4)

I

EE

VEE Power Supply Current −37 −27 −17 mA D0–D5 = V

BB

I

TTL

V

TTL

Power Supply Current 45 65 mA D0–D5 = V

BB

Symbol Parameter

TC = 0°CT

C

= +25°CT

C

= +85°C

Units Conditions

Min Max Min Max Min Max

t

PLH

Propagation Delay

0.80 3.50 0.90 3.70 1.00 4.00 ns

CL = 15 pF

t

PHL

Data to Output Figures 1, 2

t

PLH

Propagation Delay

1.60 4.30 1.70 4.50 1.80 4.80 ns

CL = 50 pF

t

PHL

Data to Output Figures 1, 3

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100325

Commercial Version (Continued)
SOIC and PLCC AC Electrical Characteristics

V

EE

= −4.2V to −5.7V, VCC = GND, V

TTL

= +4.5V to +5.5V

Note 5: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same pack­aged device. Th e specif ications apply to any out puts s witchin g in the sa me dire ction e ither HI GH-to-LO W ( t

OSHL

), or LOW-to-HIGH ( t

OSLH

), or in opposite

directions both HL and LH (t

OST

). Parameters t

OST

and tPS guaranteed by design.

Symbol Parameter

TC = 0°CT

C

= +25°CT

C

= +85°C

Units Conditions

Min Max Min Max Min Max

t

PLH

Propagation Delay

0.80 3.30 0.90 3.50 1.00 3.80 ns

CL = 15 pF

t

PHL

Data to Output Figures 1, 2

t

PLH

Propagation Delay

1.60 4.10 1.70 4.30 1.80 4.60 ns

CL = 50 pF

t

PHL

Data to Output Figures 1, 3

t

OSHL

Maximum Skew Common Edge PLCC Only
Output-to-Output Variation 0.65 0.65 0.65 ns (Note 5)
Data to Output Path

t

OSLH

Maximum Skew Common Edge PLCC Only
Output-to-Output Variation 0.65 0.65 0.65 ns (Note 5)
Data to Output Path

t

OST

Maximum Skew Opposite Edge PLCC Only
Output-to-Output Variation 2.20 2.20 2.20 ns (Note 5)
Data to Output Path

t

PS

Maximum Skew PLCC Only
Pin (Signal) Transition Variation 2.10 2.10 2.10 ns (Note 5)
Data to Output Path

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100325

Industrial Version
PLCC DC Electrical Characteristics

V

EE

= −4.2V to −5.7V, VCC = GND, TC = −40°C to +85°C (Note 6)

Note 6: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasin g the al l owable syste m opera ti ng ran ge s. Cond it i ons fo r t estin g sho w n in the tabl es are cho­sen to guarantee operation under “worst case” conditions.

Note 7: Test one output at a time.

PLCC AC Electrical Characteristics

V

EE

= −4.2V to −5.7V, VCC = GND, V

TTL

= +4.5V to +5.5V

Switching Waveform

FIGURE 1. Propagation Delay

Symbol Parameter

T

C

= −40°CTC = 0°C to +85°C

Units Conditions

Min Max Min Max

V

BB

Output Reference Voltage −1395 −1255 −1380 −1260 mV I

VBB

= −2.1 mA

V

IH

Single-Ended Input

−1170 −870 −1165 −870 mV

Guaranteed HIGH Signal for All Inputs

HIGH Voltage (with One Input Tied to V

BB

)

V

IL

Single-Ended Input

−1830 −1480 −1830 −1475 mV

Guaranteed LOW Signal for All Inputs

LOW Voltage (with One Input Tied to VBB)

V

OH

Output HIGH Voltage 2.5 2.5 V IOH = −2.0 mA VIN = V

IH (Max)

V

OL

Output LOW Voltage 0.5 0.5 V IOL = 20 mA or V

IL (Min)

V

DIFF

Input Voltage Differential 150 150 mV Required for Full Output Swing

V

CM

Common Mode Voltage VCC − 2.0 VCC − 0.5 VCC − 2.0 VCC − 0.5 V

I

IH

Input HIGH Current 450 350 µAVIN = V

IH (Max)

, D0–D5 = VBB,

D0–D5 = V

IL (Min)

I

IL

Input LOW Current 0.5 0.5 µAVIN = V

IL (Min)

, D0–D5 = V

BB

I

OS

Output Short-Circuit Current −150 −60 −150 −60 mA V

OUT

= GND (Note 7)

I

EE

VEE Power Supply Current −37 −15 −37 −17 mA D0–D5 = V

BB

I

TTL

V

TTL

Power Supply Current 65 65 mA D0–D5 = V

BB

Symbol Parameter

T

C

= −40°CT

C

= +25°CT

C

= +85°C

Units Conditions

Min Max Min Max Min Max

t

PLH

Propagation Delay

0.80 3.30 0.90 3.50 1.00 3.80 ns

CL = 15 pF

t

PHL

Data to Output Figures 1, 2

t

PLH

Propagation Delay

1.60 4.10 1.70 4.30 1.80 4.60 ns

CL = 50 pF

t

PHL

Data to Output Figures 1, 3

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100325

Test Circuits

Note:

• V

CC

= 0V, VEE = −4.5V, V

TTL

= +5V

• L1 and L2 = equal length 50Ω impedance lines

• R

T

= 50Ω terminator internal to scope

• Decoupling 0.1 µF from GND to V

CC

, VEE and V

TTL

• All unused outputs are loaded with 500Ω to GND

• C

L

= Fixture and stray capacitance = 15 pF

FIGURE 2. AC Test Circuit for 15 pF Loading

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100325

Test Circuits (Continued)

Note:

• V

CC

= 0V, VEE = −4.5V, V

TTL

= +5V

• L1 and L2 = equal length 50Ω impedance lines

• R

T

= 50Ω terminator internal to scope

• Decoupling 0.1 µF from GND to V

CC

, VEE and V

TTL

• All unused outputs are loaded with 500Ω to GND

• C

L

= Fixture and stray capacitance = 50 pF

FIGURE 3. AC Test Circuit for 50 pF Loading

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100325

Physical Dimensions inches (millimeters) unless otherwise noted

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

Package Number M24B

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide

Package Number N24E

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100325 Low Power Hex ECL-to-TTL Translator

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

Package Number V28A

Fairchild does not assume any responsibility for use of any circuitry described , no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:

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which, (a) are intended for surgical implant into the
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to perform when properly used in accordance with
instructions for use provide d in the labe l ing, can be re a­sonably expected to result in a significant injury to the
user.

2. A critical com ponen t in any com ponen t of a life s uppor t
device or system whose failure to perform can be rea­sonably expected to cause the failure of the l ife support
device or system, or to affect its safety or effectiveness.

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