Datasheet 5962-9153001VXA, 5962-9153001VYA, 5962-9153001MYA, 5962-9153001MXA, 100324MW8 Datasheet (NSC)

100324
Low Power Hex TTL-to-ECL Translator

General Description

The 100324 is a hex translator, designed to convert TTL
logic levels to 100K ECL logic levels.Theinputsarecompat­ible with standard or Schottky TTL. A common Enable (E),
when LOW, holds all inverting outputs HIGH and holds all
true outputs LOW. The differential outputs allow each circuit
to be used as an inverting/non-inverting translator, or as a
differential line driver.Theoutputlevelsare voltage compen­sated over the full −4.2V to −5.7V range.

When the circuit is used in the differential mode, the100324,
due to its high common mode rejection, overcomes voltage
gradients between the TTL and ECL ground systems. The
V

EE

and V

TTL

power may be applied in either order.

The 100324 is pin and function compatible with the 100124
with similar AC performance, but features power dissipation
roughly half of the 100124 to ease system cooling require­ments.

Features

n Pin/function compatible with 100124
n Meets 100124 AC specifications
n 50%power reduction of the 100124
n Differential outputs
n 2000V ESD protection
n −4.2V to −5.7V operating range
n Standard Microcircuit Drawing

(SMD) 5962-9153001

Logic Diagram

Pin Names Description

D

0–D5

Data Inputs
E Enable Input
Q

0–Q5

Data Outputs
Q

0–Q5

Complementary

Data Outputs

DS100313-4

August 1998

100324 Low Power Hex TTL-to-ECL Translator

© 1998 National Semiconductor Corporation DS100313 www.national.com

Connection Diagrams

24-Pin DIP

DS100313-1

24-Pin Quad Cerpak

DS100313-2

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Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National SemiconductorSalesOffice/
Distributors for availability and specifications.

Above which the useful life may be impaired.

Storage Temperature (T

STG

) −65˚C to +150˚C

Maximum Junction Temperature (T

J

)

Ceramic +175˚C

V

EE

Pin Potential to Ground Pin −7.0V to +0.5V

V

TTL

Pin Potential to Ground Pin −0.5V to +6.0V
Input Voltage (DC) −0.5V to +6.0V
Output Current (DC Output HIGH) −50 mA

ESD (Note 2) ≥2000V

Recommended Operating
Conditions

Case Temperature (TC)

Military −55˚C to +125˚C

Supply Voltage (V

EE

) −5.7V to −4.2V

Note 1: Absolute maximum ratings are those values beyond which the de­vice may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.

Note 2: ESD testing conforms to MIL-STD-883, Method 3015.

Military Version

DC Electrical Characteristics

V

EE

=

−4.2V to −5.7V, V

CC

=

V

CCA

=

GND, T

C

=

−55˚C to +125˚C, V

TTL

=

+4.5V to +5.5V

Symbol Parameter Min Max Units T

C

Conditions Notes

V

OH

Output HIGH Voltage −1025 −870 mV 0˚C to +125˚C V

IN

=

V

IH

(Max)

or VIL(Min)

Loading with

50Ω to −2.0V

(Notes 3, 4, 5)

−1085 −870 mV −55˚C

V

OL

Output LOW Voltage −1830 −1620 mV 0˚C to +125˚C

−1830 −1555 mV −55˚C

V

OHC

Output HIGH Voltage −1035 mV 0˚C to +125˚C V

IN

=

V

IH

(Max)

or VIL(Min)

Loading with

50Ω to −2.0V

(Notes 3, 4, 5)

−1085 mV −55˚C

V

OLC

Output LOW Voltage −1610 mV 0˚C to +125˚C

−1555 mV −55˚C

V

IH

Input HIGH Voltage 2.0 5.0 V −55˚C to +125˚C Over V

TTL,VEE,TC

Range (Notes 3, 4, 5, 6)

V

IL

Input LOW Voltage 0.0 0.8 V −55˚C to +125˚C Over V

TTL,VEE,TC

Range (Notes 3, 4, 5, 6)

I

IH

Input HIGH Current 20 µA −55˚C to +125˚C V

IN

=

+2.7V (Notes 3, 4, 5)

Breakdown Test 100 µA −55˚C to +125˚C V

IN

=

+7.0V

I

IL

Input LOW Current

Data −0.9 mA −55˚C to +125˚C V

IN

=

+0.4V (Notes 3, 4, 5)

Enable −5.4

V

FCD

Input Clamp Diode Voltage −1.2 V −55˚C to +125˚C I

IN

=

−18 mA (Notes 3, 4, 5)

I

EEVEE

Power Supply Current −70 −22 mA −55˚C to +125˚C All Inputs V

IN

=

+4.0V (Notes 3, 4, 5)

I

TTLVTTL

Power Supply Current 38 mA −55˚C to +125˚C All Inputs V

IN

=

GND (Notes3, 4, 5)

Note 3: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately
without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides “cold start” specs which can be considereda worst case
condition at cold temperatures.

Note 4: Screen tested 100%on each device at −55˚C, +25˚C, and +125˚C, Subgroups 1, 2, 3, 7, and 8.
Note 5: Sample tested (Method 5005, Table I) on each manufactured lot at −55˚C, +25˚C, and +125˚C, Subgroups A1, 2, 3, 7, and 8.
Note 6: Guaranteed by applying specified input condition and testing V

OH/VOL

.

AC Electrical Characteristics

V

EE

=

−4.2V to −5.7V, V

CC

=

V

CCA

=

GND, V

TTL

=

+4.5V to +5.5V

Symbol Parameter T

C

=

−55˚C T

C

=

+25˚C T

C

=

+125˚C Units Conditions Notes

Min Max Min Max Min Max

t

PLH

Propagation Delay 0.50 3.00 0.50 2.90 0.30 3.30 ns (Notes 7, 8, 9)

t

PHL

Data and Enable to Output

Figures 1, 2

t

TLH

Transition Time 0.35 1.80 0.45 1.80 0.45 1.80 ns (Note 10)

t

THL

20%to 80%,80%to 20

%

Note 7: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately
after power-up. This provides “cold start” specs which can be considered a worst case condition at cold temperatures.

Note 8: Screen tested 100%on each device at +25˚C temperature only, Subgroup A9.
Note 9: Sample tested (Method 5005, Table I) on each manufactured lot at +25˚C, Subgroup A9, and at +125˚C and −55˚C temperatures, Subgroups A10 and A11.
Note 10: Not tested at +25˚C, +125˚C, and −55˚C temperature (design characterization data).

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Switching Waveform

Test Circuit

DS100313-6

FIGURE 1. Propagation Delay and Transition Times

DS100313-5

Note:

V

CC,VCCA

=

0V, V

EE

=

−4.5V, V

TTL

=

+5.0V, V

IH

=

+3.0V
L1, L2 and L3=equal length 50Ω impedance lines
R

T

=

50Ω terminator internal to scope

Decoupling 0.1 µF from GND to V

CC,VEE

and V

TTL

All unused outputs are loaded with 50Ω to −2V or with equivalent ECL terminator network
C

L

=

Fixture and stray capacitance ≤ 3pF

FIGURE 2. AC Test Circuit

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Physical Dimensions inches (millimeters) unless otherwise noted

24-Lead Ceramic Dual-In-Line Package (0.400" Wide) (D)

NS Package Number J24E

24 Lead Quad Cerpak (F)

NS Package Number W24B

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LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE­VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI­CONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or sys-

tems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and whose fail­ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.

2. A critical component in any component of a life support
device or system whose failure to perform can be rea­sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.

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100324 Low Power Hex TTL-to-ECL Translator

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.