Datasheet 100322QIX, 100322QI, 100322QCX, 100322QC, 100322PC Datasheet (Fairchild Semiconductor)

Page 1

October 1989 Revised August 2000

100322 Low Power 9-Bit Buffer

General Description

The 100322 is a monolithic 9-bit buffer. The device contains nine non-inver ting buffer gates with s ingle input and output. All inputs h ave 50 k

Ω pull-down resistors and all

outputs are buffered.

Features

■ 30% power reduction of the 100122

■ 2000V ESD protection

■ Pin/function compatible with 100122

■ Voltage compensated operating range

= −4.2V to −5.7V

■ Available to MIL-STD-883

■ Available to industrial grade temperature range

(PLCC package only)

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Logic Symbol

Pin Descriptions

Truth Table

H = HIGH Voltage Level L = LOW Voltage Level

Connection Diagrams

24-Pin DIP

28-Pin PLCC

Order Number Package Number Package Description

100322PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 100322QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 100322QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

Industrial Temperature Range (

−40°C to +85°C)

Pin Names Description

, D

Data Inputs

, O

Data Outputs

Inputs Outputs

- D

O1 - O

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100322

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: The “Absolute Maximum Ratings” are those values beyon d which

the safety of the dev ice cannot be guaranteed. T he device sh ould not be operated at these limit s. The parametric values defin ed in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recomme nded O peratin g Cond itions ” table will defin e the condition s for actual device operation.

Note 2: ESD testing conf orm s t o M I L-STD-883, Method 3015.

Commercial Version DC Electrical Characteristics

(Note 3)

VEE = −4.2V to −5.7V, VCC = V

CCA

= GND, TC = 0°C to +85°C

Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the all owable syste m opera ti ng r ange s. Co ndi ti ons fo r t est ing shown in the ta ble s are chosen to guarantee operation under “worst case” conditions.

DIP AC Electrical Characteristics

VEE = −4.2V to −5.7V, VCC = V

CCA

= GND

Note 4: The propagation dela y sp ec if ied is for single output swit c hing. Delays may vary up to 200 ps with multiple outpu ts s w it c hing.

Storage Temperature (T

STG

) −65°C to +150°C

Maximum Junction Temperature (T

) +150°C

Pin Potential to Ground Pin −7.0V to +0.5V

Input Voltage (DC) V

to +0.5V

Output Current (DC Output HIGH)

−50 mA

ESD (Note 2)

≥ 2000V

Case Temperature (T

)

Commercial 0

°C to +85°C

Industrial

−40°C to +85°C

Supply Voltage (V

) −5.7V to −4.2V

Symbol Parameter Min Typ Max Units Conditions

Output HIGH Voltage −1025 −955 −870

VIN =V

IH (Max)

Loading with

Output LOW Voltage −1830 −1705 −1620 or V

IL (Min)

50Ω to −2.0V

OHC

Output HIGH Voltage −1035

VIN = V

IH(Min)

Loading with

OLC

Output LOW Voltage −1610 or V

IL (Max)

50Ω to −2.0V

Input HIGH Voltage −1165 −870 mV Guaranteed HIGH Signal

for All Inputs

Input LOW Voltage −1830 −1475 mV Guaranteed LOW Signal

for All Inputs

Input LOW Current 0.50 µAVIN = V

IL (Min)

Input HIGH Current 240 µAVIN = V

IH (Max)

Power Supply Current −65 −30 mA Inputs Open

Symbol Parameter

= 0°CT

= +25°CT

= +85°C

Units Conditions

Min Max Min Max Min Max

PLH

Propagation Delay

0.45 1.45 0.45 1.45 0.45 1.55 ns

Figures 1, 2

PHL

Data to Output (Note 4)

TLH

Transition Time

0.35 1.20 0.35 1.20 0.35 1.20 ns Figures 1, 2

THL

20% to 80%, 80% to 20%

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100322

Commercial Version (Continued) PLCC AC Electrical Characteristics

VEE = −4.2V to −5.7V, VCC = V

CCA

= GND

Note 5: The propagation delay s pec ified is for single output swit c hing. Delays may vary up to 200 ps with multiple outpu ts s witching. Note 6: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same pack-

aged device. The sp ecifica tions a pply to an y outp uts swit ching in the sam e direc tion eithe r HIGH to LOW (t

OSHL

), or LOW to HIGH (t

OSLH

), or in opposite

directions both HL and LH (t

OST

). Parameters t

OST

and tPS guaranteed by de s ign.

Industrial Version PLCC DC Electrical Characteristics

(Note 7)

VEE = −4.2V to −5.7V, VCC = V

CCA

= GND, TC = −40°C to +85°C

Note 7: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasin g the al l owable syste m opera ti ng ran ge s. Cond it i ons fo r t estin g sho w n in the tabl es are chosen to guarantee operation under “worst case” conditions.

PLCC AC Electrical Characteristics

VEE = −4.2V to −5.7V, VCC = V

CCA

= GND

Note 8: The propagation delay s pec ified is for single output swit c hing. Delays may vary up to 200 ps with multiple outpu ts s witching.

Symbol Parameter

= 0°CT

= +25°CT

= +85°C

Units Conditions

MinMaxMinMaxMinMax

PLH

Propagation Delay

0.45 1.25 0.45 1.25 0.45 1.35 ns

Figures 1, 2

PHL

Data to Output (Note 5)

TLH

Transition Time

0.35 1.10 0.35 1.10 0.35 1.10 ns Figures 1, 2

THL

20% to 80%, 80% to 20%

OSHL

Maximum Skew Common Edge Output-to-Output Variation 200 200 200 ps (Note 6) Data to Output Path

OSLH

Maximum Skew Common Edge Output-to-Output Variation 200 200 200 ps (Note 6) Data to Output Path

OST

Maximum Skew Opposite Edge Output-to-Output Variation 260 260 260 ps (Note 6) Data to Output Path

Maximum Skew Pin (Signal) Transition Variation 200 200 200 ps (Note 6) Data to Output Path

Symbol Parameter

TC = −40°CT

= 0°C to +85°C

Units Conditions

Min Max Min Max

Output HIGH Voltage −1085 −870 −1025 −870

VIN =V

IH (Max)

Loading with

Output LOW Voltage −1830 −1575 −1830 −1620 or V

IL (Min)

50Ω to −2.0V

OHC

Output HIGH Voltage −1095 −1035

VIN = V

IH (Min)

Loading with

OLC

Output LOW Voltage −1565 −1610 or V

IL (Max)

50Ω to −2.0V

Input HIGH Voltage −1170 −870 −1165 −870 mV Guaranteed HIGH Signal

for All Inputs

Input LOW Voltage −1830 −1480 −1830 −1475 mV Guaranteed LOW Signal

for All Inputs

Input LOW Current 0.50 0.50 µAVIN = V

IL (Min)

Input HIGH Current 300 240 µAVIN = V

IH (Max)

Power Supply Current −65 −30 −65 −30 mA Inputs Open

Symbol Parameter

TC = −40°CT

= +25°CT

= +85°C

Units Conditions

MinMaxMinMaxMinMax

PLH

Propagation Delay

0.45 1.25 0.45 1.25 0.45 1.35 ns

Figures 1, 2

PHL

Data to Output (Note 8)

TLH

Transition Time

0.30 1.20 0.35 1.10 0.35 1.10 ns Figures 1, 2

THL

20% to 80%, 80% to 20%

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100322

Test Circuit

Notes:

, V

CCA

= +2V, VEE = −2.5V

L1 and L2 = equal length 50Ω impedance lines R

= 50Ω terminator internal to scope

Decoupling 0.1 µF from GND to V

and V

All unused outputs are loaded with 50Ω to G ND C

= Fixture and stray capacitance ≤ 3 pF

FIGURE 1. AC Test Circuit

Switching Waveforms

FIGURE 2. Propagation Delay and Transition Times

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100322

Physical Dimensions inches (millimeters) unless otherwise noted

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide

Package Number N24E

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100322 Low Power 9-Bit Buffer

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

Package Number V28A

Fairchild does not assume any responsibility for use of any circuitr y described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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