Datasheet 100314SCX, 100314SC, 100314QIX, 100314QI, 100314QCX Datasheet (Fairchild Semiconductor)

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February 1990 Revised August 2000

100314 Low Power Quint Differential Line Receiver

General Description

The 100314 is a mo nolithic quint differential li ne receiver with emitter-followe r outputs. An internal re ference supply (V

) is available for single-ended reception. When used in

single-ended operatio n the appa rent in put thresh old of the true inputs is 25 mV to 30 mV higher (positive) than the threshold of the complementary inputs. Unlike other F100K ECL devices, the inputs do not have inp ut pul l-down resistors.

Active current sources provi de common-mode re jection of

1.0V in either the posit ive or negative di rection. A defin ed output state exists if both inverting and non-inverting inputs are at the same potential between V

and VCC. The

defined state is logic HIGH on the O

a–Oe

outputs.

Features

■ 35% power reduction of the 100114

■ 2000V ESD protection

■ Pin/function compatible with 100114

■ Voltage compensated operating range

= −4.2V to −5.7V

■ Available to industrial grade temperature range (PLCC package only)

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Logic Symbol

Pin Descriptions

Connection Diagrams

24-Pin DIP/SOIC

28-Pin PLCC

Order Number Package Number Package Description

100314SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 100314PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 100314QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 100314QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

Industrial Temperature Range (

−40°C to +85°C)

Pin Names Description

a–De

Data Inputs

a–De

Inverting Data Inputs

a–Oe

Data Outputs

a–Oe

Complementary Data Outputs

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100314

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: The “Absolute Maximum Ratings” are those values beyon d which

the safety of the dev ice cannot be guaranteed. T he device sh ould not be operated at these limit s. The parametric values defin ed in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recomme nded O peratin g Cond itions ” table will defin e the condition s for actual device operation.

Note 2: ESD testing conf orm s t o M I L-STD-883, Method 3015.

Commercial Version DC Electrical Characteristics

(Note 3)

= −4.2V to −5.7V, VCC = V

CCA

= GND, T

= 0°C to +85°C

Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the all owable syste m opera ti ng r ange s. Co ndi ti ons fo r t est ing shown in the ta ble s are chosen to guarantee operation under “worst case” conditions.

Storage Temperature (T

STG

) −65°C to +150°C

Maximum Junction Temperature (T

) +150°C

Pin Potential to Ground Pin (V

) −7.0V to +0.5V

Input Voltage (DC) V

to +0.5V

Output Current (DC Output HIGH)

−50 mA

ESD (Note 2)

≥2000V

Case Temperature (T

)

Commercial 0

°C to +85°C

Industrial

−40°C to +85°C

Supply Voltage (V

) −5.7V to −4.2V

Symbol Parameter Min Typ Max Units Conditions

Output HIGH Voltage −1025 −955 −870 mV VIN = VIH (Max) Loading with

Output LOW Voltage −1830 −1705 −1620 mV or VIL (Min) 50Ω to −2.0V

OHC

Output HIGH Voltage −1035 mV VIN = VIH Loading with

OLC

Output LOW Voltage −1610 mV or VIL (Max) 50Ω to −2.0V

Output Reference Voltage −1380 −1320 −1260 mV I

VBB

= −250 µA

DIFF

Input Voltage Differential 150 mV Required for Full Output Swing

Common Mode Voltage VCC − 2.0 VCC − 0.5 V

Single-Ended Guaranteed HIGH Signal for All Input HIGH Voltage −1110 −870 mV Inputs (with one input tied to VBB)

(Max) + V

DIFF

Single-Ended Guaranteed LOW Signal for All Input LOW Voltage −1830 −1530 mV Inputs (with one input tied to VBB)

(Min) − V

DIFF

Input LOW Current 0.50 µAVIN = VIL (Min)

Input HIGH Current 240 µAVIN = V

IH (Max)

, Da–De = VBB,

a–De

= V

IL(Min)

CBO

Input Leakage Current −10 µAVIN = VEE, Da–De = VBB,

a–De

= V

IL (Min)

Power Supply Current −60 −30 mA Da–De = VBB, Da–De = V

IL (Min)

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100314

Commercial Version (Continued) DIP AC Electrical Characteristics

= −4.2V to −5.7V, VCC = V

CCA

= GND

SOIC and PLCC AC Electrical Characteristics

= −4.2V to −5.7V, VCC = V

CCA

= GND

Note 4: Maximum toggle freque nc y at which VOH and VOL DC specifications a re m aintained. Note 5: Maximum toggle freque nc y at which outputs mainta in 150 mV swing. Note 6: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same pack-

aged device. The sp ecifica tions a pply to an y outp uts swit ching in the sam e direc tion eithe r HIGH -to-LOW (t

OSHL

), or LOW-to-HIGH (t

OSLH

), or in opposite

directions both HL and LH (t

OST

). Parameters t

OST

and tPS guaranteed by de s ign.

Note 7: All skews calculated usin g input crossing point to ou t put c ros s ing point propagation delays.

Symbol Parameter

TC = 0°CT

= +25°CT

= +85°C

Units Conditions

Min Max Min Max Min Max

MAXFS

Toggle Frequency

250 250 250 MHz (Note 2)

(Full Swing)

MAXRS

Toggle Frequency

700 700 700 MHz (Note 3)

(Reduced Swing)

PLH

Propagation Delay

0.65 1.90 0.65 2.00 0.70 2.00 ns

PHL

Data to Output

Figures 1, 2

TLH

Transition Time

0.35 1.20 0.35 1.20 0.35 1.20 ns

THL

20% to 80%, 80% to 20%

Symbol Parameter

TC = 0°CT

= +25°CT

= +85°C

Units Conditions

Min Max Min Max Min Max

MAXFS

Toggle Frequency

250 250 250 MHz (Note 4)

(Full Swing)

MAXRS

Toggle Frequency

700 700 700 MHz (Note 5)

(Reduced Swing)

PLH

Propagation Delay

0.65 1.70 0.65 1.80 0.70 1.80 ns

PHL

Data to Output

Figures 1, 2

TLH

Transition Time

0.35 1.10 0.35 1.10 0.35 1.10 ns

THL

20% to 80%, 80% to 20%

PLH

Propagation Delay

0.70 1.50 0.80 1.60 0.90 1.80 ns PLCC only

PHL

Data to Output

OSHL

Maximum Skew Common Edge PLCC only Output-to-Output Variation 280 280 280 ps (Note 6)(Note 7) Data to Output Path

OSLH

Maximum Skew Common Edge PLCC only Output-to-Output Variation 330 330 330 ps (Note 6)(Note 7) Data to Output Path

OST

Maximum Skew Opposite Edge PLCC only Output-to-Output Variation 330 330 330 ps (Note 6)(Note 7) Data to Output Path

Maximum Skew PLCC only Pin (Signal) Transition Variation 320 320 320 ps (Note 6)(Note 7) Data to Output Path

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100314

Industrial Version PLCC DC Electrical Characteristics

(Note 8)

= −4.2V to −5.7V, VCC = V

CCA

= GND, T

= −40°C to +85°C

Note 8: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the all owable syste m opera ti ng r ange s. Co ndi ti ons fo r t est ing shown in the ta ble s are chosen to guarantee operation under “worst case” conditions.

PLCC AC Electrical Characteristics

= −4.2V to −5.7V, VCC = V

CCA

= GND

Note 9: Maximum toggle freq uency at which VOH and VOL DC specifications ar e m aintained. Note 10: Maximum toggle frequency at which outputs maintain 150 mV swing.

Symbol Parameter

= −40°CTC = 0°C to +85°C

Units Conditions

Min Max Min Max

Output HIGH Voltage −1085 −870 −1025 −870 mV VIN = VIH (Max) Loading with

Output LOW Voltage −1830 −1575 −1830 −1620 mV or VIL (Min) 50Ω to −2.0V

OHC

Output HIGH Voltage −1095 −1035 mV VIN = V

Loading with

OLC

Output LOW Voltage −1565 −1610 mV or VIL (Min) 50Ω to −2.0V

Output Reference Voltage −1395 −1255 −1380 −1260 mV I

VBB

= −250 µA

DIFF

Input Voltage Differential 150 150 mV Required for Full Output Swing

Common Mode Voltage VCC − 2.0 VCC − 0.5 VCC − 2.0 VCC − 0.5 V

Single-Ended Guaranteed HIGH Signal for All Input HIGH Voltage −1115 −870 −1110 −870 mV Inputs (with one input tied to VBB)

VBB (Max) + V

DIFF

Single-Ended Guaranteed LOW Signal for All Input LOW Voltage −1830 −1535 −1830 −1530 mV Inputs (with one input tied to VBB)

VBB (Min) − V

DIFF

Input LOW Current 0.50 0.50 µAVIN = V

IL (Min)

Input HIGH Current 240 240 µAVIN = V

IH (Max)

, Da–De = VBB,

Da–De = V

IL (Min)

CBO

Input Leakage Current −10 −10 µAVIN = VEE, Da–De = V

Da–De = V

IL (Min)

Power Supply Current −60 −30 −60 −30 mA Da–De = VBB, Da–De = V

IL (Min)

Symbol Parameter

TC = −40°CT

= +25°CT

= +85°C

Units Conditions

Min Max Min Max Min Max

MAXFS

T oggle Fre quenc y

250 250 250 MHz (Note 9)

(Full Swing)

MAXRS

T oggle Fre quenc y

700 700 700 MHz (Note 10)

(Reduced Swing)

PLH

Propagation Delay

0.65 1.70 0.65 1.80 0.70 1.80

Figures 1, 2

PHL

Data to Output

TLH

Transition Time

0.20 1.40 0.35 1.10 0.35 1.10 ns

THL

20% to 80%, 80% to 20%

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100314

Test Circuit

Note:

• V

, V

CCA

= +2V, VEE = −2.5V

• L1 and L2 = equal length 50Ω impedance lines

• R

= 50Ω terminator internal to scope

• Decoupling 0.1 µF from GND to V

and V

• All unused outputs are loaded with 50Ω to G ND

• C

= Fixture and stray capacitance ≤ 3 pF

FIGURE 1. AC Test Circuit

Switching Waveforms

FIGURE 2. Propagation Delay and Transition Times

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100314

Physical Dimensions inches (millimeters) unless otherwise noted

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

Package Number M24B

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide

Package Number N24E

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100314 Low Power Quint Differential Line Receiver

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

Package Number V28A

Fairchild does not assume any responsibility for use of any circuitry described , no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or syst ems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provide d in the labe l ing, can be re asonably expected to result in a significant injury to the user.

2. A critical com ponen t in any com ponen t of a life s uppor t device or system whose failure to perform can be reasonably expected to cause the failure of the l ife support device or system, or to affect its safety or effectiveness.

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