Datasheet 100304QI, 100304QCX, 100304QC, 100304PC, 100304DC Datasheet (Fairchild Semiconductor)

Page 1

August 1989 Revised August 2000

100304 Low Power Quint AND/NAND Gate

General Description

The 100304 is monolithic quint AND/NAND gate. The Function output is the wire-NOR of all five AND gate outputs. All inputs have 50 k

Ω pull-down resistors.

Features

■ Low Power Operation

■ 2000V ESD protection

■ Pin/function compatible with 100104

■ Voltage compensated operating range

= −4.2V to −5.7V

■ Available to industrial grade temperature range (PLCC package only)

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Logic Symbol

Pin Descriptions

Logic Equation

Connection Diagrams

24-Pin DIP

28-Pin PLCC

Order Number Package Number Package Description

100304PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 100304QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 100304QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

Industrial Temperature Range (

−40°C to +85°C)

Pin Names Description

na–Dne

Data Inputs F Function Output O

a–Oe

Data Outputs O

a–Oe

Complementary Data Outputs

= (D

• D2a) + (D1b • D2b) + (D1c • D2c) +

• D2d) + (D1e • D2e).

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100304

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: The “Absolute Maximum Ratings” are those values beyon d which

the safety of the dev ice cannot be guaranteed. T he device sh ould not be operated at these limit s. The parametric values defin ed in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recomme nded O peratin g Cond itions ” table will defin e the condition s for actual device operation.

Note 2: ESD testing conf orm s t o M I L-STD-883, Method 3015.

Commercial Version DC Electrical Characteristics

(Note 3)

= −4.2V to −5.7V, VCC = V

CCA

= GND, T

= 0°C to +85°C

Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the all owable syste m opera ti ng r ange s. Co ndi ti ons fo r t est ing shown in the ta ble s are chosen to guarantee operation under “worst case” conditions.

DIP AC Electrical Characteristics

= −4.2V to −5.7V, VCC = V

CCA

= GND

PLCC AC Electrical Characteristics

= −4.2V to −5.7V, VCC = V

CCA

= GND

Storage Temperature (T

STG

) −65°C to +150°C

Maximum Junction Temper ature (T

) +150°C

Pin Potential to Ground Pin −7.0V to +0.5V

Input Voltage (DC) V

to +0.5V

Output Current (DC Output HIGH)

−50 mA

ESD (Note 2)

≥2000V

Case Temperature (T

)

Commercial 0

°C to +85°C

Industrial

−40°C to +85°C

Supply Voltage (V

) −5.7V to −4.2V

Symbol Parameter Min Typ Max Units Conditions

Output HIGH Voltage −1025 −955 −870 mV VIN =V

IH (Max)

Loading with

Output LOW Voltage −1830 −1705 −1620 mV or V

IL (Min)

50Ω to −2.0V

OHC

Output HIGH Voltage −1035 mV VIN = V

IH(Min)

Loading with

OLC

Output LOW Voltage −1610 mV or V

IL (Max)

50Ω to −2.0V

Input HIGH Voltage −1165 −870 mV Guaranteed HIGH Signal

for All Inputs

Input LOW Voltage −1830 −1475 mV Guaranteed LOW Signal

for All Inputs

Input LOW Current 0.50 µAVIN = V

IL (Min)

Input High Current

2a–D2e

250 µAVIN = VIH(Max)

D1a–D

350

Power Supply Current −69 −43 −30 mA Inputs open

Symbol Parameter

TC = 0°CT

= +25°CT

= +85°C

Units Conditions

Min Max Min Max Min Max

PLH

Propagation Delay

0.40 1.75 0.40 1.65 0.40 1.75 ns

PHL

Dna–Dne to O, O

Figures 1, 2

PLH

Propagation Delay

1.00 2.60 1.00 2.60 1.15 3.20 ns

PHL

Data to F

TLH

Transition Time

0.35 1.20 0.35 1.20 0.35 1.20 ns

THL

20% to 80%, 80% to 20%

Symbol Parameter

TC = 0°CT

= +25°CT

= +85°C

Units Conditions

Min Max Min Max Min Max

PLH

Propagation Delay

0.40 1.55 0.40 1.45 0.40 1.55 ns

PHL

Dna–Dne to O, O

Figures 1, 2

PLH

Propagation Delay

1.00 2.40 1.00 2.40 1.15 3.00 ns

PHL

Data to F

TLH

Transition Time

0.35 1.10 0.35 1.15 0.35 1.10 ns

THL

20% to 80%, 80% to 20%

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100304

Industrial Version PLCC DC Electrical Characteristics

(Note 4)

= −4.2V to −5.7V, VCC = V

CCA

= GND, T

= −40°C to +85°C

Note 4: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasin g the al l owable syste m opera ti ng ran ge s. Cond it i ons fo r t estin g sho w n in the tabl es are chosen to guarantee operation under “worst case” conditions.

PLCC AC Electrical Characteristics

= −4.2V to −5.7V, VCC = V

CCA

= GND

Symbol Parameter

= −40°CTC = 0°C to +85°C

Units Conditions

Min Max Min Max

Output HIGH Voltage −1085 −870 −1025 −870

VIN =V

IH (Max)

Loading with

Output LOW Voltage −1830 −1575 −1830 −1620 or V

IL (Min)

50Ω to −2.0V

OHC

Output HIGH Voltage −1095 −1035

VIN = V

IH(Min)

Loading with

OLC

Output LOW Voltage −1565 −1610 or V

IL (Max)

50Ω to −2.0V

Input HIGH Voltage −1170 −870 −1165 −870 mV Guaranteed HIGH Signal

for All Inputs

Input LOW Voltage −1830 −1480 −1830 −1475 mV Guaranteed LOW Signal

for All Inputs

Input LOW Current 0.50 0.50 µAVIN = V

IL (Min)

Input HIGH Current D2a–D

250 250 µAVIN = V

IH (Max)

D1a–D

350 350

Power Supply Current −69 −30 −69 −30 mA Inputs OPEN

Symbol Parameter

= 40°CT

= +25°CT

= +85°C

Units Conditions

Min Max Min Max Min Max

PLH

Propagation Delay

0.35 1.55 0.40 1.45 0.40 1.55

Figures 1, 2

PHL

Dna–Dne to O, O

PLH

Propagation Delay

1.00 2.40 1.00 2.40 1.15 3.00 ns

PHL

Data to F

TLH

Transition Time

0.35 1.10 0.35 1.15 0.35 1.10 ns

THL

20% to 80%, 80% to 20%

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100304

Test Circuitry

Notes:

, V

CCA

= +2V, VEE = −2.5V L1 and L2 = equal length 50Ω impedance lines R

= 50Ω terminator internal to scope

Decoupling 0.1 µF from GND to V

and V

All unused outputs are loaded with 50Ω to G ND C

= Fixture and stray capacitance ≤ 3 pF

FIGURE 1. AC Test Circuit

Switching Waveforms

FIGURE 2. Propagation Delay and Transition Times

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100304

Physical Dimensions inches (millimeters) unless otherwise noted

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide

Package Number N24E

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100304 Low Power Quint AND/NAND Gate

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

Package Number V28A

Fairchild does not assume any responsibility for use of any circuitr y described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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