5-TAP, HCMOS-INTERFACED
FIXED DELAY LINE
(SERIES SMD99C)
delay
devices, inc.
FEATURES PACKAGES
• Five equally spaced outputs
• Designed for surface mounting
• Low profile (0.175 maximum height)
• Input & outputs fully CMOS interfaced & buffered
• 10 T2L fan-out capability
T2
T4
GND
Commercial
SMD99C-xx
4
6
7
FUNCTIONAL DESCRIPTION
The SMD99C-series device is a 5-tap digitally buffered delay line. The
signal input (IN) is reproduced at the outputs (T1-T5), shifted in time by an
amount determined by the device dash number (See Table). The total
delay of the line is measured from IN to T5. The nominal tap-to-tap delay
increment is given by one-fifth of the total delay.
12
T1
10
T3
8
T5
PIN DESCRIPTIONS
IN Signal Input
T1-T5 Tap Outputs
VDD +5 Volts
GND Ground
IN
N/C
N/C
T2
N/C
T4
GND
SMD99C-xxMC2
1
2
3
4
5
6
7
Military
VCC
14
N/C
13
T1
12
N/C
11
T3
10
N/C
9
T5
8
SERIES SPECIFICATIONS
• Minimum input pulse width: 40% of total delay
• Output rise time: 8ns typical
• Supply voltage: 5VDC ± 5%
• Supply current: I
I
= 40µa typical
CCL
= 10ma typical
CCH
• Operating temperature: 0° to 70° C
• Temp. coefficient of total delay: 300 PPM/°C
20% 20% 20% 20% 20%
VDD GNDIN T1 T2 T3 T4 T5
DDU8C Functional diagram
DASH NUMBER SPECIFICATIONS
Part
Number
SMD99C-5050
SMD99C-5060
SMD99C-5075
SMD99C-5100
SMD99C-5125
SMD99C-5150
SMD99C-5175
SMD99C-5200
SMD99C-5250
NOTE: Any dash number between 5004 and 5250
not shown is also available.
Total
Delay (ns)
50 ± 2.5 10.0 ± 3.0
60 ± 3.0 12.0 ± 3.0
75 ± 4.0 15.0 ± 3.0
100 ± 5.0 20.0 ± 3.0
125 ± 6.5 25.0 ± 3.0
150 ± 7.5 30.0 ± 3.0
175 ± 8.0 35.0 ± 4.0
200 ± 10.0 40.0 ± 4.0
250 ± 12.5 50.0 ± 5.0
Delay Per
Tap (ns)
1997 Data Delay Devices
Doc #97018 DATA DELAY DEVICES, INC. 1
1/30/97 3 Mt. Prospect Ave. Clifton, NJ 07013
APPLICATION NOTES
HIGH FREQUENCY RESPONSE
The SMD99C tolerances are guaranteed for
input pulse widths and periods greater than those
specified in the test conditions. Although the
device will function properly for pulse widths as
small as 40% of the total delay and periods as
small as 80% of the total delay (for a symmetric
input), the delays may deviate from their values
at low frequency. However, for a given input
condition, the deviation will be repeatable from
pulse to pulse. Contact technical support at Data
DEVICE SPECIFICATIONS
TABLE 1: ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL MIN MAX UNITS NOTES
DC Supply Voltage V
Input Pin Voltage V
Storage Temperature T
Lead Temperature T
DD
IN
STRG
LEAD
Delay Devices if your application requires device
testing at a specific input condition.
POWER SUPPLY BYPASSING
The SMD99C relies on a stable power supply to
produce repeatable delays within the stated
tolerances. A 0.1uf capacitor from VDD to GND,
located as close as possible to the VDD pin, is
recommended. A wide VDD trace and a clean
ground plane should be used.
-0.3 7.0 V
-0.3 VDD+0.3 V
-55 150 C
300 C 10 sec
TABLE 2: DC ELECTRICAL CHARACTERISTICS
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
High Level Output Voltage V
Low Level Output Voltage V
High Level Output Current I
Low Level Output Current I
High Level Input Voltage V
Low Level Input Voltage V
Input Current I
(0C to 70C, 4.75V to 5.25V)
OH
OL
OH
OL
IH
IL
IH
3.98 4.4 V VDD = 5.0, IOH = MAX
0.15 0.26 V VDD = 5.0, IOL = MAX
3.15 V
-4.0 mA
4.0 mA
1.35 V
0.10
µA
VIH = MIN, VIL = MAX
VIH = MIN, VIL = MAX
VDD = 5.0
Doc #97018 DATA DELAY DEVICES, INC. 2
1/30/97 Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com