Datadelay PPG36F-9MC4, PPG36F-0.5, PPG36F-0.5C4, PPG36F-0.5M, PPG36F-0.5MC4 Datasheet
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PPG36F
Doc #97009 DATA DELAY DEVICES, INC. 1
1/15/97 3 Mt. Prospect Ave. Clifton, NJ 07013
6-BIT PROGRAMMABLE
PULSE GENERATOR
(SERIES PPG36F)
FEATURES PACKAGES
• Digitally programmable in 64 steps
• Monotonic pulse-width-vs-address variation
• Rising edge triggered
• Two separate outputs: inverting & non-inverting
• Precise and stable pulse width
• Input & outputs fully TTL interfaced & buffered
• 10 T2L fan-out capability
• Fits standard 24-pin DIP socket
• Auto-insertable
FUNCTIONAL DESCRIPTION
The PPG36F-series device is a 6-bit digitally programmable pulse
generator. The width, PWA, depends on the address code (A5-A0)
according to the following formula:
PWA = PW0 + T
INC
* A
where A is the address code, T
INC
is the incremental pulse width of the
device, and PW0 is the inherent pulse width of the device. The incremental
width is specified by the dash number of the device and can range from 0.5ns through 10ns, inclusively.
RESET is held LOW during normal operation. When it is brought HIGH, OUT and OUT/ are forced into
LOW and HIGH states, respectively, and the unit is ready for the next trigger input. The address is not
latched and must remain asserted while the output pulse is active.
SERIES SPECIFICATIONS
• Programmed pulse width tolerance: 5% or 2ns,
whichever is greater
• Inherent width (PW0): 12ns typical
• Inherent delay (TTO): 3.5ns ± 2ns
• Operating temperature: 0° to 70° C
• Supply voltage VCC: 5VDC ± 5%
• Supply current: ICC = 60ma typical
1997 Data Delay Devices
data
delay
devices,
inc.
3
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
TRIG
N/C
OUT
N/C
N/C
N/C
RES
N/C
N/C
N/C
N/C
GND
VCC
OUT/
N/C
N/C
N/C
A0
A1
A2
N/C
A3
A4
A5
PPG36F-xx DIP PPG36F-xxM Military DIP
PPG36F-xxC4 Gull-Wing PPG36F-xxMC4 Military Gull-Wing
PIN DESCRIPTIONS
TRIG Trigger Input
OUT Non-inverted Output
OUT/ Inverted Output
A0-A5 Address Bits
RES Reset
VCC +5 Volts
GND Ground
DASH NUMBER SPECIFICATIONS
Part
Number
Incremental Width
Per Step (ns)
Total Width
Change (ns)
PPG36F-.5
0.5 ± 0.3 31.5 ± 2.00
PPG36F-1
1 ± 0.5 63.0 ± 3.15
PPG36F-2
2 ± 0.5 126.0 ± 6.30
PPG36F-3
3 ± 1.0 189.0 ± 9.45
PPG36F-4
4 ± 1.0 252.0 ± 12.6
PPG36F-5
5 ± 1.5 315.0 ± 15.8
PPG36F-6
6 ± 1.5 378.0 ± 18.9
PPG36F-7
7 ± 1.5 441.0 ± 22.1
PPG36F-8
8 ± 2.0 504.0 ± 25.2
PPG36F-9
9 ± 2.0 567.0 ± 28.4
PPG36F-10
10 ± 2.0 630.0 ± 31.5
NOTE: Any dash number between .5 and 10 not
PPG36F
Doc #97009 DATA DELAY DEVICES, INC. 2
1/15/97 Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
APPLICATION NOTES
DEVICE TIMING
The timing definitions and restrictions for the
PPG36F are shown in Figure 1. The unit is
activated by a rising edge on the TRIG input.
After a time, TTO (called the inherent delay), the
rising edge of the pulse appears at OUT. The
duration of the pulse is given by the above
equation. For the duration of the pulse, the
device ignores subsequent triggers. Once the
falling edge of the pulse has appeared at OUT,
an additional time, T
OTR
, is required before the
device can respond to the next trigger.
At power-up, the state of the PPG36F is
unknown. Consequently, after power is applied,
the unit may not respond to input triggers for a
time equal to the maximum pulse width, PWT.
After this time, the unit will function properly. If
your application requires that the device function
immediately, issue a quick reset at power-up.
POWER SUPPLY BYPASSING
The PPG36F relies on a stable power supply to
produce repeatable pulses within the stated
tolerances. A 0.1uf capacitor from VCC to GND,
located as close as possible to each VCC pin, is
recommended. A wide VCC trace should
connect all VCC pins externally, and a clean
ground plane should be used.
INCREMENT TOLERANCES
Please note that the increment tolerances listed
represent a design goal. Although most
increments will fall within tolerance, they are not
guaranteed throughout the address range of the
unit. Monotonicity is, however, guaranteed over
all addresses.
`
T
OAX
T
RTS
T
TW
T
TO
PW
A
A5-A0
RES
TRIG
OUT
OUT/
Figure 1: Timing Diagram
A
i
A
i+1
T
SKEW
T
ATS
T
RO
T
OTR
T
TW
T
RW
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