PDU53
3-BIT, ECL-INTERFACED
data
3
1
16
N/C
N/C
IN
PROGRAMMABLE DELAY LINE
(SERIES PDU53)
delay
devices, inc.
FEATURES PACKAGES
N/C
• Digitally programmable in 8 delay steps
• Monotonic delay-versus-address variation
• Precise and stable delays
• Input & outputs fully 100K-ECL interfaced & buffered
• Available in 16-pin DIP (600 mil) socket or SMD
N/C
GND
OUT
N/C
N/C
N/C
N/C
1
2
3
4
5
6
7
8
PDU53-xx DIP
PDU53-xxM Military DIP
FUNCTIONAL DESCRIPTION
The PDU53-series device is a 3-bit digitally programmable delay line.
The delay, TDA, from the input pin (IN) to the output pin (OUT) depends
on the address code (A2-A0) according to the following formula:
TDA = TD0 + T
where A is the address code, T
and TD0 is the inherent delay of the device. The incremental delay is
specified by the dash number of the device and can range from 100ps through 3000ps, inclusively. The
address is not latched and must remain asserted during normal operation.
INC
* A
is the incremental delay of the device,
INC
16
IN
15
A2
A1
VEE
A0
N/C
N/C
N/C
GND
OUT
14
13
12
11
10
9
N/C
N/C
N/C
N/C
2
3
4
5
6
7
8
PDU53-xxC3 SMD
PDU53-xxMC3 Mil SMD
PIN DESCRIPTIONS
IN Signal Input
OUT Signal Output
A2 Address Bit 2
A1 Address Bit 1
A0 Address Bit 0
VEE -5 Volts
GND Ground
15
14
13
12
11
10
9
A2
A1
VEE
A0
N/C
N/C
N/C
SERIES SPECIFICATIONS
• Total programmed delay tolerance: 5% or 40ps,
whichever is greater
• Inherent delay (TD0): 2.2ns typical
• Address to input setup (T
• Operating temperature: 0° to 85° C
• Temperature coefficient: 100PPM/°C (excludes TD0)
• Supply voltage VEE: -5VDC ± 0.7V
• Power Supply Current: -150ma typical (50Ω to -2V)
• Minimum pulse width: 3ns or 15% of total delay,
• Minimum period: 8ns or 2 x pulse width, whichever
A2-A0
IN
OUT
1997 Data Delay Devices
TD
A
i-1
PW
IN
PW
A
Figure 1: Timing Diagram
T
OUT
): 2.9ns
AIS
whichever is greater
is greater
OAX
T
AIS
A
i
DASH NUMBER SPECIFICATIONS
Part
Number
PDU53-100
PDU53-200
PDU53-250
PDU53-400
PDU53-500
PDU53-750
PDU53-1000
PDU53-1200
PDU53-1500
PDU53-2000
PDU53-2500
PDU53-3000
NOTE: Any dash number between 100 and 3000
Incremental Delay
Per Step (ps)
100 ± 50
200 ± 60
250 ± 60
400 ± 80
500 ± 100
750 ± 100
1000 ± 200
1200 ± 200
1500 ± 200
2000 ± 400
2500 ± 400
3000 ± 500
not shown is also available.
Total Delay
Change (ns)
0.70
1.40
1.75
2.80
3.50
5.25
7.00
8.40
10.50
14.00
17.50
21.00
Doc #98003 DATA DELAY DEVICES, INC. 1
3/18/98 3 Mt. Prospect Ave. Clifton, NJ 07013
PDU53
APPLICATION NOTES
.870±.010
.015 TYP.
.070 MAX.
ADDRESS UPDATE
The PDU53 is a memory device. As such,
special precautions must be taken when
changing the delay address in order to prevent
spurious output signals. The timing restrictions
are shown in Figure 1.
After the last signal edge to be delayed has
appeared on the OUT pin, a minimum time,
T
, is required before the address lines can
OAX
change. This time is given by the following
relation:
T
where A
= max { (Ai - A
OAX
and Ai are the old and new address
i-1
i-1
) * T
INC
, 0 }
codes, respectively. Violation of this constraint
may, depending on the history of the input signal,
cause spurious signals to appear on the OUT
pin. The possibility of spurious signals persists
until the required T
has elapsed.
OAX
INPUT RESTRICTIONS
There are three types of restrictions on input
pulse width and period listed in the AC
Characteristics table. The recommended
conditions are those for which the delay
tolerance specifications and monotonicity are
guaranteed. The suggested conditions are
those for which signals will propagate through the
unit without significant distortion. The absolute
conditions are those for which the unit will
produce some type of output for a given input.
When operating the unit between the
recommended and absolute conditions, the
delays may deviate from their values at low
frequency. However, these deviations will
remain constant from pulse to pulse if the input
pulse width and period remain fixed. In other
words, the delay of the unit exhibits frequency
and pulse width dependence when operated
beyond the recommended conditions. Please
consult the technical staff at Data Delay Devices
if your application has specific high-frequency
requirements.
Please note that the increment tolerances listed
represent a design goal. Although most delay
increments will fall within tolerance, they are not
guaranteed throughout the address range of the
unit. Monotonicity is, however, guaranteed over
all addresses.
PACKAGE DIMENSIONS
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
.018
TYP.
.700±.010
7 Equal spaces
each .100±.010
Non-Accumulative
PDU53-xx (Commercial DIP)
PDU53-xxM (Military DIP)
.580
MAX.
.380
MAX.
.600
±.005
.010
±.002
Lead Material:
Nickel-Iron alloy 42
TIN PLATE
Doc #98003 DATA DELAY DEVICES, INC. 2
3/18/98 Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
PDU53
PACKAGE DIMENSIONS (cont’d)
.880±.020
.020 TYP.
.100
.090
.700
.010±.002
.040
TYP.
910111213141516
1 2 3 4 5 6 7 8
PDU53-xxC3 (Commercial SMD)
PDU53-xxMC3 (Military SMD)
DEVICE SPECIFICATIONS
TABLE 1: AC CHARACTERISTICS
PARAMETER SYMBOL MIN TYP UNITS
Total Programmable Delay TD
Inherent Delay TD
Address to Input Setup Time T
Output to Address Change T
Absolute PER
Input Period Suggested PER
Recommended PER
Absolute PW
Input Pulse Width Suggested PW
Recommended PW
AIS
OAX
.710
±.005
T
0
IN
IN
IN
IN
IN
IN
.590
MAX.
.280
MAX.
.882
±.005
.007
±.005
.050
±.010
7 T
2.2 ns
2.9 ns
See Text
30 % of TD
50 % of TD
200 % of TD
15 % of TD
25 % of TD
100 % of TD
INC
T
T
T
T
T
T
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL MIN MAX UNITS NOTES
DC Supply Voltage V
Input Pin Voltage V
Storage Temperature T
Lead Temperature T
EE
IN
STRG
LEAD
-7.0 0.3 V
VEE - 0.3 0.3 V
-65 150 C
300 C 10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(0C to 85C)
PARAMETER SYMBOL MIN MAX UNITS NOTES
High Level Output Voltage V
Low Level Output Voltage V
High Level Input Voltage V
Low Level Input Voltage V
High Level Input Current I
Low Level Input Current I
OH
OL
IH
IL
IH
IL
-1.025 -0.880 V
-1.810 -1.620 V
-1.165 -0.880 V
-1.810 -1.475 V
340
0.5
µA
µA
VIH = MAX,50Ω to -2V
VIL = MIN, 50Ω to -2V
VIH = MAX
VIL = MIN
Doc #98003 DATA DELAY DEVICES, INC. 3
3/18/98 3 Mt. Prospect Ave. Clifton, NJ 07013
PDU53
DELAY LINE AUTOMATED TESTING
OUT
OUT
TRIGINREF
TRIG
OSCILLOSCOPE
IN
ADDRESS SELECT
20%
20%
50%
50%
80%
80%
50%
50%
TEST CONDITIONS
INPUT: OUTPUT:
Ambient Temperature: 25oC ± 3oC Load: 50Ω to -2V
Supply Voltage (Vcc): -4.5V ± 0.1V C
Input Pulse: Standard 100K ECL Threshold: (VOH + VOL) / 2
levels (Rising & Falling)
Source Impedance: 50Ω Max.
Rise/Fall Time: 1.0 ns Max. (measured
between 20% and 80%)
Pulse Width: PWIN = 10ns
Period: PERIN = 100ns
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
: 5pf ± 10%
load
PULSE
GENERATOR
INPUT
SIGNAL
T
RISE
T
RISE
DEVICE UNDER
TEST (DUT)
Test Setup
PW
IN
V
IH
PER
IN
T
FALL
V
IL
T
FALL
Doc #98003 DATA DELAY DEVICES, INC. 4
3/18/98 Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
OUTPUT
SIGNAL
V
OH
Timing Diagram For Testing
V
OL
Loading...