Datadelay PDU10256H-4M, PDU10256H-4MC5, PDU10256H-5, PDU10256H-5C5, PDU10256H-5M Datasheet

PDU10256H

Doc #97047 DATA DELAY DEVICES, INC. 1

12/17/97 3 Mt. Prospect Ave. Clifton, NJ 07013

8-BIT, ECL-INTERFACED
PROGRAMMABLE DELAY LINE
(SERIES PDU10256H)

FEATURES PACKAGES

• Digitally programmable in 128 delay steps

• Monotonic delay-versus-address variation

• Precise and stable delays

• Input & outputs fully 10KH-ECL interfaced & buffered

• Fits 48-pin DIP socket

PIN DESCRIPTIONS

IN Signal Input
OUT Signal Output
A0-A7 Address Bits
ENB Output Enable
VEE -5 Volts
GND Ground

FUNCTIONAL DESCRIPTION

The PDU10256H-series device is an 8-bit digitally programmable delay line. The delay, TDA, from the
input pin (IN) to the output pin (OUT) depends on the address code (A7-A0) according to the following
formula:

TDA = TD0 + T

INC

* A

where A is the address code, T

INC

is the incremental delay of the device, and TD0 is the inherent delay of

the device. The incremental delay is specified by the dash number of the device and can range from

0.5ns through 10ns, inclusively. The enable pin (ENB) is held LOW during normal operation. When this
signal is brought HIGH, OUT is forced into a LOW state. The address is not latched and must remain
asserted during normal operation.

SERIES SPECIFICATIONS

• Total programmed delay tolerance: 5% or 2ns,
whichever is greater

Inherent delay (TD0): 12ns typical

• Setup time and propagation delay:

Address to input setup (T

AIS

): 3.6ns

Disable to output delay (T

DISO

): 1.7ns typical

• Operating temperature: 0° to 70° C

• Temperature coefficient: 100PPM/°C (excludes TD0)

• Supply voltage VEE: -5VDC ± 5%

• Power Dissipation: 925mw typical (no load)

• Minimum pulse width: 16% of total delay

1997 Data Delay Devices

data

delay
devices, inc.



3

1

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

40

39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

N/C

N/C

OUT

GND

ENB

N/C
N/C
N/C

GND

ENB

N/C
N/C
N/C
N/C
N/C
N/C
N/C

GND

ENB

IN

N/C

N/C
A2
A1
VEE
A0
N/C
A5
A4
VEE
A3
N/C
N/C
N/C
N/C
N/C
N/C
A7
VEE
A6

GND

IN

A6

VEE

GND

ENB

A0

VEE

48
47

42
41

1
2

7
8

GND
OUT

A1
A2

GND

A3

VEE

40

34
33

9

15
16

GND

A4
A5

32

25

17

19

23
24

GND

A7

PDU10256H-xxC5 SMD
PDU10256H-xxMC5 Mil SMD

PDU10256H-xx DIP
PDU10256H-xxM Mil DIP

DASH NUMBER SPECIFICATIONS

Part

Number

Incremental Delay

Per Step (ns)

Total

Delay (ns)

PDU10256H-.5

0.5 ± 0.3 127.5 ± 6.4

PDU10256H-1

1.0 ± 0.5 255 ± 12.8

PDU10256H-2

2.0 ± 0.5 510 ± 25.5

PDU10256H-3

3.0 ± 1.0 765 ± 38.2

PDU10256H-4

4.0 ± 1.0 1020 ± 51.0

PDU10256H-5

5.0 ± 1.5 1275 ± 63.8

PDU10256H-6

6.0 ± 1.5 1530 ± 76.5

PDU10256H-8

8.0 ± 2.0 2040 ± 102

PDU10256H-10

10.0 ± 2.0 2550 ± 128

NOTE: Any dash number between .5 and 10

not shown is also available.

PDU10256H

Doc #97047 DATA DELAY DEVICES, INC. 2

12/17/97 Tel: [phone] Fax: [phone] http://www.datadelay.com

APPLICATION NOTES

ADDRESS UPDATE

The PDU10256H is a memory device. As such,
special precautions must be taken when
changing the delay address in order to prevent
spurious output signals. The timing restrictions
are shown in Figure 1.

After the last signal edge to be delayed has
appeared on the OUT pin, a minimum time,
T

OAX

, is required before the address lines can
change. This time is given by the following
relation:

T

OAX

= max { (Ai - A

i-1

) * T

INC

, 0 }

where A

i-1

and Ai are the old and new address
codes, respectively. Violation of this constraint
may, depending on the history of the input signal,
cause spurious signals to appear on the OUT
pin. The possibility of spurious signals persists
until the required T

OAX

has elapsed.

A similar situation occurs when using the ENB
signal to disable the output while IN is active. In
this case, the unit must be held in the disabled
state until the device is able to “clear” itself. This
is achieved by holding the ENB signal high and
the IN signal low for a time given by:

T

DISH

= Ai * T

INC

Violation of this constraint may, depending on
the history of the input signal, cause spurious
signals to appear on the OUT pin. The

possibility of spurious signals persists until the
required T

DISH

has elapsed.

INPUT RESTRICTIONS

There are three types of restrictions on input
pulse width and period listed in the AC
Characteristics table. The recommended
conditions are those for which the delay
tolerance specifications and monotonicity are
guaranteed. The suggested conditions are
those for which signals will propagate through the
unit without significant distortion. The absolute
conditions are those for which the unit will
produce some type of output for a given input.

When operating the unit between the
recommended and absolute conditions, the
delays may deviate from their values at low
frequency. However, these deviations will
remain constant from pulse to pulse if the input
pulse width and period remain fixed. In other
words, the delay of the unit exhibits frequency
and pulse width dependence when operated
beyond the recommended conditions. Please
consult the technical staff at Data Delay Devices
if your application has specific high-frequency
requirements.

Please note that the increment tolerances listed
represent a design goal. Although most delay
increments will fall within tolerance, they are not
guaranteed throughout the address range of the
unit. Monotonicity is, however, guaranteed over
all addresses.

T

DISO

T

OAX

T

AENS

T

ENIS

PW

IN

TD

A

PW

OUT

T

DISH

A7-A0

ENB

IN

OUT

Figure 1: Timing Diagram

A

i-1

A

i

T

AIS

PDU10256H

Doc #97047 DATA DELAY DEVICES, INC. 3

12/17/97 3 Mt. Prospect Ave. Clifton, NJ 07013

DEVICE SPECIFICATIONS

TABLE 1: AC CHARACTERISTICS

PARAMETER SYMBOL MIN TYP UNITS

Total Programmable Delay TD

T

127 T

INC

Inherent Delay TD

0

12.0 ns

Disable to Output Low Delay T

DISO

1.7 ns

Address to Enable Setup Time T

AENS

1.0 ns

Address to Input Setup Time T

AIS

3.6 ns

Enable to Input Setup Time T

ENIS

3.6 ns

Output to Address Change T

OAX

See Text

Disable Hold Time T

DISH

See Text

Absolute PER

IN

12 % of TD

T

Input Period Suggested PER

IN

32 % of TD

T

Recommended PER

IN

200 % of TD

T

Absolute PW

IN

6 % of TD

T

Input Pulse Width Suggested PW

IN

16 % of TD

T

Recommended PW

IN

100 % of TD

T

TABLE 2: ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL MIN MAX UNITS NOTES

DC Supply Voltage V

EE

-7.0 0.3 V

Input Pin Voltage V

IN

VEE - 0.3 0.3 V

Storage Temperature T

STRG

-55 150 C

Lead Temperature T

LEAD

300 C 10 sec

TABLE 3: DC ELECTRICAL CHARACTERISTICS

(0C to 75C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

High Level Output Voltage V

OH

-1.020 -0.735 V

VIH = MAX,50Ω to -2V

Low Level Output Voltage V

OL

-1.950 -1.600 V

VIL = MIN, 50Ω to -2V

High Level Input Voltage V

IH

-1.070 V

Low Level Input Voltage V

IL

-1.480 V

High Level Input Current I

IH

475

µA

VIH = MAX

Low Level Input Current I

IL

0.5

µA

VIL = MIN

PDU10256H

Doc #97047 DATA DELAY DEVICES, INC. 4

12/17/97 Tel: [phone] Fax: [phone] http://www.datadelay.com

PACKAGE DIMENSIONS

PDU10256H-xx (Commercial DIP)
PDU10256H-xxM (Military DIP)

.150

±.030

2.450 TYP.

2415

.320

MAX.

.018
TYP.

.400
TYP.

.300
TYP.

.012 TYP.

.020

TYP.

40 3334 32 25

7 82

48 4142

1

47

9 1916 17 23

.600

.100

.700

.800

1.400

1.600

2.200

.075

1.500

1.800

2.300

PDU10256H-xxC5 (Commercial SMD)
PDU10256H-xxMC5 (Military SMD)

2.080±.020

.882

±.005

.020 TYP.

.040 TYP.

.100

.090

1.100

.280
MAX.

.590

MAX.

.010±.002

.050

±.010

.710

±.005

.007

±.005

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

2122232425262728293031323334353637383940

PDU10256H

Doc #97047 DATA DELAY DEVICES, INC. 5

12/17/97 3 Mt. Prospect Ave. Clifton, NJ 07013

DELAY LINE AUTOMATED TESTING

TEST CONDITIONS

INPUT: OUTPUT:
Ambient Temperature: 25oC ± 3oC Load: 50Ω to -2V
Supply Voltage (Vcc): -5.0V ± 0.1V C

load

: 5pf ± 10%

Input Pulse: Standard 10KH ECL Threshold: (VOH + VOL) / 2

levels (Rising & Falling)

Source Impedance: 50Ω Max.
Rise/Fall Time: 2.0 ns Max. (measured

between 20% and 80%)

Pulse Width: PWIN = 1.5 x Total Delay
Period: PERIN = 10 x Total Delay

NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.

OUT

OUT

TRIGINREF

TRIG

Test Setup

DEVICE UNDER

TEST (DUT)

OSCILLOSCOPE

PULSE

GENERATOR

IN

ADDRESS SELECT

Timing Diagram For Testing

T

RISE

T

FALL

PER

IN

PW

IN

T

RISE

T

FALL

20%

20%

50%

50%

80%

80%

50%

50%

V

IH

V

IL

V

OH

V

OL

INPUT
SIGNAL

OUTPUT
SIGNAL