Datadelay PDU10256H-4M, PDU10256H-4MC5, PDU10256H-5, PDU10256H-5C5, PDU10256H-5M, PDU10256H-5MC5, PDU10256H-6, PDU10256H-6C5, PDU10256H-6M, PDU10256H-6MC5, PDU10256H-1MC5, PDU10256H-2, PDU10256H-2M, PDU10256H-2MC5, PDU10256H-3, PDU10256H-3C5, PDU10256H-3M, PDU10256H-3MC5, PDU10256H-4, PDU10256H-4C5, PDU10256H-0.5C5, PDU10256H-0.5M, PDU10256H-0.5MC5, PDU10256H-1, PDU10256H-10, PDU10256H-10C5, PDU10256H-10M, PDU10256H-10MC5, PDU10256H-1C5, PDU10256H-1M, PDU10256H-8, PDU10256H-8C5, PDU10256H-8M, PDU10256H-8MC5 Datasheet

PDU10256H

8-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU10256H)

data 3 ® delay

devices, inc.

FEATURES

∙Digitally programmable in 128 delay steps

∙Monotonic delay-versus-address variation

∙Precise and stable delays

∙Input & outputs fully 10KH-ECL interfaced & buffered

∙Fits 48-pin DIP socket

PIN DESCRIPTIONS

IN	Signal Input
OUT	Signal Output
A0-A7	Address Bits
ENB	Output Enable
VEE	-5 Volts
GND	Ground

PACKAGES

GND		1	48		GND	N/C	1	40	N/C
						N/C	2	39	N/C
ENB		2	47		OUT
						OUT	3	38	A2
						GND	4	37	A1
						ENB	5	36	VEE
						N/C	6	35	A0
						N/C	7	34	N/C
A0		7	42		A1	N/C	8	33	A5
						GND	9	32	A4
VEE		8	41		A2	ENB	10	31	VEE
GND		9	40		GND	N/C	11	30	A3
						N/C	12	29	N/C
						N/C	13	28	N/C
						N/C	14	27	N/C
						N/C	15	26	N/C
						N/C	16	25	N/C
						N/C	17	24	N/C
A3		15	34		A4	GND	18	23	A7
						ENB	19	22	VEE
VEE		16	33		A5	IN	20	21	A6
GND		17	32		GND	PDU10256H-xxC5		SMD
IN		19				PDU10256H-xxMC5 Mil SMD
A6		23				PDU10256H-xx	DIP
						PDU10256H-xxM Mil DIP
VEE		24	25		A7

FUNCTIONAL DESCRIPTION

The PDU10256H-series device is an 8-bit digitally programmable delay line. The delay, TDA, from the input pin (IN) to the output pin (OUT) depends on the address code (A7-A0) according to the following formula:

TDA = TD0 + TINC * A

where A is the address code, TINC is the incremental delay of the device, and TD0 is the inherent delay of the device. The incremental delay is specified by the dash number of the device and can range from 0.5ns through 10ns, inclusively. The enable pin (ENB) is held LOW during normal operation. When this signal is brought HIGH, OUT is forced into a LOW state. The address is not latched and must remain asserted during normal operation.

SERIES SPECIFICATIONS

∙Total programmed delay tolerance: 5% or 2ns,

whichever is greater

Inherent delay (TD0): 12ns typical

∙Setup time and propagation delay: Address to input setup (TAIS): 3.6ns

Disable to output delay (TDISO): 1.7ns typical

∙Operating temperature: 0° to 70° C

∙Temperature coefficient: 100PPM/°C (excludes TD0)

∙Supply voltage VEE: -5VDC ± 5%

∙Power Dissipation: 925mw typical (no load)

∙Minimum pulse width: 16% of total delay

©1997 Data Delay Devices

DASH NUMBER SPECIFICATIONS

Part	Incremental Delay	Total
Number	Per Step (ns)	Delay (ns)
PDU10256H-.5	0.5 ± 0.3	127.5 ± 6.4
PDU10256H-1	1.0 ± 0.5	255 ± 12.8
PDU10256H-2	2.0 ± 0.5	510 ± 25.5
PDU10256H-3	3.0 ± 1.0	765 ± 38.2
PDU10256H-4	4.0 ± 1.0	1020 ± 51.0
PDU10256H-5	5.0 ± 1.5	1275 ± 63.8
PDU10256H-6	6.0 ± 1.5	1530 ± 76.5
PDU10256H-8	8.0 ± 2.0	2040 ± 102
PDU10256H-10	10.0 ± 2.0	2550 ± 128

NOTE: Any dash number between .5 and 10 not shown is also available.

Doc #97047

DATA DELAY DEVICES, INC.

1

12/17/97

3 Mt. Prospect Ave. Clifton, NJ 07013

PDU10256H

APPLICATION NOTES

ADDRESS UPDATE

The PDU10256H is a memory device. As such, special precautions must be taken when changing the delay address in order to prevent spurious output signals. The timing restrictions are shown in Figure 1.

After the last signal edge to be delayed has appeared on the OUT pin, a minimum time, TOAX, is required before the address lines can change. This time is given by the following relation:

TOAX = max { (Ai - A i-1) * TINC , 0 }

where A i-1 and Ai are the old and new address codes, respectively. Violation of this constraint may, depending on the history of the input signal, cause spurious signals to appear on the OUT pin. The possibility of spurious signals persists until the required TOAX has elapsed.

A similar situation occurs when using the ENB signal to disable the output while IN is active. In this case, the unit must be held in the disabled state until the device is able to “clear” itself. This is achieved by holding the ENB signal high and the IN signal low for a time given by:

TDISH = Ai * TINC

Violation of this constraint may, depending on the history of the input signal, cause spurious signals to appear on the OUT pin. The

possibility of spurious signals persists until the required TDISH has elapsed.

INPUT RESTRICTIONS

There are three types of restrictions on input pulse width and period listed in the AC Characteristics table. The recommended conditions are those for which the delay tolerance specifications and monotonicity are guaranteed. The suggested conditions are those for which signals will propagate through the unit without significant distortion. The absolute conditions are those for which the unit will produce some type of output for a given input.

When operating the unit between the recommended and absolute conditions, the delays may deviate from their values at low frequency. However, these deviations will remain constant from pulse to pulse if the input pulse width and period remain fixed. In other words, the delay of the unit exhibits frequency and pulse width dependence when operated beyond the recommended conditions. Please consult the technical staff at Data Delay Devices if your application has specific high-frequency requirements.

Please note that the increment tolerances listed represent a design goal. Although most delay increments will fall within tolerance, they are not guaranteed throughout the address range of the unit. Monotonicity is, however, guaranteed over all addresses.

A7-A0	A i-1	Ai
TAENS	TOAX	TAIS
ENB
TENIS	PWIN	TDISH
IN
TDA	PWOUT	TDISO
OUT
	Figure 1: Timing Diagram

Doc #97047

DATA DELAY DEVICES, INC.

2

12/17/97

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