Datadelay PDU1016H-0.5, PDU1016H-0.5C4, PDU1016H-10M, PDU1016H-10MC4, PDU1016H-15 Datasheet
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PDU1016H
Doc #97044 DATA DELAY DEVICES, INC. 1
11/1/01 3 Mt. Prospect Ave. Clifton, NJ 07013
4-BIT, ECL-INTERFACED
PROGRAMMABLE DELAY LINE
(SERIES PDU1016H)
FEATURES PACKAGES
• Digitally programmable in 16 delay steps
• Monotonic delay-versus-address variation
• Precise and stable delays
• Input & outputs fully 10KH-ECL interfaced & buffered
• Fits 32-pin DIP socket
FUNCTIONAL DESCRIPTION
The PDU1016H-series device is a 4-bit digitally programmable delay line.
The delay, TDA, from the input pin (IN) to the output pin (OUT) depends on
the address code (A3-A0) according to the following formula:
TDA = TD0 + T
INC
* A
where A is the address code, T
INC
is the incremental delay of the device,
and TD0 is the inherent delay of the device. The incremental delay is specified by the dash number of the
device and can range from 0.5ns through 100ns, inclusively. The enable pin (ENB) is held LOW during
normal operation. When this signal is brought HIGH, OUT is forced into a LOW state. The address is not
latched and must remain asserted during normal operation.
SERIES SPECIFICATIONS
• Total programmed delay tolerance: 5% or 1ns,
whichever is greater
• Inherent delay (TD0): 5.5ns typical for dash numbers
up to 5, greater for larger #’s
• Setup time and propagation delay:
Address to input setup (T
AIS
): 3.6ns
Disable to output delay (T
DISO
): 1.7ns typical
• Operating temperature: 0° to 70° C
• Temperature coefficient: 100PPM/°C (excludes TD0)
• Supply voltage VEE: -5VDC ± 5%
• Power Dissipation: 615mw typical (no load)
• Minimum pulse width: 20% of total delay
2001 Data Delay Devices
data
delay
devices,
inc.
3
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
N/C
N/C
OUT
GND
ENB
N/C
N/C
N/C
GND
ENB
N/C
IN
N/C
A2
A1
VEE
A0
N/C
N/C
N/C
VEE
A3
N/C
N/C
32
31
26
25
24
1
2
7
8
9
11
15
16
GND
ENB
A0
VEE
GND
IN
A3
VEE
GND
OUT
A1
A2
GND
PDU1016H-xxC4 SMD
PDU1016H-xxMC4 Mil SMD
PDU1016H-xx DIP
PDU1016H-xxM Mil DIP
PIN DESCRIPTIONS
IN Signal Input
OUT Signal Output
A0-A3 Address Bits
ENB Output Enable
VEE -5 Volts
GND Ground
DASH NUMBER SPECIFICATIONS
Part
Number
Incremental Delay
Per Step (ns)
Total
Delay (ns)
PDU1016H-.5
0.5 ± 0.3 7.5 ± 1.0
PDU1016H-1
1.0 ± 0.5 15 ± 1.0
PDU1016H-2
2.0 ± 0.5 30 ± 1.5
PDU1016H-3
3.0 ± 1.0 45 ± 2.2
PDU1016H-4
4.0 ± 1.0 60 ± 3.0
PDU1016H-5
5.0 ± 1.0 75 ± 3.7
PDU1016H-6
6.0 ± 1.0 90 ± 4.5
PDU1016H-8
8.0 ± 1.0 120 ± 6.0
PDU1016H-10
10.0 ± 1.5 150 ± 7.5
PDU1016H-15
15.0 ± 1.5 225 ± 11.2
PDU1016H-20
20.0 ± 2.0 300 ± 15.0
PDU1016H-25
25.0 ± 2.5 375 ± 18.8
PDU1016H-30
30.0 ± 3.0 450 ± 22.5
PDU1016H-40
40.0 ± 4.0 600 ± 30.0
PDU1016H-50
50.0 ± 5.0 750 ± 37.5
PDU1016H-60
60.0 ± 6.0 900 ± 45.0
PDU1016H-80
80.0 ± 8.0 1200 ± 60.0
PDU1016H-100
100.0 ± 10.0 1500 ± 75.0
NOTE: Any dash number between .5 and 100
not shown is also available.
PDU1016H
Doc #97044 DATA DELAY DEVICES, INC. 2
11/1/01 Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
APPLICATION NOTES
ADDRESS UPDATE
The PDU1016H is a memory device. As such,
special precautions must be taken when
changing the delay address in order to prevent
spurious output signals. The timing restrictions
are shown in Figure 1.
After the last signal edge to be delayed has
appeared on the OUT pin, a minimum time, T
OAX
,
is required before the address lines can change.
This time is given by the following relation:
T
OAX
= max { (Ai - A
i-1
) * T
INC
, 0 }
where A
i-1
and Ai are the old and new address
codes, respectively. Violation of this constraint
may, depending on the history of the input signal,
cause spurious signals to appear on the OUT pin.
The possibility of spurious signals persists until
the required T
OAX
has elapsed.
A similar situation occurs when using the ENB
signal to disable the output while IN is active. In
this case, the unit must be held in the disabled
state until the device is able to “clear” itself. This
is achieved by holding the ENB signal high and
the IN signal low for a time given by:
T
DISH
= Ai * T
INC
Violation of this constraint may, depending on the
history of the input signal, cause spurious signals
to appear on the OUT pin. The possibility of
spurious signals persists until the required T
DISH
has elapsed.
INPUT RESTRICTIONS
There are three types of restrictions on input
pulse width and period listed in the AC
Characteristics table. The recommended
conditions are those for which the delay tolerance
specifications and monotonicity are guaranteed.
The suggested conditions are those for which
signals will propagate through the unit without
significant distortion. The absolute conditions
are those for which the unit will produce some
type of output for a given input.
When operating the unit between the
recommended and absolute conditions, the
delays may deviate from their values at low
frequency. However, these deviations will remain
constant from pulse to pulse if the input pulse
width and period remain fixed. In other words,
the delay of the unit exhibits frequency and pulse
width dependence when operated beyond the
recommended conditions. Please consult the
technical staff at Data Delay Devices if your
application has specific high-frequency
requirements.
Please note that the increment tolerances listed
represent a design goal. Although most delay
increments will fall within tolerance, they are not
guaranteed throughout the address range of the
unit. Monotonicity is, however, guaranteed over
all addresses.
T
DISO
T
OAX
T
AENS
T
ENIS
PW
IN
TD
A
PW
OUT
T
DISH
A3-A0
ENB
IN
OUT
Figure 1: Timing Diagram
A
i-1
A
i
T
AIS
PDU1016H
Doc #97044 DATA DELAY DEVICES, INC. 3
11/1/01 3 Mt. Prospect Ave. Clifton, NJ 07013
DEVICE SPECIFICATIONS
TABLE 1: AC CHARACTERISTICS
PARAMETER SYMBOL MIN TYP UNITS
Total Programmable Delay TD
T
15 T
INC
Inherent Delay TD
0
5.5 ns*
Disable to Output Low Delay T
DISO
1.7 ns
Address to Enable Setup Time T
AENS
1.0 ns
Address to Input Setup Time T
AIS
3.6 ns
Enable to Input Setup Time T
ENIS
3.6 ns
Output to Address Change T
OAX
See Text
Disable Hold Time T
DISH
See Text
Absolute PER
IN
16 % of TD
T
Input Period Suggested PER
IN
40 % of TD
T
Recommended PER
IN
200 % of TD
T
Absolute PW
IN
8 % of TD
T
Input Pulse Width Suggested PW
IN
20 % of TD
T
Recommended PW
IN
100 % of TD
T
* Greater for dash numbers larger than 5
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL MIN MAX UNITS NOTES
DC Supply Voltage V
EE
-7.0 0.3 V
Input Pin Voltage V
IN
VEE - 0.3 0.3 V
Storage Temperature T
STRG
-55 150 C
Lead Temperature T
LEAD
300 C 10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(0C to 75C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
High Level Output Voltage V
OH
-1.020 -0.735 V
VIH = MAX,50Ω to -2V
Low Level Output Voltage V
OL
-1.950 -1.600 V
VIL = MIN, 50Ω to -2V
High Level Input Voltage V
IH
-1.070 V
Low Level Input Voltage V
IL
-1.480 V
High Level Input Current I
IH
475
µA
VIH = MAX
Low Level Input Current I
IL
0.5
µA
VIL = MIN
PDU1016H
Doc #97044 DATA DELAY DEVICES, INC. 4
11/1/01 Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
PACKAGE DIMENSIONS
PDU1016H-xx (Commercial DIP)
PDU1016H-xxM (Military DIP)
.150
±
.030
1.650 TYP.
1 2 7 8 1615119
.320
MAX.
.018
TYP.
.400
TYP.
.300
TYP.
.012 TYP.
.020
TYP.
3132 2526 24
.100
.600
.700
.800
1.000
1.400
1.500
.075
PDU1016H-xxC4 (Commercial SMD)
PDU1016H-xxMC4 (Military SMD)
1.280±.020
.882
±
.00
.020 TYP.
.040 TYP.
.100
.090
1.100
.320
MAX.
.590
MAX.
.010±.002
.050
±.01
.710
±
.00
.007
±.00
1 2 3 4 5 6 7 8 9 10 11 12
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PDU1016H
Doc #97044 DATA DELAY DEVICES, INC. 5
11/1/01 3 Mt. Prospect Ave. Clifton, NJ 07013
DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT: OUTPUT:
Ambient Temperature: 25oC ± 3oC Load: 50Ω to -2V
Supply Voltage (Vcc): -5.0V ± 0.1V C
load
: 5pf ± 10%
Input Pulse: Standard 10KH ECL Threshold: (VOH + VOL) / 2
levels (Rising & Falling)
Source Impedance: 50Ω Max.
Rise/Fall Time: 2.0 ns Max. (measured
between 20% and 80%)
Pulse Width: PWIN = 1.5 x Total Delay
Period: PERIN = 10 x Total Delay
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
OUTOUT
TRIG
IN
REF
TRIG
Test Setup
DEVICE UNDER
TEST (DUT)
OSCILLOSCOPE
PULSE
GENERATOR
IN
ADDRESS SELECT
Timing Diagram For Testing
D
RISE
D
FALL
PER
IN
PW
IN
T
RISE
T
FALL
20%
20%
50%
50%
80%
80%
50%
50%
V
IH
V
IL
V
OH
V
OL
INPUT
SIGNAL
OUTPUT
SIGNAL
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