DAQ PCI-MIO E Series User Manual

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User Manual

Multifunction I/O Boards for

PCI Bus Computers

January 1997 Edition

Part Number 320945B-01

Internet Support

support@natinst.com

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Tel: (512) 795-8248 Fax: (512) 794-5678

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National Instruments Corporate Headquarters

6504 Bridge Point Parkway Austin, TX 78730-5039 Tel: (512) 794-0100

Important Information

Warranty

The PCI-MIO E Series boards are warranted against defects in materials and workmanship for a period of one year from the date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to be defective during the warranty period. This warranty includes parts and labor.

The media on which you receive National Instruments software are warranted not to fail to execute programming instructions, due to defects in materials and workmanship, for a period of 90 days from date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace software media that do not execute programming instructions if National Instruments receives notice of such defects during the warranty period. National Instruments does not warrant that the operation of the software shall be uninterrupted or error free.

A Return Material Authorization (RMA) number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work. National Instruments will pay the shipping costs of returning to the owner parts which are covered by warranty.

National Instruments believes that the information in this manual is accurate. The document has been carefully reviewed for technical accuracy. In the event that technical or typographical errors exist, National Instruments reserves the right to make changes to subsequent editions of this document without prior notice to holders of this edition. The reader should consult National Instruments if errors are suspected. In no event shall National Instruments be liable for any damages arising out of or related to this document or the information contained in it.

XCEPT AS SPECIFIED HEREIN

SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE

USTOMER’S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF NATIONAL

NSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER

WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA, PROFITS, USE OF PRODUCTS, OR INCIDENTAL OR CONSEQUENTIAL DAMAGES, EVEN IF ADVISED OF THE POSSIBILITY THEREOF

Instruments will apply regardless of the form of action, whether in contract or tort, including negligence. Any action against National Instruments must be brought within one year after the cause of action accrues. National Instruments shall not be liable for any delay in performance due to causes beyond its reasonable control. The warranty provided herein does not cover damages, defects, malfunctions, or service failures caused by owner’s failure to follow the National Instruments installation, operation, or maintenance instructions; owner’s modification of the product; owner’s abuse, misuse, or negligent acts; and power failure or surges, fire, flood, accident, actions of third parties, or other events outside reasonable control.

ATIONAL INSTRUMENTS MAKES NO WARRANTIES, EXPRESS OR IMPLIED, AND

, N

ATIONAL INSTRUMENTS

. N

. This limitation of the liability of National

Copyright

Under the copyright laws, this publication may not be reproduced or transmitted in any form, electronic or mechanical, including photocopying, recording, storing in an information retrieval system, or translating, in whole or in part, without the prior written consent of National Instruments Corporation.

Trademarks

LabVIEW®, NI-DAQ®, RTSI®, ComponentWorks™, CVI™, DAQ-STC™, MITE™, NI-PGIA™, SCXI™, and VirtualBench™ are trademarks of National Instruments Corporation.

Product and company names listed are trademarks or trade names of their respective companies.

WARNING REGARDING MEDICAL AND CLINICAL USE OF NATIONAL INSTRUMENTS PRODUCTS

National Instruments products are not designed with components and testing intended to ensure a level of reliability suitable for use in treatment and diagnosis of humans. Applications of National Instruments products involving medical or clinical treatment can create a potential for accidental injury caused by product failure, or by errors on the part of the user or application designer. Any use or application of National Instruments products for or involving medical or clinical treatment must be performed by properly trained and qualified medical personnel, and all traditional medical safeguards, equipment, and procedures that are appropriate in the particular situation to prevent serious injury or death should always continue to be used when National Instruments products are being used. National Instruments products are NOT intended to be a substitute for any form of established process, procedure, or equipment used to monitor or safeguard human health and safety in medical or clinical treatment.

About This Manual

Organization of This Manual........................................................................................xi

Conventions Used in This Manual................................................................................xii

National Instruments Documentation...........................................................................xiii

Related Documentation.................................................................................................xiv

Customer Communication............................................................................................xiv

Chapter 1 Introduction

About the PCI-MIO E Series........................................................................................1-1

What You Need to Get Started .....................................................................................1-2

Software Programming Choices...................................................................................1-3

National Instruments Application Software...................................................1-3

NI-DAQ Driver Software...............................................................................1-4

Optional Equipment......................................................................................................1-6

Custom Cabling ............................................................................................................1-6

Unpacking.....................................................................................................................1-7

Table

Contents

Chapter 2 Installation and Configuration

Software Installation.....................................................................................................2-1

Hardware Installation....................................................................................................2-1

Board Configuration .....................................................................................................2-2

National Instruments Corporation v PCI-MIO E Series User Manual

Table of Contents

Chapter 3 Hardware Overview

Analog Input.................................................................................................................3-3

Input Mode.....................................................................................................3-3

Input Polarity and Input Range...................................................................... 3-4

Dither ............................................................................................................. 3-8

Multichannel Scanning Considerations ......................................................... 3-9

Analog Output.............................................................................................................. 3-11

Analog Output Reference Selection............................................................... 3-11

Analog Output Polarity Selection .................................................................. 3-11

Analog Output Reglitch Selection ................................................................. 3-12

Analog Trigger ............................................................................................................. 3-13

Digital I/O..................................................................................................................... 3-16

Timing Signal Routing................................................................................................. 3-16

Programmable Function Inputs...................................................................... 3-17

Board and RTSI Clocks ................................................................................. 3-18

RTSI Triggers ................................................................................................ 3-18

Chapter 4 Signal Connections

I/O Connector............................................................................................................... 4-1

I/O Connector Signal Descriptions ................................................................ 4-3

Analog Input Signal Connections................................................................................. 4-11

Types of Signal Sources............................................................................................... 4-13

Floating Signal Sources ................................................................................. 4-13

Ground-Referenced Signal Sources............................................................... 4-13

Input Configurations..................................................................................................... 4-13

Differential Connection Considerations (DIFF Input Configuration) ........... 4-15

Single-Ended Connection Considerations ..................................................... 4-18

Common-Mode Signal Rejection Considerations.......................................... 4-21

Analog Output Signal Connections.............................................................................. 4-22

Digital I/O Signal Connections .................................................................................... 4-23

Considerations for Selecting Input Ranges...................................... 3-7

Differential Connections for Ground-Referenced Signal

Sources.......................................................................................... 4-16

Differential Connections for Nonreferenced or Floating

Signal Sources............................................................................... 4-17

Single-Ended Connections for Floating Signal Sources

(RSE Configuration)..................................................................... 4-20

Single-Ended Connections for Grounded Signal Sources

(NRSE Configuration).................................................................. 4-20

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Table of Contents

Power Connections .......................................................................................................4-25

Timing Connections......................................................................................................4-25

Programmable Function Input Connections...................................................4-26

DAQ Timing Connections..............................................................................4-27

SCANCLK Signal............................................................................4-28

EXTSTROBE* Signal .....................................................................4-29

TRIG1 Signal...................................................................................4-29

TRIG2 Signal...................................................................................4-31

STARTSCAN Signal.......................................................................4-32

CONVERT* Signal..........................................................................4-34

AIGATE Signal................................................................................4-36

SISOURCE Signal...........................................................................4-36

Waveform Generation Timing Connections ..................................................4-37

WFTRIG Signal...............................................................................4-37

UPDATE* Signal.............................................................................4-38

UISOURCE Signal ..........................................................................4-40

General-Purpose Timing Signal Connections ................................................4-40

GPCTR0_SOURCE Signal..............................................................4-41

GPCTR0_GATE Signal...................................................................4-42

GPCTR0_OUT Signal .....................................................................4-42

GPCTR0_UP_DOWN Signal..........................................................4-43

GPCTR1_SOURCE Signal..............................................................4-43

GPCTR1_GATE Signal...................................................................4-44

GPCTR1_OUT Signal .....................................................................4-45

GPCTR1_UP_DOWN Signal..........................................................4-46

FREQ_OUT Signal..........................................................................4-47

Field Wiring Considerations.........................................................................................4-48

Chapter 5 Calibration

Loading Calibration Constants .....................................................................................5-1

Self-Calibration.............................................................................................................5-2

External Calibration......................................................................................................5-2

Other Considerations ....................................................................................................5-3

Appendix A Specifications

Appendix B Optional Cable Connector Descriptions

National Instruments Corporation vii PCI-MIO E Series User Manual

Table of Contents

Appendix C Common Questions

Appendix D Customer Communication

Glossary Index Figures

Figure 1-1. The Relationship between the Programming Environment,

NI-DAQ, and Your Hardware............................................................... 1-5

Figure 3-1. PCI-MIO-16E-1 and PCI-MIO-16E-4 Block Diagram.........................3-1

Figure 3-2. PCI-MIO-16XE-10 Block Diagram...................................................... 3-2

Figure 3-3. PCI-MIO-16XE-50 Block Diagram...................................................... 3-3

Figure 3-4. Dither.....................................................................................................3-9

Figure 3-5. Analog Trigger Block Diagram............................................................. 3-13

Figure 3-6. Below-Low-Level Analog Triggering Mode ........................................ 3-14

Figure 3-7. Above-High-Level Analog Triggering Mode ....................................... 3-14

Figure 3-8. Inside-Region Analog Triggering Mode............................................... 3-15

Figure 3-9. High-Hysteresis Analog Triggering Mode............................................3-15

Figure 3-10. Low-Hysteresis Analog Triggering Mode............................................. 3-15

Figure 3-11. CONVERT* Signal Routing................................................................. 3-17

Figure 3-12. RTSI Bus Signal Connection................................................................. 3-19

Figure 4-1. I/O Connector Pin Assignment for the PCI-MIO E Series Boards....... 4-2

Figure 4-2. PCI-MIO E Series PGIA....................................................................... 4-12

Figure 4-3. Summary of Analog Input Connections................................................ 4-14

Figure 4-4. Differential Input Connections for Ground-Referenced Signals...........4-16

Figure 4-5. Differential Input Connections for Nonreferenced Signals...................4-17

Figure 4-6. Single-Ended Input Connections for Nonreferenced or

Floating Signals..................................................................................... 4-20

Figure 4-7. Single-Ended Input Connections for Ground-Referenced Signals........ 4-21

Figure 4-8. Analog Output Connections.................................................................. 4-23

Figure 4-9. Digital I/O Connections......................................................................... 4-24

Figure 4-10. Timing I/O Connections........................................................................ 4-26

Figure 4-11. Typical Posttriggered Acquisition.........................................................4-27

Figure 4-12. Typical Pretriggered Acquisition .......................................................... 4-28

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Table of Contents

Figure 4-13. SCANCLK Signal Timing.....................................................................4-28

Figure 4-14. EXTSTROBE* Signal Timing ..............................................................4-29

Figure 4-15. TRIG1 Input Signal Timing...................................................................4-30

Figure 4-16. TRIG1 Output Signal Timing................................................................4-30

Figure 4-17. TRIG2 Input Signal Timing...................................................................4-31

Figure 4-18. TRIG2 Output Signal Timing................................................................4-32

Figure 4-19. STARTSCAN Input Signal Timing.......................................................4-33

Figure 4-20. STARTSCAN Output Signal Timing....................................................4-33

Figure 4-21. CONVERT* Input Signal Timing.........................................................4-35

Figure 4-22. CONVERT* Output Signal Timing ......................................................4-35

Figure 4-23. SISOURCE Signal Timing....................................................................4-37

Figure 4-24. WFTRIG Input Signal Timing...............................................................4-38

Figure 4-25. WFTRIG Output Signal Timing............................................................4-38

Figure 4-26. UPDATE* Input Signal Timing ............................................................4-39

Figure 4-27. UPDATE* Output Signal Timing..........................................................4-39

Figure 4-28. UISOURCE Signal Timing ...................................................................4-40

Figure 4-29. GPCTR0_SOURCE Signal Timing.......................................................4-41

Figure 4-30. GPCTR0_GATE Signal Timing in Edge-Detection Mode ...................4-42

Figure 4-31. GPCTR0_OUT Signal Timing ..............................................................4-43

Figure 4-32. GPCTR1_SOURCE Signal Timing.......................................................4-44

Figure 4-33. GPCTR1_GATE Signal Timing in Edge-Detection Mode ...................4-45

Figure 4-34. GPCTR1_OUT Signal Timing ..............................................................4-45

Figure 4-35. GPCTR Timing Summary .....................................................................4-46

Figure B-1. 68-Pin MIO Connector Pin Assignments ..............................................B-2

Figure B-2. 50-Pin MIO Connector Pin Assignments ..............................................B-3

Tables

Table 3-1. Available Input Configurations for the PCI-MIO E Series ...................3-4

Table 3-2. Actual Range and Measurement Precision,

PCI-MIO-16E-1 and PCI-MIO-16E-4...................................................3-5

Table 3-3. Actual Range and Measurement Precision,

PCI-MIO-16XE-10 and PCI-MIO-16XE-50.........................................3-7

Table 4-1. I/O Signal Summary, PCI-MIO-16E-1 and PCI-MIO-16E-4................4-6

Table 4-2. I/O Signal Summary, PCI-MIO-16XE-10.............................................4-7

Table 4-3. I/O Signal Summary, PCI-MIO-16XE-50.............................................4-9

National Instruments Corporation ix PCI-MIO E Series User Manual

About

This

Manual

This manual describes the electrical and mechanical aspects of each board in the PCI-MIO E Series product line and contains information concerning their operation and programming. Unless otherwise noted, text applies to all boards in the PCI-MIO E Series.

The PCI-MIO E Series includes the following boards:

• PCI-MIO-16E-1

• PCI-MIO-16E-4

• PCI-MIO-16XE-10

• PCI-MIO-16XE-50 The PCI-MIO E Series boards are high-performance multifunction

analog, digital, and timing I/O boards for PCI bus computers. Supported functions include analog input, analog output, digital I/O, and timing I/O.

Organization of This Manual

The

PCI-MIO E Series User Manual

• Chapter 1, lists what you need to get started, describes the optional software and optional equipment, and explains how to unpack your PCI-MIO E Series board.

• Chapter 2, and configure your PCI-MIO E Series board.

• Chapter 3, hardware functions on your PCI-MIO E Series board.

• Chapter 4, Signal Connections output signal connections to your PCI-MIO E Series board via the board I/O connector.

• Chapter 5, your PCI-MIO E Series board.

National Instruments Corporation xi PCI-MIO E Series User Manual

Introduction

Installation and Configuration

Hardware Overview

Calibration

, describes the PCI-MIO E Series boards,

, discusses the calibration procedures for

is organized as follows:

, explains how to install

, presents an overview of the

, describes how to make input and

About This Manual

• Appendix A, PCI-MIO E Series board.

• Appendix B, connectors on the optional cables for the PCI-MIO E Series boards.

• Appendix C, questions and their answers relating to usage and special features of your PCI-MIO E Series board.

• Appendix D, to request help from National Instruments or to comment on our products.

• The

Glossary

used in this manual, including acronyms, abbreviations, definitions metric prefixes, mnemonics, and symbols.

Index

including the page where you can find the topic.

Specifications

Optional Cable Connector Descriptions

Common Questions

Customer Communication

contains an alphabetical list and description of terms

alphabetically lists topics covered in this manual,

, lists the specifications of each

, describes the

, contains a list of commonly asked

, contains forms you can use

Conventions Used in This Manual

The following conventions are used in this manual.

bold

bold italic

italic

Macintosh Macintosh refers to all Macintosh computers with PCI bus, unless

monospace

NI-DAQ NI-DAQ refers to the NI-DAQ driver software for Macintosh or

PC Refers to all PC AT series computers with PCI bus unless otherwise

Bold text denotes parameters. Bold italic text denotes a note, caution, or warning. Italic text denotes emphasis on a specific board in the PCI-MIO E Series

or on other important information, a cross reference, or an introduction to a key concept.

otherwise noted. Text in this font denotes text or characters that are to be literally input

from the keyboard, sections of code, programming examples, and syntax examples. This font is also used for the proper names of disk drives, paths, directories, programs, subprograms, subroutines, device names, functions, variables, file names, and extensions, and for statements and comments taken from program code.

PC compatible computers unless otherwise noted.

noted.

PCI-MIO E Series User Manual xii

National Instruments Corporation

About This Manual

SCXI SCXI stands for Signal Conditioning eXtensions for Instrumentation

and is a National Instruments product line designed to perform front-end signal conditioning for National Instruments plug-in DAQ boards.

♦ The ♦ indicates that the text following it applies only to specific

PCI-MIO E Series boards.

< > Angle brackets containing numbers separated by an ellipsis represent a

range of values associated with a bit, port, or signal name (for example, ACH<0..7> stands for ACH0 through ACH7).

Abbreviations, acronyms, definitions, metric prefixes, mnemonics, symbols, and terms are listed in the Glossary at the end of this manual.

National Instruments Documentation

The PCI-MIO E Series User Manual is one piece of the documentation set for your DAQ system. You could have any of several types of manuals depending on the hardware and software in your system. Use the manuals you have as follows:

• Getting Started with SCXI—If you are using SCXI, this is the first manual you should read. It gives an overview of the SCXI system and contains the most commonly needed information for the modules, chassis, and software.

• Your SCXI hardware user manuals—If you are using SCXI, read these manuals next for detailed information about signal connections and module configuration. They also explain in greater detail how the module works and contain application hints.

• Your DAQ hardware documentation—This documentation has detailed information about the DAQ hardware that plugs into or is connected to your computer. Use this documentation for hardware installation and configuration instructions, specification information about your DAQ hardware, and application hints.

• Software documentation—You may have both application software and NI-DAQ software documentation. National Instruments application software includes ComponentWorks, LabVIEW, LabWindows®/CVI, Measure, and VirtualBench. After you set up your hardware system, use either your application software documentation or the NI-DAQ documentation to help you write your application. If you have a large, complicated system, it is

National Instruments Corporation xiii PCI-MIO E Series User Manual

About This Manual

worthwhile to look through the software documentation before you configure your hardware.

• Accessory installation guides or manuals—If you are using accessory products, read the terminal block and cable assembly installation guides. They explain how to physically connect the relevant pieces of the system. Consult these guides when you are making your connections.

• SCXI Chassis Manual—If you are using SCXI, read this manual for maintenance information on the chassis and installation instructions.

Customer Communication

National Instruments wants to receive your comments on our products and manuals. We are interested in the applications you develop with our products, and we want to help if you have problems with them. To make it easy for you to contact us, this manual contains comment and configuration forms for you to complete. These forms are in Appendix D, Customer Communication, at the end of this manual.

PCI-MIO E Series User Manual xiv

National Instruments Corporation

Chapter

Introduction

This chapter describes the PCI-MIO E Series boards, lists what you need to get started, describes the optional software and optional equipment, and explains how to unpack your PCI-MIO E Series board.

About the PCI-MIO E Series

Thank you for buying a National Instruments PCI-MIO E Series board. The PCI-MIO E Series boards are completely Plug and Play, multifunction analog, digital, and timing I/O boards for PCI bus computers. This family of boards features 12-bit and 16-bit ADCs with 16 analog inputs, 12-bit and 16-bit DACs with voltage outputs, eight lines of TTL-compatible digital I/O, and two 24-bit counter/timers for timing I/O. Because the PCI-MIO E Series boards have no DIP switches, jumpers, or potentiometers, they are easily softwareconfigured and calibrated.

The PCI-MIO E Series boards are completely switchless and jumperless data acquisition (DAQ) boards for the PCI bus. This feature is made possible by the National Instruments MITE bus interface chip that connects the board to the PCI I/O bus. The MITE implements the PCI Local Bus Specification so that the interrupts and base memory addresses are all software configured.

The PCI-MIO E Series boards use the National Instruments DAQ-STC system timing controller for time-related functions. The DAQ-STC consists of three timing groups that control analog input, analog output, and general-purpose counter/timer functions. These groups include a total of seven 24-bit and three 16-bit counters and a maximum timing resolution of 50 ns. The DAQ-STC makes possible such applications as buffered pulse generation, equivalent time sampling, and seamlessly changing the sampling rate.

Often with DAQ boards, you cannot easily synchronize several measurement functions to a common trigger or timing event. The PCI-MIO E Series boards have the Real-Time System Integration (RTSI) bus to solve this problem. The RTSI bus consists of our RTSI

National Instruments Corporation 1-1 PCI-MIO E Series User Manual

Chapter 1 Introduction

bus interface and a ribbon cable to route timing and trigger signals between several functions on as many as five DAQ boards in your computer.

The PCI-MIO E Series boards can interface to an SCXI system so that you can acquire over 3,000 analog signals from thermocouples, RTDs, strain gauges, voltage sources, and current sources. You can also acquire or generate digital signals for communication and control. SCXI is the instrumentation front end for plug-in DAQ boards.

Detailed specifications of the PCI-MIO E Series boards are in Appendix A, Specifications.

What You Need to Get Started

To set up and use your PCI-MIO E Series board, you will need the following:

❑ One of the following boards:

PCI-MIO-16E-1 PCI-MIO-16E-4 PCI-MIO-16XE-10 PCI-MIO-16XE-50

❑ PCI-MIO E Series User Manual ❑ One of the following software packages and documentation:

ComponentWorks LabVIEW for Macintosh LabVIEW for Windows LabWindows/CVI for Windows Measure NI-DAQ for Macintosh NI-DAQ for PC Compatibles VirtualBench

❑ Your computer

1. Please note that only the PCI-MIO-16XE-50 is currently supported on the Macintosh. Please contact National Instruments for information on Macintosh support for the other boards in the PCI-MIO E Series.

PCI-MIO E Series User Manual 1-2

National Instruments Corporation

Software Programming Choices

You have several options to choose from when programming your National Instruments DAQ and SCXI hardware. You can use National Instruments application software, NI-DAQ, or register-level programming.

National Instruments Application Software

ComponentWorks contains tools for data acquisition and instrument control built on NI-DAQ driver software. ComponentWorks provides a higher-level programming interface for building virtual instruments through standard OLE controls and DLLs. With ComponentWorks, you can use all of the configuration tools, resource management utilities, and interactive control utilities included with NI-DAQ.

LabVIEW features interactive graphics, a state-of-the-art user interface, and a powerful graphical programming language. The LabVIEW Data Acquisition VI Library, a series of VIs for using LabVIEW with National Instruments DAQ hardware, is included with LabVIEW. The LabVIEW Data Acquisition VI Library is functionally equivalent to NI-DAQ software.

Chapter 1 Introduction

LabWindows/CVI features interactive graphics, state-of-the-art user interface, and uses the ANSI standard C programming language. The LabWindows/CVI Data Acquisition Library, a series of functions for using LabWindows/CVI with National Instruments DAQ hardware, is included with the NI-DAQ software kit. The LabWindows/CVI Data Acquisition Library is functionally equivalent to the NI-DAQ software.

VirtualBench features virtual instruments that combine DAQ products, software, and your computer to create a stand-alone instrument with the added benefit of the processing, display, and storage capabilities of your computer. VirtualBench instruments load and save waveform data to disk in the same forms that can be used in popular spreadsheet programs and word processors.

Using ComponentWorks, LabVIEW, LabWindows/CVI, or VirtualBench software will greatly reduce the development time for your data acquisition and control application.

National Instruments Corporation 1-3 PCI-MIO E Series User Manual

Chapter 1 Introduction

NI-DAQ Driver Software

The NI-DAQ driver software is included at no charge with all National Instruments DAQ hardware. NI-DAQ is not packaged with SCXI or accessory products, except for the SCXI-1200. NI-DAQ has an extensive library of functions that you can call from your application programming environment. These functions include routines for analog input (A/D conversion), buffered data acquisition (high-speed A/D conversion), analog output (D/A conversion), waveform generation (timed D/A conversion), digital I/O, counter/timer operations, SCXI, RTSI, self-calibration, messaging, and acquiring data to extended memory.

NI-DAQ has both high-level DAQ I/O functions for maximum ease of use and low-level DAQ I/O functions for maximum flexibility and performance. Examples of high-level functions are streaming data to disk or acquiring a certain number of data points. An example of a low-level function is writing directly to registers on the DAQ device. NI-DAQ does not sacrifice the performance of National Instruments DAQ devices because it lets multiple devices operate at their peak.

NI-DAQ also internally addresses many of the complex issues between the computer and the DAQ hardware such as programming interrupts and DMA controllers. NI-DAQ maintains a consistent software interface among its different versions so that you can change platforms with minimal modifications to your code. Whether you are using conventional programming languages or National Instruments application software, your application uses the NI-DAQ driver software, as illustrated in Figure 1-1.

PCI-MIO E Series User Manual 1-4

National Instruments Corporation

Chapter 1 Introduction

Programming Environment

SCXI Hardware

Figure 1-1. The Relationship between the Programming Environment,

The final option for programming any National Instruments DAQ hardware is to write register-level software. Writing register-level programming software can be very time-consuming and inefficient, and is not recommended for most users.

Conventional 

 

DAQ or

ComponentWorks,

LabWindows/CVI, or

NI-DAQ

Driver Software

NI-DAQ, and Your Hardware



LabVIEW,

VirtualBench



Personal 

Computer or 

Workstation

Even if you are an experienced register-level programmer, using NI-DAQ or application software to program your National Instruments DAQ hardware is easier than, and as flexible as, register-level programming, and can save weeks of development time.

National Instruments Corporation 1-5 PCI-MIO E Series User Manual

Chapter 1 Introduction

Optional Equipment

National Instruments offers a variety of products to use with your PCI-MIO E Series board, including cables, connector blocks, and other accessories, as follows:

• Cables and cable assemblies, shielded and ribbon

• Connector blocks, shielded and unshielded 50 and 68-pin screw terminals

• Real Time System Integration (RTSI) bus cables

• SCXI modules and accessories for isolating, amplifying, exciting, and multiplexing signals for relays and analog output. With SCXI you can condition and acquire up to 3,072 channels.

• Low channel count signal conditioning modules, boards, and accessories, including conditioning for strain gauges and RTDs, simultaneous sample and hold, and relays

For more specific information about these products, refer to your National Instruments catalogue or call the office nearest you.

Custom Cabling

National Instruments offers cables and accessories for you to prototype your application or to use if you frequently change board interconnections.

If you want to develop your own cable, however, the following guidelines may be useful:

• For the analog input signals, shielded twisted-pair wires for each analog input pair yield the best results, assuming that you use differential inputs. Tie the shield for each signal pair to the ground reference at the source.

• You should route the analog lines separately from the digital lines.

• When using a cable shield, use separate shields for the analog and digital halves of the cable. Failure to do so results in noise coupling into the analog signals from transient digital signals.

The following list gives recommended part numbers for connectors that mate to the I/O connector on your PCI-MIO E Series board.

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National Instruments Corporation

Unpacking

Chapter 1 Introduction

Mating connectors and a backshell kit for making custom 68-pin cables are available from National Instruments (part number 776832-01)

♦ PCI-MIO-16E-1, PCI-MIO-16E-4, PCI-MIO-16XE-10, and the

PCI-MIO-16XE-50 Honda 68-position, solder cup, female connector (part number

PCS-E68FS) Honda backshell (part number PCS-E68LKPA)

Your PCI-MIO E Series board is shipped in an antistatic package to prevent electrostatic damage to the board. Electrostatic discharge can damage several components on the board. To avoid such damage in handling the board, take the following precautions:

• Ground yourself via a grounding strap or by holding a grounded object.

• Touch the antistatic package to a metal part of your computer chassis before removing the board from the package.

• Remove the board from the package and inspect the board for loose components or any other sign of damage. Notify National Instruments if the board appears damaged in any way. Do not install a damaged board into your computer.

• Never touch the exposed pins of connectors.

National Instruments Corporation 1-7 PCI-MIO E Series User Manual

Installation and

Chapter

Configuration

This chapter explains how to install and configure your PCI-MIO E Series board.

Software Installation

Install your software before you install your PCI-MIO E Series board. Refer to the appropriate release notes indicated below for specific instructions on the software installation sequence.

If you are using NI-DAQ, refer to your NI-DAQ release notes. Find the installation section for your operating system and follow the instructions given there.

If you are using LabVIEW, LabWindows/CVI, or other National Instruments application software packages, refer to the appropriate release notes. After you have installed your application software, refer to your NI-DAQ release notes and follow the instructions given there for your operating system and application software package.

If you are a register-level programmer, refer to the PCI-MIO E Series Register-Level Programmer Manual and the DAQ-STC Technical Reference Manual for software configuration information.

Hardware Installation

You can install a PCI-MIO E Series board in any available expansion slot in your computer. However, to achieve best noise performance, leave as much room as possible between the PCI-MIO E Series board and other boards and hardware. The following are general installation instructions, but consult your computer user manual or technical reference manual for specific instructions and warnings.

National Instruments Corporation 2-1 PCI-MIO E Series User Manual

Chapter 2 Installation and Conﬁguration

1. Write down the PCI-MIO E Series board serial number in the PCI-MIO E Series Hardware and Software Configuration Form in Appendix D, Customer Communication, of this manual.

2. Turn off and unplug your computer.

3. Remove the top cover or access port to the I/O channel.

4. Remove the expansion slot cover on the back panel of the computer.

5. Insert the PCI-MIO E Series board into a 5 V PCI slot. Gently rock the board to ease it into place. It may be a tight fit, but do not force the board into place.

6. If required, screw the mounting bracket of the PCI-MIO E Series board to the back panel rail of the computer.

7. Replace the cover.

8. Plug in and turn on your computer.

The PCI-MIO E Series board is installed. You are now ready to configure your software. Refer to your software documentation for configuration instructions.

Board Configuration

Due to the National Instruments standard architecture for data acquisition and the PCI bus specification, the PCI-MIO E Series boards are completely software configurable. You must perform two types of configuration on the PCI-MIO E Series boards—bus-related and data acquisition-related configuration.

The PCI-MIO E Series boards are fully compatible with the industry standard PCI Local Bus Specification Revision 2.0. This allows the PCI system to automatically perform all bus-related configurations and requires no user interaction. Bus-related configuration includes setting the board base memory address and interrupt channel.

Data-acquisition-related configuration includes such settings as analog input polarity and range, analog input mode, and others. You can modify these settings through application level software, such as NI-DAQ, ComponentWorks, LabVIEW, LabWindows/CVI, and VirtualBench.

PCI-MIO E Series User Manual 2-2

National Instruments Corporation

Chapter

Hardware Overview

This chapter presents an overview of the hardware functions on your PCI-MIO E Series board.

Figure 3-1 shows a block diagram for the PCI-MIO-16E-1 and PCI-MIO-16E-4.

Dither

Circuitry

Calibration

DACs

+

NI-PGIA Gain Amplifier –

Trigger

Counter/

Timing I/O

Digital I/O

Configuration

Voltage

REF

(8)

Analog Muxes

(8)

Calibration

Mux

DACs

Trigger

PFI / Trigger

Timing

Digital I/O (8)

Trigger Level

I/O Connector

Mux Mode Selection Switches

Analog

Trigger

Circuitry

12-Bit

Sampling

A/D

Converter

Memory

Analog Input

Timing/Control

DAQ - STC

Analog Output Timing/Control

AI Control

DMA/ Interrupt Request

Bus

Interface

RTSI Bus

Interface

ADC

FIFO

IRQ DMA

Data (16)

Analog

Input

Control

DAQ-STC

Bus

Interface

Analog Output Control

Generic

Bus

Interface

EEPROM

EEPROM

Control

Interface

Control

PCI

MITE

Bus

Interface

Address/Data

DMA

Interface

MIO

I/O

Bus

Interface

Address (5)

PCI Bus

AO Control

DAC0

DAC1

DAC

FIFO

Calibration

DACs

Data (16)

RTSI Bus

Figure 3-1. PCI-MIO-16E-1 and PCI-MIO-16E-4 Block Diagram

National Instruments Corporation 3-1 PCI-MIO E Series User Manual

Chapter 3 Hardware Overview

Voltage

REF

(8)

Analog Muxes

(8)

Trigger Level

DACs

Trigger

PFI / Trigger

Digital I/O (8)

I/O Connector

Timing

Calibration

Mux

Mux Mode Selection Switches

Analog Trigger

Circuitry

Figure 3-2 shows a block diagram for the PCI-MIO-16XE-10.

REF

Calibration

DACs

+

Programmable Gain Amplifier –

Trigger

Counter/

Timing I/O

Digital I/O

Sampling Converter

Configuration

Memory

Analog Input

Timing/Control

DAQ - STC

Analog Output Timing/Control

AO Control

Buffer

16-Bit

A/D

AI Control

DMA/ Interrupt Request

Bus

Interface

RTSI Bus

Interface

ADC

FIFO

Data (16)

IRQ DMA

Analog

Input

Control

DAQ-STC

Bus

Interface

Analog Output Control

Generic

Bus

Interface

EEPROM

EEPROM

Control

MIO

Interface

MITE

Interface



Interface

DMA

Bus

I/O

PCI Bus

Interface

Control

Address/Data

Address (5)

PCI Bus

DAC0

DAC1

DAC

FIFO

Calibration

DACs

Data (16)

RTSI Bus

Figure 3-2. PCI-MIO-16XE-10 Block Diagram

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National Instruments Corporation

Chapter 3 Hardware Overview

Figure 3-3 shows a block diagram for the PCI-MIO-16XE-50.

Voltage

REF

(8)

Analog Muxes

(8)

Calibration

Mux

PFI / Trigger

Timing

I/O Connector

Digital I/O (8)

DAC0

DAC1

Mux Mode Selection Switches

Calibration

DACs

+

Programmable Gain Amplifier –

Calibration

DACs

16-Bit

Configuration

Memory

Sampling

A/D

Converter

ADC FIFO

AI Control

IRQ

Data (16)

DMA

Trigger

Counter/

Timing I/O

Digital I/O

Analog Input

Timing/Control

DAQ - STC

Analog Output Timing/Control

AO Control

Data (16)

DMA/ Interrupt Request

Bus

Interface

RTSI Bus

Interface

RTSI Bus

Figure 3-3. PCI-MIO-16XE-50 Block Diagram

Analog

Input

Control

DAQ-STC

Bus

Interface

Analog Output

Control

Generic

Bus

Interface

EEPROM

EEPROM

Control

Interface

MIO

MITE

Interface

DMA

Interface

I/O

Bus

Interface

PCI Bus

Control

Address/Data

Address (5)

PCI Bus

Analog Input

The analog input section of each PCI-MIO E Series board is software configurable. You can select different analog input configurations through application software designed to control the PCI-MIO E Series boards. The following sections describe in detail each of the analog input categories.

Input Mode

The PCI-MIO E Series boards have three different input modes— nonreferenced single-ended (NRSE) input, referenced single-ended (RSE) input, and differential (DIFF) input. The single-ended input configurations provide up to 16 channels. The DIFF input configuration provides up to eight channels. Input modes are programmed on a per

National Instruments Corporation 3-3 PCI-MIO E Series User Manual

Chapter 3 Hardware Overview

channel basis for multimode scanning. For example, you can configure the circuitry to scan 12 channels—four differentially-configured channels and eight single-ended channels. Table 3-1 describes the three input configurations.

Table 3-1. Available Input Configurations for the PCI-MIO E Series

Configuration Description

DIFF A channel configured in DIFF mode uses two analog

channel input lines. One line connects to the positive input of the board programmable gain instrumentation amplifier (PGIA), and the other connects to the negative input of the PGIA.

RSE A channel configured in RSE mode uses one analog

channel input line, which connects to the positive input of the PGIA. The negative input of the PGIA is internally tied to analog input ground (AIGND).

NRSE A channel configured in NRSE mode uses one

analog channel input line, which connects to the positive input of the PGIA. The negative input of the PGIA connects to the analog input sense (AISENSE) input.

For more information about the three types of input configuration, refer to the Analog Input Signal Connections section in Chapter 4, Signal Connections, which contains diagrams showing the signal paths for the three configurations.

Input Polarity and Input Range

♦ PCI-MIO-16E-1 and PCI-MIO-16E-4

These boards have two input polarities—unipolar and bipolar. Unipolar input means that the input voltage range is between 0 and V V

is a positive reference voltage. Bipolar input means that the input

ref

voltage range is between -V and PCI-MIO-16E-4 have a unipolar input range of 10 V (0 to 10 V) and a bipolar input range of 10 V (±5 V).

PCI-MIO E Series User Manual 3-4

ref

and + V

, where

ref

/2. The PCI-MIO-16E-1

ref

National Instruments Corporation

Chapter 3 Hardware Overview

You can program polarity and range settings on a per channel basis so that you can configure each input channel uniquely.

The software-programmable gain on these boards increases their overall flexibility by matching the input signal ranges to those that the ADC can accommodate. The PCI-MIO-16E-1 and PCI-MIO-16E-4 have gains of 0.5, 1, 2, 5, 10, 20, 50, and 100 and are suited for a wide variety of signal levels. With the proper gain setting, you can use the full resolution of the ADC to measure the input signal. Table 3-2 shows the overall input range and precision according to the input range configuration and gain used.

Table 3-2. Actual Range and Measurement Precision, PCI-MIO-16E-1 and PCI-MIO-16E-4

Range

Gain Actual Input Range Precision

Configuration

0 to +10 V 1.0

2.0

5.0

10.0

20.0

50.0

100.0

-5 to +5 V 0.5

1.0

2.0

5.0

10.0

20.0

50.0

100.0

The value of 1 LSB of the 12-bit ADC; that is, the voltage increment

0 to +10 V

0 to +5 V 0 to +2 V

0 to +1 V 0 to +500 mV 0 to +200 mV 0 to +100 mV

-10 to +10 V

-5 to +5 V

-2.5 to +2.5 V

-1 to +1 V

-500 to +500 mV

-250 to +250 mV

-100 to +100 mV

-50 to +50 mV

2.44 mV

1.22 mV

488.28 µV

244.14 µV

122.07 µV

48.83 µV

24.41 µV

4.88 mV

2.44 mV

1.22 mV

488.28 µV

244.14 µV

122.07 µV

48.83 µV

24.41 µV

corresponding to a change of one count in the ADC 12-bit count.

Note: See Appendix A, Specifications, for absolute maximum

ratings.

National Instruments Corporation 3-5 PCI-MIO E Series User Manual

Chapter 3 Hardware Overview

♦ PCI-MIO-16XE-10 and PCI-MIO-16XE-50

Note: You can calibrate your PCI-MIO-16XE-10 and PCI-MIO-16XE-50 analog

input circuitry for either a unipolar or bipolar polarity. If you mix unipolar and bipolar channels in your scan list and you are using NI-DAQ, then NI-DAQ will load the calibration constants appropriate to the polarity for which analog input channel 0 is configured.

These boards have two input polarities—unipolar and bipolar. Unipolar input means that the input voltage range is between 0 and V V

is a positive reference voltage. Bipolar input means that the input

ref

voltage range is between -V

ref

and +V

. The PCI-MIO-16XE-10 and

ref

, where

ref

PCI-MIO-16XE-50 have a unipolar input range of 10 V (0 to 10 V) and a bipolar input range of 20 V (±10 V). You can program polarity and range settings on a per channel basis so that you can configure each input channel uniquely.

The software-programmable gain on these boards increases their overall flexibility by matching the input signal ranges to those that the ADC can accommodate. The PCI-MIO-16XE-50 has gains of 1, 2, 10, and 100 and the PCI-MIO-16XE-10 has gains of 1, 2, 5, 10, 20, 50, and 100. These gains are suited for a wide variety of signal levels. With the proper gain setting, you can use the full resolution of the ADC to measure the input signal.

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Chapter 3 Hardware Overview

Table 3-3 shows the overall input range and precision according to the input range configuration and gain used.

Table 3-3. Actual Range and Measurement Precision,

PCI-MIO-16XE-10 and PCI-MIO-16XE-50

Range

Gain Actual Input Range Precision

Configuration

0 to +10 V 1.0

2.0

5.0

10.0

20.0

50.0

100.0

-10 to +10 V 1.0

2.0

5.0

10.0

20.0

50.0

100.0

The value of 1 LSB of the 16-bit ADC; that is, the voltage increment

0 to +10 V

0 to +5 V

0 to +2 V

0 to +1 V 0 to +500 mV 0 to +200 mV

0 to 100 mV

-10 to +10 V

-5 to +5 V

-2 to +2 V

-1 to +1 V

-500 to +500 mV

-200 to +200 mV

-100 to +100 mV

152.59 µV

76.29 µV

30.52 µV

15.26 µV

7.63µV

3.05 µV

1.53 µV

305.18 µV

152.59 µV

61.04 µV

30.52 µV

15.26 µV

6.10 µV

3.05 µV

corresponding to a change of one count in the ADC 16-bit count.

PCI-MIO-16XE-10 only

Note: See Appendix A, Specifications, for absolute maximum

ratings.

Considerations for Selecting Input Ranges

Which input polarity and range you select depends on the expected range of the incoming signal. A large input range can accommodate a large signal variation but reduces the voltage resolution. Choosing a smaller input range improves the voltage resolution but may result in the input signal going out of range. For best results, match the input range as closely as possible to the expected range of the input signal. For example, if you are certain the input signal will not be negative (below 0 V), unipolar input polarity is best. However, if the signal is negative or equal to zero, you will get inaccurate readings if you use unipolar input polarity.

National Instruments Corporation 3-7 PCI-MIO E Series User Manual

Chapter 3 Hardware Overview

Dither

When you enable dither, you add approximately 0.5 LSBrms of white Gaussian noise to the signal to be converted by the ADC. This addition is useful for applications involving averaging to increase the resolution of your PCI-MIO E Series board, as in calibration or spectral analysis. In such applications, noise modulation is decreased and differential linearity is improved by the addition of the dither. When taking DC measurements, such as when checking the board calibration, you should enable dither and average about 1,000 points to take a single reading. This process removes the effects of quantization and reduces measurement noise, resulting in improved resolution. For high-speed applications not involving averaging or spectral analysis, you may want to disable the dither to reduce noise. Your software enables and disables the dither circuitry.

Figure 3-4 illustrates the effect of dither on signal acquisition. Figure 3-4a shows a small (±4 LSB) sine wave acquired with dither off. The ADC quantization is clearly visible. Figure 3-4b shows what happens when 50 such acquisitions are averaged together; quantization is still plainly visible. In Figure 3-4c, the sine wave is acquired with dither on. There is a considerable amount of visible noise. But averaging about 50 such acquisitions, as shown in Figure 3-4d, eliminates both the added noise and the effects of quantization. Dither has the effect of forcing quantization noise to become a zero-mean random variable rather than a deterministic function of the input signal.

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Chapter 3 Hardware Overview

LSBs

6.0

4.0

2.0

0.0

-2.0

-4.0

-6.0

-6.0 100 200 300 4000 500

100 200 300 4000 500

LSBs

6.0

4.0

2.0

0.0

-2.0

-4.0

-6.0

-6.0 100 200 300 4000 500

100 200 300 4000 500

a. Dither disabled; no averaging b. Dither disabled; average of 50 acquisitions

LSBs

6.0

4.0

2.0

0.0

-2.0

-4.0

-6.0

-6.0 100 200 300 4000 500

100 200 300 4000 500

c. Dither enabled; no averaging

LSBs

6.0

4.0

2.0

0.0

-2.0

-4.0

-6.0

-6.0 100 200 300 4000 500

100 200 300 4000 500

d. Dither enabled; average of 50 acquisitions

Figure 3-4. Dither

You cannot disable dither on the PCI-MIO-16XE-10 or PCI-MIO-16XE-50. This is because the ADC resolution is so fine that the ADC and the PGIA inherently produce almost 0.5 LSBrms of noise. This is equivalent to having a dither circuit that is always enabled.

Multichannel Scanning Considerations

Most of the PCI-MIO E Series boards can scan multichannels at the same maximum rate as their single-channel rate; however, pay careful attention to the settling times for each of the boards. The settling time for most of the PCI-MIO E Series boards is independent of the selected gain, even at the maximum sampling rate. The settling time for the very high-speed boards is gain dependent, which can affect the useful sampling rate for a given gain. No extra settling time is necessary between channels as long as the gain is constant and source impedances are low. Refer to Appendix A, Specifications, for a complete listing of settling times for each of the PCI-MIO E Series boards.

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Chapter 3 Hardware Overview

When scanning among channels at various gains, the settling times may increase. When the PGIA switches to a higher gain, the signal on the previous channel may be well outside the new, smaller range. For instance, suppose a 4 V signal is connected to channel 0 and a 1 mV signal is connected to channel 1, and suppose the PGIA is programmed to apply a gain of one to channel 0 and a gain of 100 to channel 1. When the multiplexer switches to channel 1 and the PGIA switches to a gain of 100, the new full-scale range is 100 mV (if the ADC is in unipolar mode).

The approximately 4 V step from 4 V to 1 mV is 4,000% of the new full-scale range. For a 16-bit board to settle within 0.0015% (15 ppm or 1 LSB) of the 100 mV full-scale range on channel 1, the input circuitry has to settle within 0.00004% (0.4 ppm or 1/400 LSB) of the 4 V step. It may take as long as 200 µs for the circuitry to settle this much. In general, this extra settling time is not needed when the PGIA is switching to a lower gain.

Settling times can also increase when scanning high-impedance signals due to a phenomenon called charge injection, where the analog input multiplexer injects a small amount of charge into each signal source when that source is selected. If the impedance of the source is not low enough, the effect of the charge—a voltage error—will not have decayed by the time the ADC samples the signal. For this reason, keep source impedances under 1 kΩ to perform high-speed scanning.

Due to problems with settling times, multichannel scanning is not recommended unless sampling rates are low enough or it is necessary to sample several signals as nearly simultaneously as possible. The data is much more accurate and channel-to-channel independent if you acquire data from each channel independently (for example, 100 points from channel 0, then 100 points from channel 1, then 100 points from channel 2, and so on).

PCI-MIO E Series User Manual 3-10

National Instruments Corporation

Analog Output

♦ PCI-MIO-16E-1 and PCI-MIO-16E-4

These PCI-MIO E Series boards supply two channels of analog output voltage at the I/O connector. The reference and range for the analog output circuitry is software selectable. The reference can be either internal or external, whereas the range can be either bipolar or unipolar.

♦ PCI-MIO-16XE-10

The PCI-MIO-16XE-10 supplies two channels of analog output voltage at the I/O connector. The range is software-selectable between unipolar (0 to 10 V) and bipolar (+10 V).

♦ PCI-MIO-16XE-50

The PCI-MIO-16XE-50 supplies two channels of analog output voltage at the I/O connector. The range is fixed at bipolar ±10 V.

Analog Output Reference Selection

Chapter 3 Hardware Overview

♦ PCI-MIO-16E-1 and PCI-MIO-16E-4

You can connect each D/A converter (DAC) to these PCI-MIO E Series boards’ internal reference of 10 V or to the external reference signal connected to the external reference (EXTREF) pin on the I/O connector. This signal applied to EXTREF should be within ±11 V. You do not need to configure both channels for the same mode.

Analog Output Polarity Selection

♦ PCI-MIO-16E-1 and PCI-MIO-16E-4

You can configure each analog output channel for either unipolar or bipolar output. A unipolar configuration has a range of 0 to V analog output. A bipolar configuration has a range of -V the analog output. V analog output circuitry and can be either the +10 V onboard reference or an externally supplied reference within ±11 V. You do not need to configure both channels for the same range.

National Instruments Corporation 3-11 PCI-MIO E Series User Manual

is the voltage reference used by the DACs in the

ref

to +V

at the

ref

Chapter 3 Hardware Overview

♦ PCI-MIO-16XE-10

Selecting a bipolar range for a particular DAC means that any data written to that DAC will be interpreted as two’s complement format. In two’s complement mode, data values written to the analog output channel can be either positive or negative. If you select unipolar range, data is interpreted in straight binary format. In straight binary mode, data values written to the analog output channel range must be positive.

You can configure each analog output channel for either unipolar or bipolar output. A unipolar configuration has a range of 0 to 10 V at the analog output. A bipolar configuration has a range of -10 to +10 V at the analog output. You do not need to configure both channels for the same range.

Analog Output Reglitch Selection

♦ PCI-MIO-16E-1

In normal operation, a DAC output will glitch whenever it is updated with a new value. The glitch energy differs from code to code and appears as distortion in the frequency spectrum. Each analog output of the PCI-MIO-16E-1 contains a reglitch circuit that generates uniform glitch energy at every code rather than large glitches at the major code transitions. This uniform glitch energy appears as a multiple of the update rate in the frequency spectrum. Notice that this reglitch circuit does not eliminate the glitches; it only makes them more uniform in size. Reglitching is normally disabled at startup and your software can independently enable each channel.

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National Instruments Corporation

Analog Trigger

♦ PCI-MIO-16E-1, PCI-MIO-16E-4, and PCI-MIO-16XE-10

Note: The PFI0/TRIG1 pin is an analog input when configured as an analog

trigger. Therefore, it is susceptible to crosstalk from adjacent pins, which can result in false triggering when the pin is left unconnected. To avoid false triggering, make sure this pin is connected to a low-impedance signal source (less than 1 kΩ source impedance) if you plan to enable this input via software.

Chapter 3 Hardware Overview

In addition to supporting internal software triggering and external digital triggering to initiate a data acquisition sequence, the PCI-MIO-16E-1, PCI-MIO-16E-4, and PCI-MIO-16XE-10 also support analog triggering. You can configure the analog trigger circuitry to accept either a direct analog input from the PFI0/TRIG1 pin on the I/O connector or a postgain signal from the output of the PGIA, as shown in Figure 3-5. The trigger-level range for the direct analog channel is ±10 V in 78 mV steps for the PCI-MIO-16E-1 and PCI-MIO-16E-4, and ±10 V in 4.9 mV steps for the PCI-MIO-16XE-10. The range for the post-PGIA trigger selection is simply the full-scale range of the selected channel, and the resolution is that range divided by 256 for the PCI-MIO-16E-1 and PCI-MIO-16E-4, and divided by 4,096 for the PCI-MIO-16XE-10.

Analog  Input  Channels

PFI0/TRIG1

National Instruments Corporation 3-13 PCI-MIO E Series User Manual

PGIA

ADC

Analog

Mux

Figure 3-5. Analog Trigger Block Diagram

Trigger Circuit

DAQ-STC

Chapter 3 Hardware Overview

There are five analog triggering modes available, as shown in Figures 3-6 through 3-10. You can set lowValue and highValue independently in software.

In below-low-level analog triggering mode, the trigger is generated when the signal value is less than lowValue. HighValue is unused.

lowValue

Trigger

Figure 3-6. Below-Low-Level Analog Triggering Mode

In above-high-level analog triggering mode, the trigger is generated when the signal value is greater than highValue. LowValue is unused.

highValue

Trigger

Figure 3-7. Above-High-Level Analog Triggering Mode

In inside-region analog triggering mode, the trigger is generated when the signal value is between the lowValue and the highValue.

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Chapter 3 Hardware Overview

highValue

lowValue

Trigger

Figure 3-8. Inside-Region Analog Triggering Mode

In high-hysteresis analog triggering mode, the trigger is generated when the signal value is greater than highValue, with the hysteresis specified by lowValue.

highValue

lowValue

Trigger

Figure 3-9. High-Hysteresis Analog Triggering Mode

In low-hysteresis analog triggering mode, the trigger is generated when the signal value is less than lowValue, with the hysteresis specified by

highValue.

highValue

lowValue

Trigger

Figure 3-10. Low-Hysteresis Analog Triggering Mode

National Instruments Corporation 3-15 PCI-MIO E Series User Manual

Chapter 3 Hardware Overview

Digital I/O

The analog trigger circuit generates an internal digital trigger based on the analog input signal and the user-defined trigger levels. This digital trigger can be used by any of the timing sections of the DAQ-STC, including the analog input, analog output, and general-purpose counter/timer sections. For example, the analog input section can be configured to acquire n scans after the analog input signal crosses a specific threshold. As another example, the analog output section can be configured to update its outputs whenever the analog input signal crosses a specific threshold.

The PCI-MIO E Series boards contain eight lines of digital I/O for general-purpose use. You can individually software-configure each line for either input or output. At system startup and reset, the digital I/O ports are all high impedance.

The hardware up/down control for general-purpose counters 0 and 1 are connected onboard to DIO6 and DIO7, respectively. Thus, you can use DIO6 and DIO7 to control the general-purpose counters. The up/down control signals are input only and do not affect the operation of the DIO lines.

Timing Signal Routing

The DAQ-STC provides a very flexible interface for connecting timing signals to other boards or external circuitry. Your PCI-MIO E Series board uses the RTSI bus to interconnect timing signals between boards, and the Programmable Function Input (PFI) pins on the I/O connector to connect the board to external circuitry. These connections are designed to enable the PCI-MIO E Series board to both control and be controlled by other boards and circuits.

There are a total of 13 timing signals internal to the DAQ-STC that can be controlled by an external source. These timing signals can also be controlled by signals generated internally to the DAQ-STC, and these selections are fully software configurable. For example, the signal routing multiplexer for controlling the CONVERT* signal is shown in Figure 3-11.

PCI-MIO E Series User Manual 3-16

National Instruments Corporation

RTSI Trigger <0..6>

PFI<0..9>

Sample Interval Counter TC

GPCTR0_OUT

Figure 3-11. CONVERT* Signal Routing

Chapter 3 Hardware Overview

CONVERT*

This figure shows that CONVERT* can be generated from a number of sources, including the external signals RTSI<0..6> and PFI<0..9> and the internal signals Sample Interval Counter TC and GPCTR0_OUT.

Many of these timing signals are also available as outputs on the RTSI pins, as indicated in the RTSI Triggers section later in this chapter, and on the PFI pins, as indicated in Chapter 4, Signal Connections.

Programmable Function Inputs

The 10 PFIs are connected to the signal routing multiplexer for each timing signal, and software can select one of the PFIs as the external source for a given timing signal. It is important to note that any of the PFIs can be used as an input by any of the timing signals and that multiple timing signals can use the same PFI simultaneously. This flexible routing scheme reduces the need to change physical connections to the I/O connector for different applications. You can also individually enable each of the PFI pins to output a specific internal timing signal. For example, if you need the UPDATE* signal as an output on the I/O connector, software can turn on the output driver for the PFI5/UPDATE* pin.

National Instruments Corporation 3-17 PCI-MIO E Series User Manual

Chapter 3 Hardware Overview

Board and RTSI Clocks

Many functions performed by the PCI-MIO E Series boards require a frequency timebase to generate the necessary timing signals for controlling A/D conversions, DAC updates, or general-purpose signals at the I/O connector.

A PCI-MIO E Series board can use either its internal 20 MHz timebase or a timebase received over the RTSI bus. In addition, if you configure the board to use the internal timebase, you can also program the board to drive its internal timebase over the RTSI bus to another board that is programmed to receive this timebase signal. This clock source, whether local or from the RTSI bus, is used directly by the board as the primary frequency source. The default configuration at startup is to use the internal timebase without driving the RTSI bus timebase signal. This timebase is software selectable.

RTSI Triggers

The seven RTSI trigger lines on the RTSI bus provide a very flexible interconnection scheme for any PCI-MIO E Series board sharing the RTSI bus. These bidirectional lines can drive any of eight timing signals onto the RTSI bus and can receive any of these timing signals. This signal connection scheme is shown in Figure 3-12.

PCI-MIO E Series User Manual 3-18

National Instruments Corporation

Chapter 3 Hardware Overview

DAQ-STC TRIG1 TRIG2 CONVERT* UPDATE* WFTRIG GPCTR0_SOURCE

Trigger

 

RTSI Bus Connector

Clock

RTSI Switch

switch

GPCTR0_GATE GPCTR0_OUT STARTSCAN AIGATE SISOURCE UISOURCE GPCTR1_SOURCE GPCTR1_GATE RTSI_OSC (20 MHz)

Figure 3-12. RTSI Bus Signal Connection

Refer to the Timing Connections section of Chapter 4 for a description of the signals shown in Figure 3-12.

National Instruments Corporation 3-19 PCI-MIO E Series User Manual

Chapter

Signal Connections

This chapter describes how to make input and output signal connections

to your PCI-MIO E Series board via the board I/O connector. The I/O connector for the PCI-MIO-16E-1, PCI-MIO-16E-4,

PCI-MIO-16XE-10, and PCI-MIO-16XE-50 has 68 pins that you can connect to 68-pin accessories with the SH6868 shielded cable or the R6868 ribbon cable. With the SH6850 shielded cable or R6850 ribbon cable, you can connect your board to 50-pin signal conditioning modules and terminal blocks.

I/O Connector

Figure 4-1 shows the pin assignments for the 68-pin I/O connector on the PCI-MIO E Series boards. Refer to Appendix B, Optional Cable Connector Descriptions, for the pin assignments for the 50-pin connector. A signal description follows the connector pinouts.

Warning: Connections that exceed any of the maximum ratings of input or output

signals on the PCI-MIO E Series boards can damage the PCI-MIO E Series board and the computer. Maximum input ratings for each signal are given in the Protection column of Tables 4-1, 4-2, and 4-3. National Instruments is connections.

NOT liable for any damages resulting from such signal

National Instruments Corporation 4-1 PCI-MIO E Series User Manual

Chapter 4 Signal Connections

ACH8

ACH1 AIGND ACH10

ACH3 AIGND

ACH4 AIGND ACH13

ACH6 AIGND

ACH15

DAC0OUT



PFI9/GPCTR0_GATE

DAC1OUT

EXTREF

DIO4

DGND

DIO1

DIO6

DGND

DGND PFI0/TRIG1 PFI1/TRIG2

DGND

PFI5/UPDATE*

PFI6/WFTRIG

DGND

GPCTR0_OUT

FREQ_OUT

+5 V

34 33 32 31 30 29 28 27 26 25 24 23 22 21

18 17 16 15 14

13 12

9 8 7 6 5 4 3 2 1

ACH0

AIGND

ACH9

ACH2

AIGND

ACH11

AISENSE

ACH12

ACH5 AIGND

ACH14

58 57

ACH7

AIGND AOGND

55 54

AOGND

5319

DGND

DIO0

DIO5

DGND DIO2

49 48

DIO7 DIO3

47 46

SCANCLK

EXTSTROBE*

DGND

PFI2/CONVERT*

PFI3/GPCTR1_SOURCE

PFI4/GPCTR1_GATE

GPCTR1_OUT

DGND

PFI7/STARTSCAN

PFI8/GPCTR0_SOURCE

DGND

Not available on PCI-MIO-16XE-10 or PCI-MIO-16XE-50

Figure 4-1. I/O Connector Pin Assignment for the PCI-MIO E Series Boards

PCI-MIO E Series User Manual 4-2

National Instruments Corporation

Chapter 4 Signal Connections

I/O Connector Signal Descriptions

Signal Name Reference Direction Description

AIGND — — Analog Input Ground—These pins are the reference point

for single-ended measurements in RSE configuration and

the bias current return point for differential measurements.

All three ground references—AIGND, AOGND, and

DGND—are connected together on your PCI-MIO E Series

board.

ACH<0..15> AIGND Input Analog Input Channels 0 through 15—Each channel pair,

ACH<i, i+8> (i = 0..7), can be configured as either one

differential input or two single-ended inputs.

AISENSE AIGND Input Analog Input Sense—This pin serves as the reference node

for any of channels ACH <0..15> in NRSE configuration.

DAC0OUT AOGND Output Analog Channel 0 Output—This pin supplies the voltage

output of analog output channel 0.

DAC1OUT AOGND Output Analog Channel 1 Output—This pin supplies the voltage

output of analog output channel 1.

EXTREF

A0GND Input External Reference—This is the external reference input for

the analog output circuitry. This pin is not available on the

PCI-MIO-16XE-10 or PCI-MIO-16XE-50.

AOGND — — Analog Output Ground—The analog output voltages are

referenced to this node. All three ground references—

AIGND, AOGND, and DGND—are connected together on

your PCI-MIO E Series board.

DGND — — Digital Ground—This pin supplies the reference for the

digital signals at the I/O connector as well as the +5 VDC

supply. All three ground references—AIGND, AOGND,

and DGND—are connected together on your PCI-MIO E

Series board.

DIO<0..7> DGND Input or

Output

+5 V DGND Output +5 VDC Source—These pins are fused for up to 1 A of

SCANCLK DGND Output Scan Clock—This pin pulses once for each A/D conversion

National Instruments Corporation 4-3 PCI-MIO E Series User Manual

Digital I/O signals—DIO6 and 7 can control the up/down

signal of general-purpose counters 0 and 1, respectively.

+5 V supply. The fuse is self-resetting.

in the scanning modes when enabled. The low-to-high edge

indicates when the input signal can be removed from the

input or switched to another signal.

Chapter 4 Signal Connections

Signal Name Reference Direction Description (Continued)

EXTSTROBE* DGND Output External Strobe—This output can be toggled under software

control to latch signals or trigger events on external devices.

PFI0/TRIG1 DGND Input

Output

PFI1/TRIG2 DGND Input

Output

PFI2/CONVERT* DGND Input

Output

PFI3/GPCTR1_SOURCE DGND Input

PFI0/Trigger 1—As an input, this is either one of the Programmable Function Inputs (PFIs) or the source for the hardware analog trigger. PFI signals are explained in the Timing Connections section later in this chapter. The hardware analog trigger is explained in the Analog Trigger section in Chapter 2. Analog trigger is available only on the PCI-MIO-16E-1, PCI-MIO-16E-4, and the PCI-MIO-16XE-10.

As an output, this is the TRIG1 signal. In posttrigger data acquisition sequences, a low-to-high transition indicates the initiation of the acquisition sequence. In pretrigger applications, a low-to-high transition indicates the initiation of the pretrigger conversions.

PFI1/Trigger 2—As an input, this is one of the PFIs.

As an output, this is the TRIG2 signal. In pretrigger applications, a low-to-high transition indicates the initiation of the posttrigger conversions. TRIG2 is not used in posttrigger applications.

PFI2/Convert—As an input, this is one of the PFIs.

As an output, this is the CONVERT* signal. A high-to-low edge on CONVERT* indicates that an A/D conversion is occurring.

PFI3/Counter 1 Source—As an input, this is one of the PFIs.

Output

PFI4/GPCTR1_GATE DGND Input

Output

GPCTR1_OUT DGND Output Counter 1 Output—This output is from the general-purpose

PCI-MIO E Series User Manual 4-4

As an output, this is the GPCTR1_SOURCE signal. This signal reflects the actual source connected to the general-purpose counter 1.

PFI4/Counter 1 Gate—As an input, this is one of the PFIs.

As an output, this is the GPCTR1_GATE signal. This signal reflects the actual gate signal connected to the general-purpose counter 1.

counter 1 output.

National Instruments Corporation

Signal Name Reference Direction Description (Continued)

Chapter 4 Signal Connections

PFI5/UPDATE* DGND Input

Output

PFI6/WFTRIG DGND Input

Output

PFI7/STARTSCAN DGND Input

Output

PFI8/GPCTR0_SOURCE DGND Input

Output

PFI9/GPCTR0_GATE DGND Input

Output

PFI5/Update—As an input, this is one of the PFIs.

As an output, this is the UPDATE* signal. A high-to-low

edge on UPDATE* indicates that the analog output primary

group is being updated.

PFI6/Waveform Trigger—As an input, this is one of the

PFIs.

As an output, this is the WFTRIG signal. In timed analog

output sequences, a low-to-high transition indicates the

initiation of the waveform generation.

PFI7/Start of Scan—As an input, this is one of the PFIs.

As an output, this is the STARTSCAN signal. This pin

pulses once at the start of each analog input scan in the

interval scan. A low-to-high transition indicates the start of

the scan.

PFI8/Counter 0 Source—As an input, this is one of the

PFIs.

As an output, this is the GPCTR0_SOURCE signal. This

signal reflects the actual source connected to the

general-purpose counter 0.

PFI9/Counter 0 Gate—As an input, this is one of the PFIs.

As an output, this is the GPCTR0_GATE signal. This signal

reflects the actual gate signal connected to the

general-purpose counter 0.

GPCTR0_OUT DGND Output Counter 0 Output—This output is from the general-purpose

counter 0 output.

FREQ_OUT DGND Output Frequency Output—This output is from the frequency

generator output.

EXTREF is not available on the PCI-MIO-16XE-10 or the PCI-MIO-16XE-50.

National Instruments Corporation 4-5 PCI-MIO E Series User Manual

Chapter 4 Signal Connections

Table 4-1. I/O Signal Summary, PCI-MIO-16E-1 and PCI-MIO-16E-4

Table 4-1 shows the I/O signal summary for the PCI-MIO-16E-1 and

PCI-MIO-16E-4.

Signal Name Signal

Type and Direction

ACH<0..15> AI 100 GΩ

AISENSE, AISENSE2 AI 100 GΩ

AIGND AO — — — — — —

DAC0OUT AO 0.1 Ω Short-circuit

DAC1OUT AO 0.1 Ω Short-circuit

EXTREF AI 10 kΩ 25/15 — — — —

AOGND AO — — — — — —

DGND DO — — — — — —

VCC DO 0.1 Ω Short-circuit

Impedance

Input/

Output

in parallel with 100 pF

Protection

(Volts) On/Off

25/15 — — — ±200 pA

to ground

Source

(mA at V)

5 at 10 5 at -10 20

1A — — —

Sink (mA

at V)

Rise

Time

(ns)

V/µs

Bias

—

DIO<0..7> DIO — Vcc +0.5 13 at (Vcc -0.4) 24 at

0.4

SCANCLK DO — — 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

EXTSTROBE* DO — — 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI0/TRIG1 AI/DIO 10 kΩ Vcc +0.5/±35 3.5 at (Vcc -0.4) 5 at 0.4 1.5 9 kΩ pu

PFI1/TRIG2 DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI2/CONVERT* DIO — V

PCI-MIO E Series User Manual 4-6

+0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

National Instruments Corporation

1.1 50 kΩ pu

and 10 kΩ pd

Chapter 4 Signal Connections

Table 4-1. I/O Signal Summary, PCI-MIO-16E-1 and PCI-MIO-16E-4 (Continued)

Signal Name Signal

Type and

Direction

PFI3/GPCTR1_SOURCE DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI4/GPCTR1_GATE DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

GPCTR1_OUT DO — — 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI5/UPDATE* DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI6/WFTRIG DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI7/STARTSCAN DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI8/GPCTR0_SOURCE DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI9/GPCTR0_GATE DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

GPCTR0_OUT DO — — 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

FREQ_OUT DO — — 3.5 at (Vcc-0.4) 5 at 0.4 1.5 50 kΩ pu

AI = Analog Input DIO = Digital Input/Output pu = pullup AO = Analog Output DO = Digital Output AI/DIO = Analog/Digital Input/Output

Note: The tolerance on the 50 kΩ pullup and pulldown resistors is very large. Actual value may range between

17 kΩ and 100 kΩ.

Impedance

Input/ Output

Protection

(Volts)

On/Off

Source

(mA at V)

Sink

(mA

at V)

Rise

Time

(ns)

Bias

Table 4-2 shows the I/O signal summary for the PCI-MIO-16XE-10.

Table 4-2. I/O Signal Summary, PCI-MIO-16XE-10

Signal Name Signal

Type and

Direction

ACH<0..15> AI 100 GΩ

AISENSE AI 100 GΩ

National Instruments Corporation 4-7 PCI-MIO E Series User Manual

Impedance

Input/

Output

in parallel with 100 pF

Protection

(Volts)

On/Off

25/15 — — — ±1 nA

Source

(mA at V)

Sink (mA

at V)

Rise

Time

(ns)

Bias

Chapter 4 Signal Connections

Table 4-2. I/O Signal Summary, PCI-MIO-16XE-10 (Continued)

Signal Name Signal

Type and Direction

AIGND AO — — — — — —

DAC0OUT AO 0.1 Ω Short-circuit

DAC1OUT AO 0.1 Ω Short-circuit

AOGND AO — — — — — —

DGND DO — — — — — —

VCC DO 0.1 Ω Short-circuit

DIO<0..7> DIO — Vcc +0.5 13 at (Vcc -0.4) 24 at 0.4 1.1 50 kΩ pu

SCANCLK DO — — 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

EXTSTROBE* DO — — 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI0/TRIG1 DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 9 kΩ pu

PFI1/TRIG2 DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

Impedance

Input/ Output

Protection

(Volts) On/Off

to ground

Source

(mA at V)

5 at 10 5 at -10 5 V/ µs—

1 A — — —

Sink (mA

at V)

Rise

Time

(ns)

and 10 kΩ pd

Bias

PFI2/CONVERT* DIO — V

PFI3/GPCTR1_SOURCE DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI4/GPCTR1_GATE DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

GPCTR1_OUT DO — — 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI5/UPDATE* DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI6/WFTRIG DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI7/STARTSCAN DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI8/GPCTR0_SOURCE DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI9/GPCTR0_GATE DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PCI-MIO E Series User Manual 4-8

+0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

National Instruments Corporation

Chapter 4 Signal Connections

Table 4-2. I/O Signal Summary, PCI-MIO-16XE-10 (Continued)

Signal Name Signal

Type and

Direction

GPCTR0_OUT DO — — 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

FREQ_OUT DO — — 3.5 at (Vcc-0.4) 5 at 0.4 1.5 50 kΩ pu

AI = Analog Input DIO = Digital Input/Output pu = pullup AO = Analog Output DO = Digital Output

Note: The tolerance on the 50 kΩ pullup and pulldown resistors is very large. Actual value may range between

17 kΩ and 100 kΩ.

Impedance

Input/

Output

Protection

(Volts)

On/Off

Source

(mA at V)

Sink (mA

at V)

Rise

Time

(ns)

Bias

Table 4-3 shows the I/O signal summary for the PCI-MIO-16XE-50.

Table 4-3. I/O Signal Summary, PCI-MIO-16XE-50

Signal Name Signal

Type and

Direction

ACH<0..15> AI 20 GΩ in

AISENSE AI 20 GΩ in

Impedance

Input/

Output

parallel with 100 pF

Protection

(Volts)

On/Off

25/15 — — — ±3 nA

Source

(mA at V)

Sink (mA

at V)

Rise

Time

(ns)

Bias

AIGND AO — — — — — —

DAC0OUT AO 0.1 Ω Short-circuit

to ground

DAC1OUT AO 0.1 Ω Short-circuit

to ground

AOGND AO — — — — — —

DGND DO — — — — — —

VCC DO 0.1 Ω Short-circuit

to ground

DIO<0..7> DIO — Vcc +0.5 13 at (Vcc -0.4) 24 at 0.4 1.1 50 kΩ pu

National Instruments Corporation 4-9 PCI-MIO E Series User Manual

5 at -10 5 at -10 2 V/µs —

1A — — —

Chapter 4 Signal Connections

Table 4-3. I/O Signal Summary, PCI-MIO-16XE-50 (Continued)

Signal Name Signal

Type and Direction

SCANCLK DO — — 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

EXTSTROBE* DO — — 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI0/TRIG1 DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI1/TRIG2 DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI2/CONVERT* DIO — V

PFI3/GPCTR1_SOURCE DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI4/GPCTR1_GATE DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

GPCTR1_OUT DO — — 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI5/UPDATE* DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI6/WFTRIG DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI7/STARTSCAN DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI8/GPCTR0_SOURCE DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

PFI9/GPCTR0_GATE DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

Impedance

Input/ Output

Protection

(Volts) On/Off

+0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

Source

(mA at V)

Sink (mA

at V)

Rise

Time

(ns)

Bias

GPCTR0_OUT DO — — 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu

FREQ_OUT DO — — 3.5 at (Vcc-0.4) 5 at 0.4 1.5 50 kΩ pu

AI = Analog Input DIO = Digital Input/Output pu = pullup AO = Analog Output DO = Digital Output

PCI-MIO E Series User Manual 4-10

National Instruments Corporation

Analog Input Signal Connections

The analog input signals for the PCI-MIO E Series boards are ACH<0..15>, AISENSE, and AIGND. The ACH<0..15> signals are tied to the 16 analog input channels of your PCI-MIO E Series board. In single-ended mode, signals connected to ACH<0..15> are routed to the positive input of the board PGIA. In differential mode, signals connected to ACH<0..7> are routed to the positive input of the PGIA, and signals connected to ACH<8..15> are routed to the negative input of the PGIA.

Warning: Exceeding the differential and common-mode input ranges distorts your

input signals. Exceeding the maximum input voltage rating can damage the PCI-MIO E Series board and the computer. National Instruments is

NOT liable for any damages resulting from such signal connections. The

maximum input voltage ratings are listed in the Protection column of Tables 4-1 to 4-3.

In NRSE mode, the AISENSE signal is connected internally to the negative input of the PCI-MIO E Series board PGIA when their corresponding channels are selected. In DIFF and RSE modes, this signal is left unconnected.

Chapter 4 Signal Connections

AIGND is an analog input common signal that is routed directly to the ground tie point on the PCI-MIO E Series boards. You can use this signal for a general analog ground tie point to your PCI-MIO E Series board if necessary.

Connection of analog input signals to your PCI-MIO E Series board depends on the configuration of the analog input channels you are using and the type of input signal source. With the different configurations, you can use the PGIA in different ways. Figure 4-2 shows a diagram of your PCI-MIO E Series board PGIA.

National Instruments Corporation 4-11 PCI-MIO E Series User Manual

Chapter 4 Signal Connections

Instrumentation

in+

Amplifier

PGIA

in-

Measured

Voltage

Vm = [V

Figure 4-2. PCI-MIO E Series PGIA

The PGIA applies gain and common-mode voltage rejection and presents high input impedance to the analog input signals connected to your PCI-MIO E Series board. Signals are routed to the positive and negative inputs of the PGIA through input multiplexers on the board. The PGIA converts two input signals to a signal that is the difference between the two input signals multiplied by the gain setting of the amplifier. The amplifier output voltage is referenced to the ground for the board. Your PCI-MIO E Series board A/D converter (ADC) measures this output voltage when it performs A/D conversions.

in+

- V

]* Gain

in-

You must reference all signals to ground either at the source device or at the board. If you have a floating source, you should reference the signal to ground by using the RSE input mode or the DIFF input configuration with bias resistors (see the Differential Connections for Nonreferenced or Floating Signal Sources section later in this chapter). If you have a grounded source, you should not reference the signal to AIGND. You can avoid this reference by using DIFF or NRSE input configurations.

PCI-MIO E Series User Manual 4-12

National Instruments Corporation

Types of Signal Sources

When configuring the input channels and making signal connections, you must first determine whether the signal sources are floating or ground-referenced. The following sections describe these two types of signals.

Floating Signal Sources

A floating signal source is not connected in any way to the building ground system but, rather, has an isolated ground-reference point. Some examples of floating signal sources are outputs of transformers, thermocouples, battery-powered devices, optical isolator outputs, and isolation amplifiers. An instrument or device that has an isolated output is a floating signal source. You must tie the ground reference of a floating signal to your PCI-MIO E Series board analog input ground to establish a local or onboard reference for the signal. Otherwise, the measured input signal varies as the source floats out of the common-mode input range.

Ground-Referenced Signal Sources

A ground-referenced signal source is connected in some way to the building system ground and is, therefore, already connected to a common ground point with respect to the PCI-MIO E Series board, assuming that the computer is plugged into the same power system. Nonisolated outputs of instruments and devices that plug into the building power system fall into this category.

Chapter 4 Signal Connections

The difference in ground potential between two instruments connected to the same building power system is typically between 1 and 100 mV but can be much higher if power distribution circuits are not properly connected. If a grounded signal source is improperly measured, this difference may appear as an error in the measurement. The connection instructions for grounded signal sources are designed to eliminate this ground potential difference from the measured signal.

Input Configurations

You can configure your PCI-MIO E Series board for one of three input modes—NRSE, RSE, or DIFF. The following sections discuss the use of single-ended and differential measurements and considerations for measuring both floating and ground-referenced signal sources.

National Instruments Corporation 4-13 PCI-MIO E Series User Manual

Chapter 4 Signal Connections

Figure 4-3 summarizes the recommended input configuration for both types of signal sources.

Signal Source Type

Input

Differential

(DIFF)

Single-Ended —

Ground

Referenced

(RSE)

Floating Signal Source

(Not Connected to Building Ground)

Examples

• Ungrounded Thermocouples

• Signal conditioning with isolated outputs

• Battery devices

ACH(+)

ACH (-)

AIGND

See text for information on bias resistors.

ACH

AIGND

Grounded Signal Source

Examples

• Plug-in instruments with nonisolated outputs

NOT RECOMMENDED

+ Vg -

ACH(+)

ACH (-)

ACH

AIGND

Single-Ended —

Nonreferenced

(NRSE)

ACH

AISENSE

See text for information on bias resistors.

Figure 4-3. Summary of Analog Input Connections

PCI-MIO E Series User Manual 4-14

Ground-loop losses, Vg, are added to measured signal

AIGND

National Instruments Corporation

ACH

AISENSE

AIGND

Chapter 4 Signal Connections

Differential Connection Considerations (DIFF Input Configuration)

A differential connection is one in which the PCI-MIO E Series board analog input signal has its own reference signal or signal return path. These connections are available when the selected channel is configured in DIFF input mode. The input signal is tied to the positive input of the PGIA, and its reference signal, or return, is tied to the negative input of the PGIA.

When you configure a channel for differential input, each signal uses two multiplexer inputs—one for the signal and one for its reference signal. Therefore, with a differential configuration for every channel, up to eight analog input channels are available.

You should use differential input connections for any channel that meets any of the following conditions:

• The input signal is low level (less than 1 V).

• The leads connecting the signal to the PCI-MIO E Series board are greater than 10 ft (3 m).

• The input signal requires a separate ground-reference point or return signal.

• The signal leads travel through noisy environments.

Differential signal connections reduce picked up noise and increase common-mode noise rejection. Differential signal connections also allow input signals to float within the common-mode limits of the PGIA.

National Instruments Corporation 4-15 PCI-MIO E Series User Manual

Chapter 4 Signal Connections

Ground-

Referenced

Signal

Source

Differential Connections for Ground-Referenced Signal Sources

Figure 4-4 shows how to connect a ground-referenced signal source to a channel on the PCI-MIO E Series board configured in DIFF input mode.

ACH<0..7>

Instrumentation

Amplifier

Common-

Mode

Noise and



Ground

Potential

I/O Connector

ACH<8..15>

PGIA

Input Multiplexers

AISENSE

AIGND

Selected Channel in DIFF Configuration

Measured

Voltage

Figure 4-4. Differential Input Connections for Ground-Referenced Signals

With this type of connection, the PGIA rejects both the common-mode noise in the signal and the ground potential difference between the signal source and the PCI-MIO E Series board ground, shown as Vcm in Figure 4-4.

PCI-MIO E Series User Manual 4-16

National Instruments Corporation

Floating

Signal

Source

Bias

Current

Return

Paths

Chapter 4 Signal Connections

Differential Connections for Nonreferenced or Floating Signal Sources

Figure 4-5 shows how to connect a floating signal source to a channel on the PCI-MIO E Series board configured in DIFF input mode.

ACH<0..7>

bias resistors  (see text)

ACH<8..15>

Input Multiplexers

Instrumentation

Amplifier

PGIA

Measured

Voltage

AISENSE

AIGND

I/O Connector

Selected Channel in DIFF Configuration

Figure 4-5. Differential Input Connections for Nonreferenced Signals

Figure 4-5 shows two bias resistors connected in parallel with the signal leads of a floating signal source. If you do not use the resistors and the source is truly floating, the source is not likely to remain within the common-mode signal range of the PGIA, and the PGIA will saturate, causing erroneous readings. You must reference the source to AIGND. The easiest way is simply to connect the positive side of the signal to the positive input of the PGIA and connect the negative side of the signal to AIGND as well as to the negative input of the PGIA, without any resistors at all. This connection works well for DC-coupled sources with low source impedance (less than 100 Ω).

National Instruments Corporation 4-17 PCI-MIO E Series User Manual

Chapter 4 Signal Connections

However, for larger source impedances, this connection leaves the differential signal path significantly out of balance. Noise that couples electrostatically onto the positive line does not couple onto the negative line because it is connected to ground. Hence, this noise appears as a differential-mode signal instead of a common-mode signal, and the PGIA does not reject it. In this case, instead of directly connecting the negative line to AIGND, connect it to AIGND through a resistor that is about 100 times the equivalent source impedance. The resistor puts the signal path nearly in balance, so that about the same amount of noise couples onto both connections, yielding better rejection of electrostatically coupled noise. Also, this configuration does not load down the source (other than the very high input impedance of the PGIA).

You can fully balance the signal path by connecting another resistor of the same value between the positive input and AIGND, as shown in Figure 4-5. This fully-balanced configuration offers slightly better noise rejection but has the disadvantage of loading the source down with the series combination (sum) of the two resistors. If, for example, the source impedance is 2 kΩ and each of the two resistors is 100 kΩ, the resistors load down the source with 200 kΩ and produce a -1% gain error.

Both inputs of the PGIA require a DC path to ground in order for the PGIA to work. If the source is AC coupled (capacitively coupled), the PGIA needs a resistor between the positive input and AIGND. If the source has low impedance, choose a resistor that is large enough not to significantly load the source but small enough not to produce significant input offset voltage as a result of input bias current (typically 100 kΩ to 1 MΩ). In this case, you can tie the negative input directly to AIGND. If the source has high output impedance, you should balance the signal path as previously described using the same value resistor on both the positive and negative inputs; you should be aware that there is some gain error from loading down the source.

Single-Ended Connection Considerations

A single-ended connection is one in which the PCI-MIO E Series board analog input signal is referenced to a ground that can be shared with other input signals. The input signal is tied to the positive input of the PGIA, and the ground is tied to the negative input of the PGIA.

When every channel is configured for single-ended input, up to 16 analog input channels are available.

PCI-MIO E Series User Manual 4-18

National Instruments Corporation

Chapter 4 Signal Connections

You can use single-ended input connections for any input signal that meets the following conditions:

• The input signal is high level (greater than 1 V).

• The leads connecting the signal to the PCI-MIO E Series board are less than 10 ft (3 m).

• The input signal can share a common reference point with other signals.

DIFF input connections are recommended for greater signal integrity for any input signal that does not meet the preceding conditions.

You can software configure the PCI-MIO E Series board channels for two different types of single-ended connections—RSE configuration and NRSE configuration. The RSE configuration is used for floating signal sources; in this case, the PCI-MIO E Series board provides the reference ground point for the external signal. The NRSE input configuration is used for ground-referenced signal sources; in this case, the external signal supplies its own reference ground point and the PCI-MIO E Series board should not supply one.

In single-ended configurations, more electrostatic and magnetic noise couples into the signal connections than in differential configurations. The coupling is the result of differences in the signal path. Magnetic coupling is proportional to the area between the two signal conductors. Electrical coupling is a function of how much the electric field differs between the two conductors.

National Instruments Corporation 4-19 PCI-MIO E Series User Manual

Chapter 4 Signal Connections

Floating

Signal

Source

I/O Connector

Single-Ended Connections for Floating Signal Sources (RSE Configuration)

Figure 4-6 shows how to connect a floating signal source to a channel

on the PCI-MIO E Series board configured for RSE mode.

ACH<0..15>

 



Input Multiplexers



AISENSE



AIGND

Selected Channel in RSE Configuration

Instrumentation

Amplifier

PGIA

Measured

Voltage

Figure 4-6. Single-Ended Input Connections for Nonreferenced or Floating Signals

Single-Ended Connections for Grounded Signal Sources (NRSE Configuration)

To measure a grounded signal source with a single-ended configuration, you must configure your PCI-MIO E Series board in the NRSE input configuration. The signal is then connected to the positive input of the PCI-MIO E Series PGIA, and the signal local ground reference is connected to the negative input of the PGIA. The ground point of the signal should, therefore, be connected to the AISENSE pin. Any potential difference between the PCI-MIO E Series ground and the signal ground appears as a common-mode signal at both the positive and negative inputs of the PGIA, and this difference is rejected by the amplifier. If the input circuitry of a PCI-MIO E Series board were referenced to ground, in this situation as in the RSE input configuration, this difference in ground potentials would appear as an error in the measured voltage.

PCI-MIO E Series User Manual 4-20

National Instruments Corporation

Chapter 4 Signal Connections

Figure 4-7 shows how to connect a grounded signal source to a channel on the PCI-MIO E Series board configured for NRSE mode.

ACH<0..15>



Input Multiplexers

AIGND

Selected Channel in NRSE Configuration

AISENSE

Ground-

Referenced

Signal

Source

Common-

Mode Noise

and Ground

Potential

I/O Connector

 



 

Figure 4-7. Single-Ended Input Connections for Ground-Referenced Signals

Common-Mode Signal Rejection Considerations

Figures 4-4 and 4-7 show connections for signal sources that are already referenced to some ground point with respect to the PCI-MIO E Series board. In these cases, the PGIA can reject any voltage caused by ground potential differences between the signal source and the board. In addition, with differential input connections, the PGIA can reject common-mode noise pickup in the leads connecting the signal sources to the board. The PGIA can reject common-mode signals as long as

PCI-MIO-16XE-50 has the additional restriction that (V added to the gain times (V At gains of 10 and 100, this is roughly equivalent to restricting the two input voltages to within ±8 V of AIGND.

and V

(input signals) are both within ±11 V of AIGND. The

- V

) must be within ±26 V of AIGND.

Instrumentation

Amplifier

PGIA

Measured

Voltage

+ V

)

National Instruments Corporation 4-21 PCI-MIO E Series User Manual

Chapter 4 Signal Connections

Analog Output Signal Connections

The analog output signals are DAC0OUT, DAC1OUT, EXTREF, and AOGND. EXTREF is not available on the PCI-MIO-16XE-10 or PCI-MIO-16XE-50.

DAC0OUT is the voltage output signal for analog output channel 0. DAC1OUT is the voltage output signal for analog output channel 1.

EXTREF is the external reference input for both analog output channels. You must configure each analog output channel individually for external reference selection in order for the signal applied at the external reference input to be used by that channel. If you do not specify an external reference, the channel will use the internal reference. You

cannot use an external analog output reference with the PCI-MIO-16XE-10 or PCI-MIO-16XE-50. Analog output configuration options are explained in the Analog Output section in Chapter 3, Hardware Overview. The following ranges and ratings apply to the

EXTREF input:

• Usable input voltage range: ±11 V peak with respect to AOGND

• Absolute maximum ratings: ±15 V peak with respect to AOGND

AOGND is the ground reference signal for both analog output channels and the external reference signal.

Figure 4-8 shows how to make analog output connections and the external reference input connection to your PCI-MIO E Series board.

PCI-MIO E Series User Manual 4-22

National Instruments Corporation

External Reference Signal (Optional)

Chapter 4 Signal Connections

EXTREF

DAC0OUT

ref

Load

VOUT 0

AOGND

Channel 0

Load

VOUT 1

DAC1OUT

Figure 4-8. Analog Output Connections

The external reference signal can be either a DC or an AC signal. The board multiplies this reference signal by the DAC code (divided by the full-scale DAC code) to generate the output voltage.

Digital I/O Signal Connections

The digital I/O signals are DIO<0..7> and DGND. DIO<0..7> are the signals making up the DIO port, and DGND is the ground reference signal for the DIO port. You can program all lines individually to be inputs or outputs.

Warning: Exceeding the maximum input voltage ratings, which are listed in

Tables 4-1, 4-2, and 4-3 can damage the PCI-MIO E Series board and the computer. National Instruments is from such signal connections.

Channel 1

Analog Output Channels

E Series Board

NOT liable for any damages resulting

National Instruments Corporation 4-23 PCI-MIO E Series User Manual

Chapter 4 Signal Connections

+5 V

LED

Figure 4-9 shows signal connections for three typical digital I/O

applications.

DIO<4..7>

+5 V

TTL Signal

DIO<0..3>

Switch

DGND

I/O Connector

E Series Board

Figure 4-9. Digital I/O Connections

Figure 4-9 shows DIO<0..3> configured for digital input and DIO<4..7> configured for digital output. Digital input applications include receiving TTL signals and sensing external device states such as the state of the switch shown in the figure. Digital output applications include sending TTL signals and driving external devices such as the LED shown in the figure.

PCI-MIO E Series User Manual 4-24

National Instruments Corporation

Power Connections

Two pins on the I/0 connector supply +5 V from the computer power supply via a self-resetting fuse. The fuse will reset automatically within a few seconds after the overcurrent condition is removed. These pins are referenced to DGND and can be used to power external digital circuitry.

• Power rating +4.65 to +5.25 VDC at 1 A

Warning: Under no circumstances should you connect these +5 V power pins directly

to analog or digital ground or to any other voltage source on the PCI-MIO E Series board or any other device. Doing so can damage the PCI-MIO E Series board and the computer. National Instruments is NOT liable for damages resulting from such a connection.

Timing Connections

Warning: Exceeding the maximum input voltage ratings, which are listed in

Tables 4-1, 4-2, and 4-3 can damage the PCI-MIO E Series board and the computer. National Instruments is from such signal connections.

Chapter 4 Signal Connections

NOT liable for any damages resulting

All external control over the timing of your PCI-MIO E Series board is routed through the 10 programmable function inputs labeled PFI0 through PFI9. These signals are explained in detail in the next section, Programmable Function Input Connections. These PFIs are bidirectional; as outputs they are not programmable and reflect the state of many DAQ, waveform generation, and general-purpose timing signals. There are five other dedicated outputs for the remainder of the timing signals. As inputs, the PFI signals are programmable and can control any DAQ, waveform generation, and general-purpose timing signals.

The DAQ signals are explained in the DAQ Timing Connections section later in this chapter. The waveform generation signals are explained in the Waveform Generation Timing Connections section later in this chapter. The general-purpose timing signals are explained in the General-Purpose Timing Signal Connections section later in this chapter.

National Instruments Corporation 4-25 PCI-MIO E Series User Manual

Chapter 4 Signal Connections

All digital timing connections are referenced to DGND. This reference is demonstrated in Figure 4-10, which shows how to connect an external TRIG1 source and an external CONVERT* source to two PCI-MIO E Series board PFI pins.

PFI0/TRIG1

PFI2/CONVERT*

TRIG1

Source

CONVERT*

Source

I/O Connector

Figure 4-10. Timing I/O Connections

Programmable Function Input Connections

There are a total of 13 internal timing signals that you can externally control from the PFI pins. The source for each of these signals is software-selectable from any of the PFIs when you want external control. This flexible routing scheme reduces the need to change the physical wiring to the board I/O connector for different applications requiring alternative wiring.

You can individually enable each of the PFI pins to output a specific internal timing signal. For example, if you need the CONVERT* signal as an output on the I/O connector, software can turn on the output driver for the PFI2/CONVERT* pin. Be careful not to drive a PFI signal externally when it is configured as an output.

DGND

E Series Board

PCI-MIO E Series User Manual 4-26

National Instruments Corporation

As an input, you can individually configure each PFI for edge or level detection and for polarity selection, as well. You can use the polarity selection for any of the 13 timing signals, but the edge or level detection will depend upon the particular timing signal being controlled. The detection requirements for each timing signal are listed within the section that discusses that individual signal.

In edge-detection mode, the minimum pulse width required is 10 ns. This applies for both rising-edge and falling-edge polarity settings. There is no maximum pulse-width requirement in edge-detect mode.

In level-detection mode, there are no minimum or maximum pulse-width requirements imposed by the PFIs themselves, but there may be limits imposed by the particular timing signal being controlled. These requirements are listed later in this chapter.

DAQ Timing Connections

The DAQ timing signals are SCANCLK, EXTSTROBE*, TRIG1, TRIG2, STARTSCAN, CONVERT*, AIGATE, and SISOURCE.

Posttriggered data acquisition allows you to view only data that is acquired after a trigger event is received. A typical posttriggered DAQ sequence is shown in Figure 4-11. Pretriggered data acquisition allows you to view data that is acquired before the trigger of interest in addition to data acquired after the trigger. Figure 4-12 shows a typical pretriggered DAQ sequence. The description for each signal shown in these figures is included later in this chapter.

Chapter 4 Signal Connections

TRIG1

STARTSCAN

CONVERT*

Scan Counter

Figure 4-11. Typical Posttriggered Acquisition

National Instruments Corporation 4-27 PCI-MIO E Series User Manual

13042

Chapter 4 Signal Connections

TRIG1

TRIG2

STARTSCAN

CONVERT*

Scan Counter

Don't Care

01231 0222

Figure 4-12. Typical Pretriggered Acquisition

SCANCLK Signal

SCANCLK is an output-only signal that generates a pulse with the leading edge occurring approximately 50 to 100 ns after an A/D conversion begins. The polarity of this output is software-selectable but is typically configured so that a low-to-high leading edge can clock external analog input multiplexers indicating when the input signal has been sampled and can be removed. This signal has a 400 to 500 ns pulse width and is software enabled. Figure 4-13 shows the timing for the SCANCLK signal.

CONVERT*

SCANCLK

Figure 4-13. SCANCLK Signal Timing

PCI-MIO E Series User Manual 4-28

= 50 to 100 ns

= 400 to 500 ns

National Instruments Corporation

Chapter 4 Signal Connections

EXTSTROBE* Signal

EXTSTROBE* is an output-only signal that generates either a single pulse or a sequence of eight pulses in the hardware-strobe mode. An external device can use this signal to latch signals or to trigger events. In the single-pulse mode, software controls the level of the EXTSTROBE* signal. A 10 µs and a 1.2 µs clock are available for generating a sequence of eight pulses in the hardware-strobe mode. Figure 4-14 shows the timing for the hardware-strobe mode EXTSTROBE* signal.

= 600 ns or 5 µs

Figure 4-14. EXTSTROBE* Signal Timing

TRIG1 Signal

Any PFI pin can externally input the TRIG1 signal, which is available as an output on the PFI0/TRIG1 pin.

Refer to Figures 4-11 and 4-12 for the relationship of TRIG1 to the DAQ sequence.

As an input, the TRIG1 signal is configured in the edge-detection mode. You can select any PFI pin as the source for TRIG1 and configure the polarity selection for either rising or falling edge. The selected edge of the TRIG1 signal starts the data acquisition sequence for both posttriggered and pretriggered acquisitions. The PCI-MIO-16E-1, PCI-MIO-16E-4, and PCI-MIO-16XE-10 support analog triggering on the PFI0/TRIG1 pin. See Chapter 3, Hardware Overview, for more information on analog triggering.

National Instruments Corporation 4-29 PCI-MIO E Series User Manual

Chapter 4 Signal Connections

Rising-edge polarity

Falling-edge polarity

As an output, the TRIG1 signal reflects the action that initiates a DAQ sequence. This is true even if the acquisition is being externally triggered by another PFI. The output is an active high pulse with a pulse width of 50 to 100 ns. This output is set to tri-state at startup.

Figures 4-15 and 4-16 show the input and output timing requirements for the TRIG1 signal.

= 10 ns minimum

Figure 4-15. TRIG1 Input Signal Timing

Figure 4-16. TRIG1 Output Signal Timing

The board also uses the TRIG1 signal to initiate pretriggered DAQ operations. In most pretriggered applications, the TRIG1 signal is generated by a software trigger. Refer to the TRIG2 signal description for a complete description of the use of TRIG1 and TRIG2 in a pretriggered DAQ operation.

PCI-MIO E Series User Manual 4-30

= 50-100 ns

National Instruments Corporation

Chapter 4 Signal Connections

TRIG2 Signal

Any PFI pin can externally input the TRIG2 signal, which is available as an output on the PFI1/TRIG2 pin.

Refer to Figure 4-12 for the relationship of TRIG2 to the DAQ sequence.

As an input, the TRIG2 signal is configured in the edge-detection mode. You can select any PFI pin as the source for TRIG2 and configure the polarity selection for either rising or falling edge. The selected edge of the TRIG2 signal initiates the posttriggered phase of a pretriggered acquisition sequence. In pretriggered mode, the TRIG1 signal initiates the data acquisition. The scan counter indicates the minimum number of scans before TRIG2 can be recognized. After the scan counter decrements to zero, it is loaded with the number of posttrigger scans to acquire while the acquisition continues. The board ignores the TRIG2 signal if it is asserted prior to the scan counter decrementing to zero. After the selected edge of TRIG2 is received, the board will acquire a fixed number of scans and the acquisition will stop. This mode acquires data both before and after receiving TRIG2.

As an output, the TRIG2 signal reflects the posttrigger in a pretriggered acquisition sequence. This is true even if the acquisition is being externally triggered by another PFI. The TRIG2 signal is not used in posttriggered data acquisition. The output is an active high pulse with a pulse width of 50 to 100 ns. This output is set to tri-state at startup.

Figures 4-17 and 4-18 show the input and output timing requirements for the TRIG2 signal.

Rising-edge polarity

Falling-edge polarity

= 10 ns minimum

Figure 4-17. TRIG2 Input Signal Timing

National Instruments Corporation 4-31 PCI-MIO E Series User Manual

Chapter 4 Signal Connections

= 50-100 ns

Figure 4-18. TRIG2 Output Signal Timing

STARTSCAN Signal

Any PFI pin can externally input the STARTSCAN signal, which is available as an output on the PFI7/STARTSCAN pin.

Refer to Figures 4-11 and 4-12 for the relationship of STARTSCAN to the DAQ sequence.

As an input, the STARTSCAN signal is configured in the edge-detection mode. You can select any PFI pin as the source for STARTSCAN and configure the polarity selection for either rising or falling edge. The selected edge of the STARTSCAN signal initiates a scan. The sample interval counter starts if you select internally triggered CONVERT*.

As an output, the STARTSCAN signal reflects the actual start pulse that initiates a scan. This is true even if the starts are being externally triggered by another PFI. You have two output options. The first is an active high pulse with a pulse width of 50 to 100 ns, which indicates the start of the scan. The second action is an active high pulse that terminates at the start of the last conversion in the scan, which indicates a scan in progress. STARTSCAN will be deasserted t conversion in the scan is initiated. This output is set to tri-state at startup.

Figures 4-19 and 4-20 show the input and output timing requirements for the STARTSCAN signal.

PCI-MIO E Series User Manual 4-32

after the last

off

National Instruments Corporation

Rising-edge polarity

Falling-edge polarity

STARTSCAN

Chapter 4 Signal Connections

= 10 ns minimum

Figure 4-19. STARTSCAN Input Signal Timing

tw = 50-100 ns

a. Start of Scan

Start Pulse

CONVERT*

STARTSCAN

off



off

= 10 ns minimum



b. Scan in Progress, Two Conversions per Scan

Figure 4-20. STARTSCAN Output Signal Timing

National Instruments Corporation 4-33 PCI-MIO E Series User Manual

Chapter 4 Signal Connections

The CONVERT* pulses are masked off until the board generates the STARTSCAN signal. If you are using internally generated conversions, the first CONVERT* appears when the onboard sample interval counter reaches zero. If you select an external CONVERT*, the first external pulse after STARTSCAN generates a conversion. The STARTSCAN pulses should be separated by at least one scan period.

A counter on your PCI-MIO E Series board internally generates the STARTSCAN signal unless you select some external source. This counter is started by the TRIG1 signal and is stopped either by software or by the sample counter.

Scans generated by either an internal or external STARTSCAN signal are inhibited unless they occur within a DAQ sequence. Scans occurring within a DAQ sequence may be gated by either the hardware (AIGATE) signal or software command register gate.

CONVERT* Signal

Any PFI pin can externally input the CONVERT* signal, which is available as an output on the PFI2/CONVERT* pin.

Refer to Figures 4-11 and 4-12 for the relationship of STARTSCAN to the DAQ sequence.

As an input, the CONVERT* signal is configured in the edge-detection mode. You can select any PFI pin as the source for CONVERT* and configure the polarity selection for either rising or falling edge. The selected edge of the CONVERT* signal initiates an A/D conversion.

As an output, the CONVERT* signal reflects the actual convert pulse that is connected to the ADC. This is true even if the conversions are being externally generated by another PFI. The output is an active low pulse with a pulse width of 50 to 100 ns. This output is set to tri-state at startup.

Figures 4-21 and 4-22 show the input and output timing requirements for the CONVERT* signal.

PCI-MIO E Series User Manual 4-34

National Instruments Corporation

Rising-edge polarity

Falling-edge polarity

Chapter 4 Signal Connections

= 10 ns minimum

Figure 4-21. CONVERT* Input Signal Timing

= 50-100 ns minimum

Figure 4-22. CONVERT* Output Signal Timing

The ADC switches to hold mode within 60 ns of the selected edge. This hold-mode delay time is a function of temperature and does not vary from one conversion to the next. Separate the CONVERT* pulses by at least one conversion period.

The sample interval counter on the PCI-MIO E Series board normally generates the CONVERT* signal unless you select some external source. The counter is started by the STARTSCAN signal and continues to count down and reload itself until the scan is finished. It then reloads itself in preparation for the next STARTSCAN pulse.

A/D conversions generated by either an internal or external CONVERT* signal are inhibited unless they occur within a DAQ sequence. Scans occurring within a DAQ sequence may be gated by either the hardware (AIGATE) signal or software command register gate.

National Instruments Corporation 4-35 PCI-MIO E Series User Manual

Chapter 4 Signal Connections

AIGATE Signal

Any PFI pin can externally input the AIGATE signal, which is not available as an output on the I/O connector. The AIGATE signal can mask off scans in a DAQ sequence. You can configure the PFI pin you select as the source for the AIGATE signal in either the level-detection or edge-detection mode. You can configure the polarity selection for the PFI pin for either active high or active low.

In the level-detection mode if AIGATE is active, the STARTSCAN signal is masked off and no scans can occur. In the edge-detection mode, the first active edge disables the STARTSCAN signal, and the second active edge enables STARTSCAN.

The AIGATE signal can neither stop a scan in progress nor continue a previously gated-off scan; in other words, once a scan has started, AIGATE does not gate off conversions until the beginning of the next scan and, conversely, if conversions are being gated off, AIGATE does not gate them back on until the beginning of the next scan.

SISOURCE Signal

Any PFI pin can externally input the SISOURCE signal, which is not available as an output on the I/O connector. The onboard scan interval counter uses the SISOURCE signal as a clock to time the generation of the STARTSCAN signal. You must configure the PFI pin you select as the source for the SISOURCE signal in the level-detection mode. You can configure the polarity selection for the PFI pin for either active high or active low.

The maximum allowed frequency is 20 MHz, with a minimum pulse width of 23 ns high or low. There is no minimum frequency limitation.

Either the 20 MHz or 100 kHz internal timebase generates the SISOURCE signal unless you select some external source. Figure 4-23 shows the timing requirements for the SISOURCE signal.

PCI-MIO E Series User Manual 4-36

National Instruments Corporation

Chapter 4 Signal Connections

Figure 4-23. SISOURCE Signal Timing

= 50 ns minimum

= 23 ns minimum

Waveform Generation Timing Connections

The analog group defined for your PCI-MIO E Series board is controlled by WFTRIG, UPDATE*, and UISOURCE.

WFTRIG Signal

Any PFI pin can externally input the WFTRIG signal, which is available as an output on the PFI6/WFTRIG pin.

As an input, the WFTRIG signal is configured in the edge-detection mode. You can select any PFI pin as the source for WFTRIG and configure the polarity selection for either rising or falling edge. The selected edge of the WFTRIG signal starts the waveform generation for the DACs. The update interval (UI) counter is started if you select internally generated UPDATE*.

As an output, the WFTRIG signal reflects the trigger that initiates waveform generation. This is true even if the waveform generation is being externally triggered by another PFI. The output is an active high pulse with a pulse width of 50 to 100 ns. This output is set to tri-state at startup.

Figures 4-24 and 4-25 show the input and output timing requirements for the WFTRIG signal.

National Instruments Corporation 4-37 PCI-MIO E Series User Manual

Chapter 4 Signal Connections

Rising-edge polarity

Falling-edge polarity

= 10 ns minimum

Figure 4-24. WFTRIG Input Signal Timing

Figure 4-25. WFTRIG Output Signal Timing

UPDATE* Signal

Any PFI pin can externally input the UPDATE* signal, which is available as an output on the PFI5/UPDATE* pin.

As an input, the UPDATE* signal is configured in the edge-detection mode. You can select any PFI pin as the source for UPDATE* and configure the polarity selection for either rising or falling edge. The selected edge of the UPDATE* signal updates the outputs of the DACs. In order to use UPDATE*, you must set the DACs to posted-update mode.

PCI-MIO E Series User Manual 4-38

= 50-100 ns

National Instruments Corporation

Rising-edge polarity

Falling-edge polarity

Chapter 4 Signal Connections

As an output, the UPDATE* signal reflects the actual update pulse that is connected to the DACs. This is true even if the updates are being externally generated by another PFI. The output is an active low pulse with a pulse width of 300 to 350 ns. This output is set to tri-state at startup.

Figures 4-26 and 4-27 show the input and output timing requirements for the UPDATE* signal.

= 10 ns minimum

Figure 4-26. UPDATE* Input Signal Timing

t

= 300-350 ns

Figure 4-27. UPDATE* Output Signal Timing

The DACs are updated within 100 ns of the leading edge. Separate the UPDATE* pulses with enough time that new data can be written to the DAC latches.

The PCI-MIO E Series board UI counter normally generates the UPDATE* signal unless you select some external source. The UI counter is started by the WFTRIG signal and can be stopped by software or the internal Buffer Counter.

National Instruments Corporation 4-39 PCI-MIO E Series User Manual

Chapter 4 Signal Connections

D/A conversions generated by either an internal or external UPDATE* signal do not occur when gated by the software command register gate.

UISOURCE Signal

Any PFI pin can externally input the UISOURCE signal, which is not available as an output on the I/O connector. The UI counter uses the UISOURCE signal as a clock to time the generation of the UPDATE* signal. You must configure the PFI pin you select as the source for the UISOURCE signal in the level-detection mode. You can configure the polarity selection for the PFI pin for either active high or active low. Figure 4-28 shows the timing requirements for the UISOURCE signal.

Figure 4-28. UISOURCE Signal Timing

= 50 ns minimum

= 23 ns minimum

The maximum allowed frequency is 20 MHz, with a minimum pulse width of 23 ns high or low. There is no minimum frequency limitation.

Either the 20 MHz or 100 kHz internal timebase normally generates the UISOURCE signal unless you select some external source.

General-Purpose Timing Signal Connections

The general-purpose timing signals are GPCTR0_SOURCE, GPCTR0_GATE, GPCTR0_OUT, GPCTR0_UP_DOWN, GPCTR1_SOURCE, GPCTR1_GATE, GPCTR1_OUT, GPCTR1_UP_DOWN, and FREQ_OUT.

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National Instruments Corporation

Chapter 4 Signal Connections

GPCTR0_SOURCE Signal

Any PFI pin can externally input the GPCTR0_SOURCE signal, which is available as an output on the PFI8/GPCTR0_SOURCE pin.

As an input, the GPCTR0_SOURCE signal is configured in the edge-detection mode. You can select any PFI pin as the source for GPCTR0_SOURCE and configure the polarity selection for either rising or falling edge.

As an output, the GPCTR0_SOURCE signal reflects the actual clock connected to general-purpose counter 0. This is true even if another PFI is externally inputting the source clock. This output is set to tri-state at startup.

Figure 4-29 shows the timing requirements for the GPCTR0_SOURCE signal.

Figure 4-29. GPCTR0_SOURCE Signal Timing

= 50 ns minimum

= 23 ns minimum

The maximum allowed frequency is 20 MHz, with a minimum pulse width of 23 ns high or low. There is no minimum frequency limitation.

The 20 MHz or 100 kHz timebase normally generates the GPCTR0_SOURCE signal unless you select some external source.

National Instruments Corporation 4-41 PCI-MIO E Series User Manual

Chapter 4 Signal Connections

GPCTR0_GATE Signal

Any PFI pin can externally input the GPCTR0_GATE signal, which is available as an output on the PFI9/GPCTR0_GATE pin.

As an input, the GPCTR0_GATE signal is configured in the edge-detection mode. You can select any PFI pin as the source for GPCTR0_GATE and configure the polarity selection for either rising or falling edge. You can use the gate signal in a variety of different applications to perform actions such as starting and stopping the counter, generating interrupts, saving the counter contents, and so on.

As an output, the GPCTR0_GATE signal reflects the actual gate signal connected to general-purpose counter 0. This is true even if the gate is being externally generated by another PFI. This output is set to tri-state at startup.

Figure 4-30 shows the timing requirements for the GPCTR0_GATE signal.

Rising-edge polarity

Falling-edge polarity

Figure 4-30. GPCTR0_GATE Signal Timing in Edge-Detection Mode

GPCTR0_OUT Signal

This signal is available only as an output on the GPCTR0_OUT pin. The GPCTR0_OUT signal reflects the terminal count (TC) of general-purpose counter 0. You have two software-selectable output options—pulse on TC and toggle output polarity on TC. The output polarity is software selectable for both options. This output is set to tri-state at startup. Figure 4-31 shows the timing of the GPCTR0_OUT signal.

PCI-MIO E Series User Manual 4-42

= 10 ns minimum

National Instruments Corporation

GPCTR0_SOURCE

GPCTR0_OUT

(Pulse on TC)

GPCTR0_OUT

(Toggle output on TC)

Chapter 4 Signal Connections

Figure 4-31. GPCTR0_OUT Signal Timing

GPCTR0_UP_DOWN Signal

This signal can be externally input on the DIO6 pin and is not available as an output on the I/O connector. The general-purpose counter 0 will count down when this pin is at a logic low and count up when it is at a logic high. You can disable this input so that software can control the up-down functionality and leave the DIO6 pin free for general use.

GPCTR1_SOURCE Signal

Any PFI pin can externally input the GPCTR1_SOURCE signal, which is available as an output on the PFI3/GPCTR1_SOURCE pin.

As an input, the GPCTR1_SOURCE signal is configured in the edge-detection mode. You can select any PFI pin as the source for GPCTR1_SOURCE and configure the polarity selection for either rising or falling edge.

As an output, the GPCTR1_SOURCE monitors the actual clock connected to general-purpose counter 1. This is true even if the source clock is being externally generated by another PFI. This output is set to tri-state at startup.

Figure 4-32 shows the timing requirements for the GPCTR1_SOURCE signal.

National Instruments Corporation 4-43 PCI-MIO E Series User Manual

Chapter 4 Signal Connections

Figure 4-32. GPCTR1_SOURCE Signal Timing

= 50 ns minimum

= 23 ns minimum

The maximum allowed frequency is 20 MHz, with a minimum pulse width of 23 ns high or low. There is no minimum frequency limitation.

The 20 MHz or 100 kHz timebase normally generates the GPCTR1_SOURCE unless you select some external source.

GPCTR1_GATE Signal

Any PFI pin can externally input the GPCTR1_GATE signal, which is available as an output on the PFI4/GPCTR1_GATE pin.

As an input, the GPCTR1_GATE signal is configured in edge-detection mode. You can select any PFI pin as the source for GPCTR1_GATE and configure the polarity selection for either rising or falling edge. You can use the gate signal in a variety of different applications to perform such actions as starting and stopping the counter, generating interrupts, saving the counter contents, and so on.

As an output, the GPCTR1_GATE signal monitors the actual gate signal connected to general-purpose counter 1. This is true even if the gate is being externally generated by another PFI. This output is set to tri-state at startup.

Figure 4-33 shows the timing requirements for the GPCTR1_GATE signal.

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National Instruments Corporation

Rising-edge polarity

Falling-edge polarity

Chapter 4 Signal Connections

= 10 ns minimum

Figure 4-33. GPCTR1_GATE Signal Timing in Edge-Detection Mode

GPCTR1_OUT Signal

This signal is available only as an output on the GPCTR1_OUT pin. The GPCTR1_OUT signal monitors the TC board general-purpose counter 1. You have two software-selectable output options—pulse on TC and toggle output polarity on TC. The output polarity is software selectable for both options. This output is set to tri-state at startup. Figure 4-34 shows the timing requirements for the GPCTR1_OUT signal.

GPCTR1_SOURCE

GPCTR1_OUT (Pulse on TC)

GPCTR1_OUT (Toggle output on TC)

Figure 4-34. GPCTR1_OUT Signal Timing

National Instruments Corporation 4-45 PCI-MIO E Series User Manual

Chapter 4 Signal Connections

GPCTR1_UP_DOWN Signal

This signal can be externally input on the DIO7 pin and is not available as an output on the I/O connector. General-purpose counter 1 counts down when this pin is at a logic low and counts up at a logic high. This input can be disabled so that software can control the up-down functionality and leave the DIO7 pin free for general use. Figure 4-35 shows the timing requirements for the GATE and SOURCE input signals and the timing specifications for the OUT output signals of your PCI-MIO E Series board.

SOURCE

GATE

OUT

gsu

Source Clock Period Source Pulse Width Gate Setup Time Gate Hold Time Gate Pulse Width Output Delay Time

out

t 50 ns minimum

gsu

out

23 ns minimum

10 ns minimum

0 ns minimum 10 ns minimum 80 ns maximum

Figure 4-35. GPCTR Timing Summary

The GATE and OUT signal transitions shown in Figure 4-35 are referenced to the rising edge of the SOURCE signal. This timing diagram assumes that the counters are programmed to count rising edges. The same timing diagram, but with the source signal inverted and referenced to the falling edge of the source signal, would apply when the counter is programmed to count falling edges.

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National Instruments Corporation

Chapter 4 Signal Connections

The GATE input timing parameters are referenced to the signal at the SOURCE input or to one of the internally generated signals on your PCI-MIO E Series board. Figure 4-35 shows the GATE signal referenced to the rising edge of a source signal. The gate must be valid (either high or low) for at least 10 ns before the rising or falling edge of a source signal for the gate to take effect at that source edge, as shown by t

and tgh in Figure 4-35. The gate signal is not required to be held

gsu

after the active edge of the source signal. If you use an internal timebase clock, the gate signal cannot be

synchronized with the clock. In this case, gates applied close to a source edge take effect either on that source edge or on the next one. This arrangement results in an uncertainty of one source clock period with respect to unsynchronized gating sources.

The OUT output timing parameters are referenced to the signal at the SOURCE input or to one of the internally generated clock signals on the PCI-MIO E Series boards. Figure 4-35 shows the OUT signal referenced to the rising edge of a source signal. Any OUT signal state changes occur within 80 ns after the rising or falling edge of the source signal.

FREQ_OUT Signal

This signal is available only as an output on the FREQ_OUT pin. The PCI-MIO E Series board frequency generator outputs the FREQ_OUT pin. The frequency generator is a 4-bit counter that can divide its input clock by the numbers 1 through 16. The input clock of the frequency generator is software- selectable from the internal 10 MHz and 100 kHz timebases. The output polarity is software selectable. This output is set to tri-state at startup.

National Instruments Corporation 4-47 PCI-MIO E Series User Manual

Chapter 4 Signal Connections

Field Wiring Considerations

Environmental noise can seriously affect the accuracy of measurements made with your PCI-MIO E Series board if you do not take proper care when running signal wires between signal sources and the board. The following recommendations apply mainly to analog input signal routing to the board, although they also apply to signal routing in general.

Minimize noise pickup and maximize measurement accuracy by taking the following precautions:

• Use differential analog input connections to reject common-mode noise.

• Use individually shielded, twisted-pair wires to connect analog input signals to the board. With this type of wire, the signals attached to the CH+ and CH- inputs are twisted together and then covered with a shield. You then connect this shield only at one point to the signal source ground. This kind of connection is required for signals traveling through areas with large magnetic fields or high electromagnetic interference.

• Route signals to the board carefully. Keep cabling away from noise sources. The most common noise source in a PCI data acquisition system is the video monitor. Separate the monitor from the analog signals as much as possible.

The following recommendations apply for all signal connections to

your PCI-MIO E Series board:

• Separate PCI-MIO E Series board signal lines from high-current or high-voltage lines. These lines can induce currents in or voltages on the PCI-MIO E Series board signal lines if they run in parallel paths at a close distance. To reduce the magnetic coupling between lines, separate them by a reasonable distance if they run in parallel, or run the lines at right angles to each other.

• Do not run signal lines through conduits that also contain power lines.

• Protect signal lines from magnetic fields caused by electric motors, welding equipment, breakers, or transformers by running them through special metal conduits.

For more information, refer to the application note, Field Wiring and Noise Consideration for Analog Signals, available from National Instruments.

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National Instruments Corporation

Chapter

Calibration

This chapter discusses the calibration procedures for your PCI-MIO E Series board. If you are using the NI-DAQ device driver, that software includes calibration functions for performing all of the steps in the calibration process.

Calibration refers to the process of minimizing measurement and output voltage errors by making small circuit adjustments. On the PCI-MIO E Series boards, these adjustments take the form of writing values to onboard calibration DACs (CalDACs).

Some form of board calibration is required for all but the most forgiving applications. If you do not calibrate your board, your signals and measurements could have very large offset, gain, and linearity errors.

Three levels of calibration are available to you and described in this chapter. The first level is the fastest, easiest, and least accurate, whereas the last level is the slowest, most difficult, and most accurate.

Loading Calibration Constants

Your PCI-MIO E Series board is factory calibrated before shipment at approximately 25° C to the levels indicated in Appendix A, Specifications. The associated calibration constants—the values that were written to the CalDACs to achieve calibration in the factory—are stored in the onboard nonvolatile memory (EEPROM). Because the CalDACs have no memory capability, they do not retain calibration information when the board is unpowered. Loading calibration constants refers to the process of loading the CalDACs with the values stored in the EEPROM. NI-DAQ software determines when this is necessary and does it automatically. If you are not using NI-DAQ, you must load these values yourself.

In the EEPROM there is a user-modifiable calibration area in addition to the permanent factory calibration area. This means that you can load the CalDACs with values either from the original factory calibration or from a calibration that you subsequently performed.

National Instruments Corporation 5-1 PCI-MIO E Series User Manual

Chapter 5 Calibration

This method of calibration is not very accurate because it does not take into account the fact that the board measurement and output voltage errors can vary with time and temperature. It is better to self-calibrate when the board is installed in the environment in which it will be used.

Self-Calibration

Your PCI-MIO E Series board can measure and correct for almost all of its calibration-related errors without any external signal connections. Your National Instruments software provides a self-calibration method. This self-calibration process, which generally takes less than a minute, is the preferred method of assuring accuracy in your application. Initiate self-calibration to minimize the effects of any offset, gain, and linearity drifts, particularly those due to warmup.

Immediately after self-calibration, the only significant residual calibration error could be gain error due to time or temperature drift of the onboard voltage reference. This error is addressed by external calibration, which is discussed in the following section. If you are interested primarily in relative measurements, you can ignore a small amount of gain error, and self-calibration should be sufficient.

External Calibration

Your PCI-MIO E Series board has an onboard calibration reference to ensure the accuracy of self-calibration. Its specifications are listed in Appendix A, Specifications. The reference voltage is measured at the factory and stored in the EEPROM for subsequent self-calibrations. This voltage is stable enough for most applications, but if you are using your board at an extreme temperature or if the onboard reference has not been measured for a year or more, you may wish to externally calibrate your board.

An external calibration refers to calibrating your board with a known external reference rather than relying on the onboard reference. Redetermining the value of the onboard reference is part of this process and the results can be saved in the EEPROM, so you should not have to perform an external calibration very often. You can externally calibrate your board by calling the NI-DAQ calibration function.

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National Instruments Corporation

To externally calibrate your board, be sure to use a very accurate external reference. The reference should be several times more accurate than the board itself. For example, to calibrate a 16-bit board, the external reference should be at least ±0.001% (±10 ppm) accurate.

Other Considerations

The CalDACs adjust the gain error of each analog output channel by adjusting the value of the reference voltage supplied to that channel. This calibration mechanism is designed to work only with the internal 10 V reference. Thus, in general, it is not possible to calibrate the analog output gain error when using an external reference. In this case, it is advisable to account for the nominal gain error of the analog output channel either in software or with external hardware. See Appendix A, Specifications, for analog output gain error information.

Chapter 5 Calibration

National Instruments Corporation 5-3 PCI-MIO E Series User Manual

Appendix

Specifications

This appendix lists the specifications of each PCI-MIO E Series board. These specifications are typical at 25° C unless otherwise noted.

PCI-MIO-16E-1 and PCI-MIO-16E-4

Analog Input

Input Characteristics

Number of channels ...............................16 single-ended, or 8 differential

Type of ADC.......................................... Successive approximation

Resolution ..............................................12 bits, 1 in 4,096

Maximum sampling rate

PCI-MIO-16E-1..............................1.25 MS/s multichannel

PCI-MIO-16E-4..............................500 kS/s single-channel

(software-selectable per channel)

250 kS/s multichannel

National Instruments Corporation A-1 PCI-MIO E Series User Manual

Appendix A Speciﬁcations for PCI-MIO-16E-1 and PCI-MIO-16E-4

Input signal ranges

Channel Gain

(Software-Selectable)

Board Range

(Software-Selectable)

Bipolar Unipolar

0.5 ±10 V — 1 ±5 V 0 to 10 V 2 ±2.5 V 0 to 5 V 5 ±1 V 0 to 2 V

10 ±500 mV 0 to 1 V 20 ±250 mV 0 to 500 mV 50 ±100 mV 0 to 200 mV

100 ±50 mV 0 to 100 mV

Input coupling.........................................DC

Maximum working voltage

(signal and common mode).............Each input should remain within

±11 V of ground

Overvoltage protection ...........................±25 V powered on,

Inputs protected ..........................ACH<0..15>, AISENSE

FIFO buffer size......................................512 S

Data transfers..........................................DMA, interrupts,

DMA modes............................................Scatter-gather

Configuration memory size ....................512 words

PCI-MIO E Series User Manual A-2

±15 V powered off

programmed I/O

National Instruments Corporation

Appendix A Speciﬁcations for PCI-MIO-16E-1 and PCI-MIO-16E-4

Transfer Characteristics

Relative accuracy................................... ±0.5 LSB typ dithered,

±1.5 LSB max undithered

DNL ....................................................... ±0.5 LSB typ, ±1 LSB max

No missing codes ...................................12 bits, guaranteed

Offset error

State PCI-MIO-16E-1 PCI-MIO-16E-4

Pregain error after calibration Pregain error before calibration Postgain error after calibration Postgain error before calibration

Gain error (relative to calibration reference)

After calibration (gain = 1)............. ±0.02% of reading max

Before calibration............................±2.5% of reading max

Gain ≠ 1 with gain error

adjusted to 0 at gain = 1................±0.02% of reading max

±12 µV max ±2.5 mV max ±0.5 mV max

±100 mV max

±16 µV max ±4.0 mV max ±0.8 mV max

±200 mV max

Amplifier Characteristics

Input impedance

Normal powered on.........................100 GΩ in parallel with 100 pF

Powered off.....................................820 Ω min.

Overload..........................................820 Ω min.

Input bias current ................................... ±200 pA

Input offset current.................................±100 pA

National Instruments Corporation A-3 PCI-MIO E Series User Manual

Appendix A Speciﬁcations for PCI-MIO-16E-1 and PCI-MIO-16E-4

CMRR, all input ranges, DC to 60 Hz

CMRR

Gain

PCI-MIO-16E-1 PCI-MIO-16E-4

0.5 95 dB 90 dB 1 100 dB 95 dB

≥2 106 dB 100 dB

Dynamic Characteristics

Bandwidth

Board Small Signal (-3 dB) Large Signal (1% THD)

PCI-MIO-16E-1 PCI-MIO-16E-4

1.6 MHz 600 kHz

1 MHz

350 kHz

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National Instruments Corporation

DAQ PCI-MIO E Series User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Warranty

Copyright

Trademarks

Tables

Organization of This Manual

Conventions Used in This Manual

National Instruments Documentation

Related Documentation

Customer Communication

What You Need to Get Started

Software Programming Choices

National Instruments Application Software

Optional Equipment

Custom Cabling

Unpacking

Software Installation

Hardware Installation

Board Configuration

Analog Input

Input Mode

Input Polarity and Input Range

Considerations for Selecting Input Ranges

Dither

Figure 3-4. Dither

Multichannel Scanning Considerations

Analog Output

Analog Output Reference Selection

Analog Output Polarity Selection

Analog Output Reglitch Selection

Analog Trigger

Digital I/O

Timing Signal Routing

Figure 3-11. CONVERT* Signal Routing

Programmable Function Inputs

Board and RTSI Clocks

RTSI Triggers

Figure 3-12. RTSI Bus Signal Connection

I/O Connector

I/O Connector Signal Descriptions

Analog Input Signal Connections

Types of Signal Sources

Floating Signal Sources

Input Configurations

Figure 4-3. Summary of Analog Input Connections

Analog Output Signal Connections

Figure 4-8. Analog Output Connections

Digital I/O Signal Connections

Figure 4-9. Digital I/O Connections

Power Connections

Timing Connections

Figure 4-10. Timing I/O Connections

Programmable Function Input Connections

DAQ Timing Connections

Figure 4-11. Typical Posttriggered Acquisition

Figure 4-12. Typical Pretriggered Acquisition

SCANCLK Signal

Figure 4-13. SCANCLK Signal Timing

EXTSTROBE* Signal

Figure 4-14. EXTSTROBE* Signal Timing

TRIG1 Signal

Figure 4-15. TRIG1 Input Signal Timing

Figure 4-16. TRIG1 Output Signal Timing

TRIG2 Signal

Figure 4-17. TRIG2 Input Signal Timing

Figure 4-18. TRIG2 Output Signal Timing

STARTSCAN Signal

Figure 4-19. STARTSCAN Input Signal Timing

Figure 4-20. STARTSCAN Output Signal Timing

CONVERT* Signal

Figure 4-21. CONVERT* Input Signal Timing

Figure 4-22. CONVERT* Output Signal Timing

AIGATE Signal

SISOURCE Signal

Figure 4-23. SISOURCE Signal Timing

Waveform Generation Timing Connections

WFTRIG Signal