DAQ PCI-FRM01 Application Manual
Application Note (AN241)
PCI-FRM01 Register Level Application Guide
2005 DAQ system, all rights reserved. http://www.daqsystem.com
PCI-FRM01 Register Level
Application Guide (Ver1.1)
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Copyrights 2005 DAQ system, All rights reserved.
Application Note (AN241)
PCI-FRM01 Register Level Application Guide
2005 DAQ system, all rights reserved. http://www.daqsystem.com
-- Contents --
1. PCI BUS Address Space
2. PCI-FRM01 Functional Block Diagram
3. I/O Address Usage
4. Memory Address Usage
5. UART Usage
6. Interrupt Controller Usage
7. LVDS(Camera Link) Interface Usage
8. DIO(Digital Input/Output) Usage
References
Application Note (AN241)
PCI-FRM01 Register Level Application Guide
2005 DAQ system, all rights reserved. http://www.daqsystem.com
1. PCI BUS Address Space
As it uses CPU of the x86 system which we use mainly, it can classify greatly it to memory and I/O
area. In order to support Plug & Play in case of PCI bus that has a special configuration. It can make
the resource and device state control register etc.
Memory
Area
I/O Area
Configuration
Area
4G
64K
64DWORD
The PCI-FRM01 use a memory and I/O that have been assigned to system for operation, the
contents are as follows that they required.
Address Area
Requirements
Remark
Memory
Maximum 64MByte
I/O
256 Byte
Configuration
128 Byte
Application Note (AN241)
PCI-FRM01 Register Level Application Guide
2005 DAQ system, all rights reserved. http://www.daqsystem.com
2. PCI-FRM01 Functional Block Diagram
The address area assigned by the system in the PCI-FRM01 division is shown in the figure below.
Most peripheral control and status register is in the I/O area, only SDR SRAM is in the memory area.
The configuration area can not be used in the most application because of only using resources for the
system boot time.
PCI Target
PCI BUS
Local Bus
Address
Data(Mem,I/O)
Reserved
(0x00 ? 0x5F)
Reserved
(0x70 ? 0xAF)
UART
(0x60)
Camera Link(LVDS)
(0xC0)
Interrupt controller
DIO
(0xD0)
Ext. Address, Data, Control
Local BUS
Interrupt
Controller
(0xb0)
INT sources in Chip
IO Decoder
MEM Decoder
To each IO
Module
PCI-FRM01 INTERNAL BLOCK - FPGA
DPRAM
From Ext.
CLOCK syn.
MEM Decoder
BUS Mux
Reserved
(0xE0 ? 0xFF)
PCI-FRM01 of the figure shows the function block, which features the dotted area is reserved for
future feature additions.
Application Note (AN241)
PCI-FRM01 Register Level Application Guide
2005 DAQ system, all rights reserved. http://www.daqsystem.com
3. I/O Address Usage
The below table indicates the base address of the peripheral device that is located I/O area address.
The table below the I / O area is located at the address indicates the base address of the peripheral
device. All I / O registers are 32-bit input / output processing.
Reserved area for future use00h-5Fh
Description
I/O Address
Offset Base
Reserved
Function
60h
70h-AFh
Universal asynchronous receiver transmitter (RS232C)
Reserved area for future use
UART
Reserved
Frame grabber LVDS interfaceC0h
D0h
E0h-FFh
Photo-coupler isolated Digital input/Output
Reserved area for future use
Camera Link
DIO
Reserved
Comment
B0h Interrupt controllerInterrupt
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