Dallas Semiconductor DS9034PCX, DS1743WP-100, DS1743W-70, DS1743W-100, DS1743P-70 Datasheet

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FEATURES

 Integrated NV SRAM, real time clock, crystal, power-

fail control circuit and lithium energy source

 Clock registers are accessed identical to the static

RAM. These registers are resident in the eight top
RAM locations.

 Century byte register
 Totally nonvolatile with over 10 years of operation in
 the absence of power
 BCD coded century, year, month, date, day, hours,
 minutes, and seconds with automatic leap year

compensation valid up to the year 2100

 Battery voltage level indicator flag
 Power-fail write protection allows for ±10% V

CC

power supply tolerance

 Lithium energy source is electrically disconnected to

retain freshness until power is applied for the first time

 DIP Module only

– Standard JEDEC bytewide 8k x 8 static RAM

pinout

 PowerCap



Module Board only

– Surface mountable package for direct connection

to PowerCap containing battery and crystal

– Replaceable battery (PowerCap)
– Power-On Reset Output
– Pin for pin compatib le with other densities of

DS174XP Timekeeping RA M

ORDERING INFORMATION

DS1743P-XXX (5V)

-70 70 ns access

-100 100 ns access

blank 28-pin DIP Module
P 34-pin PowerCap Module

board*

*DS1743WP-XXX (3.3V)

-120 120 ns access

-150 150 ns access

blank 28-pin DIP Module
P 34-pin PowerCap Module

board*

*DS9034PCX (PowerCap) Required:

(must be ordered separately)

PIN ASSIGNMENT

PIN DESCRIPTION

A0-A12 - Address Input

CE - Chip Enable

CE2 - Chip Enable 2 (DIP

Module only)

OE - Output Enable
WE - Write Enable

V

CC

- Power Supply Input
GND - Ground
DQ0-DQ7 - Data Input/Output
NC - No Connection

RST - Power-On Reset Output

(PowerCap Module board only)
X1, X2 - Crystal Connection
V

BAT

- Battery Connection

DS1743/DS1743P

Y2KC Nonvolatile Timekeeping RAM

www.dalsemi.com

V

CC

WE
CE2

A8A9A

11

OE

A

10
CE
DQ7
DQ6
DQ5
DQ4
DQ3

1
2
3
4
5
6
7
8
9
10
11
12
13
14

NC

A12

A7
A6
A5
A4
A3
A2
A1

A0
DQ0
DQ1
DQ2

GND

28
27
26
25
24
23
22
21
20
19
18
17
16
15

28-Pin Encapsulated Package

(

700-mil Extended

)

1

NC

2

3

NC
NC

RST

V

CC

WE

OE

CE
DQ7
DQ6
DQ5
DQ4
DQ3

DQ2
DQ1
DQ0

GND

4
5
6
7
8
9
10
11
12
13
14
15
16
17

NC
NC

33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18

NC

A12A11A

10

A

9

A8A7A

6

A

5

A

4

A3A

2

A

1

A

0

34

NC

X1 GND

V

BAT

X2

34-Pin Powercap Module Board

(Uses DS9034PCX Powercap)

DS1743/DS1743P

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DESCRIPTION

The DS1743 is a full function, year 2000-compliant (Y2KC), real-time clock/calendar (RTC) and 8k x 8
non-volatile static RAM. User access to all registers within the DS1743 is accomplished with a bytewide
interface as shown in Figure 1. The Real Time Clock (RTC) information and control bits reside in the
eight uppermost RAM locations. The RTC registers contain century, year, month, date, day, hours,
minutes, and seconds data in 24-hour BCD format. Corrections for the day of the month and le ap year are
made automatically. The RTC clock registers are double buffered to avoid access of incor rect data that
can occur during clock update cycles. The double buffered system also prevents time loss as the
timekeeping countdown continues unabated by access to time register data. The DS1743 also contains its
own power-fail circuitry, which deselects the device when the VCC supply is in an out of tolerance
condition. This feature prevents loss of data from unpredictable system operation brought on by low V

CC

as errant access and update cycles are avoided.

PACKAGES

The DS1743 is available in two packages (28-pin DIP and 34-pin PowerCap module). The 28-pin DIP
style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap Module Board is designed with contacts for connection to a separate PowerCap (DS9034PCX)
that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the
DS1743P after the completion of the surface mount process. Mounting the PowerCap after the surface
mount process prevents damage to the crystal and battery due to the high temperatures required for solde r
reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap
are ordered separately and shipped in separate containers. The part number for the PowerCap is
DS9034PCX.

CLOCK OPERATIONS-READING THE CLOCK

While the double buffered register structure reduces the chance o f reading incorrect data, inte rnal updates
to the DS1743 clock registers should be halted before clock data is read to prevent reading of data in
transition. However, halting the internal clock register updating process does not affect clock accuracy.
Updating is halted when a 1 is written into the read bit, bit 6 of the century register, see Table 2. As long
as a 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the count, that
is day, date, and time that was current at the moment the halt command was issued. However, the internal
clock registers of the double-buffered system continue to update so that the clock accuracy is not affected
by the access of data. All of the DS1743 registers are updated simultaneously after the internal clock
register updating process has been re-enabled. Updating is within a second after the read bit is written to

0.
The READ bit must be a zero for a minimum of 500 µs to ensure the external registers will be updated.

DS1743/DS1743P

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DS1743 BLOCK DIAGRAM Figure 1

DS1743 TRUTH TABLE Table 1

V

CC

CE

CE2

OE WE

MODE

DQ

POWER

V

IH

X X X DESELECT HIGH-Z STANDBY

XVILX X DESELECT HIGH-Z STANDBY

V

IL

V

IH

XVILWRITE DATA IN ACTIVE

V

IL

V

IH

V

IL

V

IH

READ DATA OUT ACTIVE

VCC>V

PF

V

IL

V

IH

V

IH

V

IH

READ HIGH-Z ACTIVE

VSO<VCC<V

PF

X X X X DESELECT HIGH-Z CMOS STANDBY

VCC<VSO<V

PF

X X X X DESELECT HIGH-Z DATA RETENTION

MODE

SETTING THE CLOCK

As shown in Table 2, bit 7 of the century register is the write bit. Setting the write bit to a 1, like the read
bit, halts updates to the DS1743 registers. The user can then load them with the correct day, date and time
data in 24-hour BCD format. Resetting the write bit to a 0 then transfers those values to the actual clock
counters and allows normal operation to resume.

STOPPING AND STARTING THE CLOCK OSCILLATOR

The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off
to minimize current drain from the battery. The OSC bit is the MSB (bit 7) of the seconds registers, see

Table 2. Setting it to a 1 stops the oscillator.

FREQUENCY TEST BIT

As shown in Table 2, bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to
logic 1 and the oscillator is running, the LSB of the seconds register will toggle at 512 Hz. When the
seconds register is being read, the DQ0 line will toggle at the 512 Hz frequency as long as conditions for

access remain valid (i.e.,

CE low, OE low, WE high, and address for seconds register rem ain valid and

stable).

DS1743/DS1743P

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CLOCK ACCURACY (DIP MODULE)

The DS1743 is guaranteed to keep time accuracy to within ±1 minute per month at 25°C. The RTC is
calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements, and does not r equire
additional For this reason, methods of field clock calibration are not available and not necessary. Clock
accuracy is also effected by the electrical environment and caution should be taken to place the RTC in the
lowest level EMI section of the PCB layout. For additional information please see application note 58.

CLOCK ACCURACY (POWERCAP MODULE)

The DS1743 and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module will typically keep time accuracy to within ±1.53 minutes per month (35 ppm) at 25°C. Clock
accuracy is also effected by the electrical environment and caution should be taken to place the RTC in the
lowest level EMI section of the PCB layout. For additional information please see application note 58.

DS1743 REGISTER MAP Table 2

DATA

ADDRESS

B

7

B

6

B

5

B

4

B

3

B

2

B

1

B

0

FUNCTION/RANGE

1FFF 10 Year YEAR YEAR 00-99

1FFE X X X 10 Mo MONTH MONTH 01-12
1FFD X X 10 Date DATE DATE 01-31
1FFC BF FT X X X DAY DAY 01-07
1FFB X X 10 HOUR HOUR HOUR 00-23
1FFA X 10 MINUTES MINUTES MINUTES 00-59

1FF9

OSC

10 SECONDS SECONDS SECONDS 00-59

1FF8 W R 10 CENTURY CENTURY CONTROL 00-39

OSC = STOP BIT

R = READ BIT FT = FREQUENCY TEST

W = WRITE BIT X = SEE NOTE BELOW BF = BATTERY FLAG

NOTE:

All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.

RETRIEVING DATA FROM RAM OR CLOCK

The DS1743 is in the read mode whenever OE (output enable) is low, WE (write enable) is high, and CE
(chip enable) is low. The device archit ecture allows ripple-throu gh access to any of the address locations
in the NV SRAM. Valid data will be available at the DQ pins within tAA after the last address input is

stable, providing that the CE , and OE access times and states are s atisfied. If CE , or OE access times and
states are not met, valid data will be available at the latter of chip enable access (t

CEA

) or at output enable

access time (t

CEA

). The state of the data input/output pins (DQ) is controlled by CE , and OE . If the

outputs are activated before t

AA

, the data lines are driven to an intermediate state until tAA. If the address

inputs are changed while

CE , and OE remain valid, output data will remain valid for output data hold time

(tOH) but will then go indeterminate until the next address access.

DS1743/DS1743P

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WRITING DATA TO RAM OR CLOCK

The DS1743 is in the write mode whenever WE , and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE , on CE . The addresses must be held valid throughout
the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of another read or

write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH afterward. In a
typical application, the

OE signal will be high during a write cycle. However, OE can be active provided

that care is taken with the data bus to avoid bus contention. If

OE is low prior to WE transitioning low the

data bus can become active with read data defined by the address inputs. A low transition on WE will
then disable the outputs t

WEZ

after WE goes active.

DATA RETENTION MODE

The 5-volt device is fully accessible and data can be written or read only when VCC is greater than VPF.
However, when VCC is below the power fail point, V

PF

, (point at which write protection occurs) the internal

clock registers and SRAM are blocked from any access. At this time(PowerCap only)the power fail reset
output signal (RST ) is driven active and will remain active until VCC returns to nominal levels. When VCC

falls below the battery switch point VSO (battery supply level), device power is switched from the VCC pin to
the backup battery. RTC operation and SRAM data are maintained from the battery until V

CC is returned to

nominal levels. The 3.3-volt device is fully accessible and data can be written or read only when V

CC is

greater than V

PF. When VCC fal ls below the power fail point, VPF, access to the device is inhibited. At this

time the power fail reset output signal (

RST) is driven active and will remain active until VCC returns to

nominal levels. If V

PF is less than Vso, the device power is switch ed from VCC to the backup supply (VBAT)

when V

CC drops below VPF. If VPF is greater than Vso, the device power is switched from VCC to the backup

supply (V

BAT) when VCC drops below Vso. RTC operation and SRAM data are maintained f rom the batter y

until V

CC is returned to nominal levels. The RST (PowerCap only) signal is an open drain output and

requires a pull up. Except for the

RST , all control, data, and addr ess signals must be powered down when

V

CC is powered down.

BATTERY LONGEVITY

The DS1743 has a lithium power source that is designed to provide energy for clock activity and clock and
RAM data retention when the V

CC

supply is not present. The capability of this internal power supply is
sufficient to power the DS1743 continuously for the life of the equipment in which it is installed. For
specification purposes, the life ex pectanc y is 10 years at 25

°C with the internal clock oscillator running in

the absence of V

CC

power. Each DS1743 is shipped from Dallas Semiconductor with its lithium energy

source disconnected, guaranteein g full energy capacity. When V

CC

is first applied at a level greater than

V

PF

, the lithium energy source is enabled for battery backup operation. Actual life expectancy of the

DS1743 will be much longer than 10 years since no lithium battery energy is consumed when V

CC

is

present.

BATTERY MONITOR

The DS1743 constantly monitors the battery voltage of the internal battery. The Battery Flag bit (bit 7) of
the day register is used to indicate the voltage level range of the battery. This bit is not writable and should
always be a 1 when read. If a 0 is ever present, an exhausted lithium energy source is indicated and both
the contents of the RTC and RAM are questionable.

DS1743/DS1743P

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ABSOLUTE MAXIMUM RATINGS*

Voltage on Any Pin Relative to Ground -0.3V to +6.0V
Operating Temperature 0

°C to 70°C

Storage Temperature -40

°C to +85°C

Soldering Temperature See J-STD-020A Specification (See Note 8)

* This is a stress rating only and functional operation of the device at these or any other conditions above

those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.

OPERATING RANGE

Range Temperature V

CC

Commercial 0°C to +70°C

3.3V

± 10% or 5V ± 10%

RECOMMENDED DC OPERATING CONDITIONS

(Over the Operating Range)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Logic 1 Voltage All Inputs

V

CC

= 5V ±10%

V

IH

2.2 VCC +0.3V V 1

VCC = 3.3V ±10%

V

IH

2.0 VCC +0.3V V 1

Logic 0 Voltage All Inputs

V

CC

= 5V ±10% V

IL

-0.3 0.8 V 1

VCC = 3.3V ±10%

V

IL

-0.3 0.6 V 1

DC ELECTRICAL CHARACTERISTICS

(Over the Operating Range; V

CC

= 5.0V ± 10%)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Active Supply Current I

CC

15 50 mA 2, 3

TTL Standby Current
(

CE =V

IH

, CE2=VIL)

I

CC1

13mA2, 3

CMOS Standby Current
(

CE ≥=V

CC

- 0.2V, CE2=

GND + 0.2V)

I

CC2

13mA2, 3

Input Leakage Current
(any input)

I

IL

-1 +1

µA

Output Leakage Current
(any output)

I

OL

-1 +1

µA

Output Logic 1 Voltage
(I

OUT

= -1.0 mA)

V

OH

2.4 1

Output Logic 0 Voltage
(I

OUT

= 2.1 mA)

V

OL1

0.4 1

Write Protection Voltage V

PF

4.25 4.50 V 1

Battery Switch-over Voltage V

SO

V

BAT

1, 4