Dallas Semiconductor DS87C520-WCL, DS87C520-QNL, DS87C520-QCL, DS87C520-MNL, DS87C520-MCL Datasheet

Note:

Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple

ugh various sales channels. For information about device

errata, click here:

http://www.maxim

-

ic.com/errata

.

DS87C520/DS83C520

www.maxim

-

ic.com

PRELIMINARY

FEATURES

§ 80C52-compatible

- 8051 pin and instruction set compatible

- Four 8-bit I/O ports

- Three 16-bit timer/counters

- 256 bytes scratchpad RAM

§ Large on-chip memory

- 16kB program memory

- 1kB extra on-chip SRAM for MOVX

§ ROMSIZE feature

- Selects internal ROM size from 0 to 16kB

- Allows access to entire external memory
map

- Dynamically adjustable by software

- Useful as boot block for external FLASH

§ High-speed architecture

- 4 clocks/machine cycle (8051 = 12)

- Runs DC to 33MHz clock rates

- Single-cycle instr uction in 121ns

- Dual data pointer

- Optional variable length MOVX to access
fast/slow RAM/peripherals

§ Power Management Mode

- Programmable clock source to save power

- CPU runs from (crystal/64) or
(crystal/1024)

- Provides automatic hardware and software
exit

§ EMI Reduction Mode disables ALE

§ Two full-duplex hardware serial ports

§ High integration controller includes:

- Power-Fail Reset

- Early -Warning Power-Fail Interrupt

- Programmable Watchdog Timer

§ 13 total interrupt sources with 6 external

§ Available in 40-pin PDIP, 44-pin PLCC,

44-pin TQFP, and 40-pin windowed CERDIP

§ Factory Mask DS83C520 or EPROM (OTP)

DS87C520

EPROM/ROM High-Speed Micro

PACKAGE OUTLINE

revisions of any device may be simultaneously available thro

1 of 42 070300

DS87C520/DS83C520

DESCRIPTION

The DS87C520/DS83C520 EPROM/ROM High-Speed Micro is a fast 8051-compatible microcontroller.
It features a redesigned processor core without wasted clock and memory cycles. As a result, it executes
every 8051 instruction between 1.5 and 3 times faster than the original for the same crystal speed.
Typical applications will see a speed improvement of 2.5 times using the same code and the same crystal.
The DS87C520/DS83C520 offers a maximum crystal speed of 33 MHz, resulting in apparent execution
speeds of 82.5 MHz (approximately 2.5X).

The DS87C520/DS83C520 is pin-compatible with all three packages of the standard 8051 and includes
standard resources such as three timer/counters, serial port, and four 8-bit I/O ports. It features 16 kB of
EPROM or Mask ROM with an extra 1 kB of data RAM. Both OTP and windowed packages are
available.

Besides greater speed, the microcontroller includes a second full hardware serial port, seven additional
interrupts, programmable Watchdog Timer, Brown-out Monitor, and Power-Fail Reset. The device also
provides dual data pointers (DPTRs) to speed block data memory moves. It also can adjust the speed of
MOVX data memory access from two to nine machine cycles for flexibility in selecting external memory
and peripherals.

A new Power Management Mode (PMM) is useful for portable applications. This feature allows software
to select a lower speed clock as the main time base. While normal operation has a machine cycle rate of 4
clocks per cycle, the PMM runs the processor at 64 or 1024 clocks per cycle. For example, at 12 MHz,
standard operation has a machine cycle rate of 3 MHz. In Power Management Mode, software can select
either 187.5 kHz or 11.7 kHz machine cycle rate. There is a corresponding reduction in power
consumption when the processor runs slower.

The EMI reduction feature allows software to select a reduced emission mode. This disables the ALE
signal when it is unneeded.

The DS83C520 is a factory Mask ROM version of the DS87C520 designed for high-volume, cost­sensitive applications. It is identical in all respects to the DS87C520, except that the 16 kB of EPROM is
replaced by a user-supplied application program. All references to features of the DS87C520 will apply to
the DS83C520, with the exception of EPROM-specific features where noted. Please contact your local
Dallas Semiconductor sales representative for ordering information.

ORDERING INFORMATION: DESCRIPTION

PART NUMBER PACKAGE MAX. CLOCK SPEED TEMPERATURE RANGE

DS87C520-MCL 40-pin plastic DIP 33 MHz 0°C to 70°C

DS87C520-QCL 44-pin PLCC 33 MHz 0°C to 70°C

DS87C520-ECL 44-pin TQFP 33 MHz 0°C to 70°C

DS87C520-MNL 40-pin plastic DIP 33 MHz -40°C to +85°C

DS87C520-QNL 44-pin PLCC 33 MHz -40°C to +85°C
DS87C520-ENL 44-pin TQFP 33 MHz -40°C to +85°C

DS87C520-WCL 40-pin windowed CERDIP 33 MHz 0°C to 70°C

DS83C520-MCL 40-pin plastic DIP 33 MHz 0°C to 70°C

DS83C520-QCL 44-pin PLCC 33 MHz 0°C to 70 °C

DS83C520-ECL 44-pin TQFP 33 MHz 0°C to 70°C

DS83C520-MNL 40-pin plastic DIP 33 MHz -40°C to +85°C

DS83C520-QNL 44-pin PLCC 33 MHz -40°C to +85°C
DS83C520-ENL 44-pin TQFP 33 MHz -40°C to +85°C

2 of 42

DS87C530/DS83C520 BLOCK DIAGRAM Figure 1

DS87C520/DS83C520

PIN DESCRIPTION Table 1

DIP PLCC TQFP SIGNAL

NAME

40 44 38 VCC VCC - +5V
20 22,23,

1

9 10 4 RST RST - input. The RST input pin contains a Schmitt

18
19

29 32 26

20
21

16, 17,

39

14
15

GND GND - Digital circuit ground.

voltage input to recognize external active high Reset
inputs. The pin also employs an internal pulldown resistor
to allow for a combination of wired OR external Reset
sources. An RC is not required for power-up, as the

device provides this function internally.
XTAL2
XTAL1

XTAL1, XTAL2 - The crystal oscillator pins XTAL1 and

XTAL2 provide support for parallel resonant, AT cut

crystals. XTAL1 acts also as an input if there is an external

clock source in place of a crystal. XTAL2 serves as the

output of the crystal amplifier.

PSEN PSEN - Output. The Program Store Enable output. This

signal is commonly connected to optional external ROM

memory as a chip enable. PSEN will provide an active

low pulse and is driven high when external ROM is not

being accessed.

DESCRIPTION

3 of 42

DS87C520/DS83C520

DIP PLCC TQFP SIGNAL

NAME

30 33 27 ALE ALE - Output. The Address Latch Enable output

functions as a clock to latch the external address LSB from

the multiplexed address/data bus on Port 0. This signal is

commonly connected to the latch enable of an external 373

family transparent latch. ALE has a pulse width of 1.5

XTAL1 cycles and a period of four XTAL1 cycles. ALE is

forced high when the DS87C520/DS83C520 is in a Reset

condition. ALE can also be disabled and forced high by

writing ALEOFF=1 (PMR.2). ALE operates

independently of ALEOFF during external memory

accesses.

39
38
37
36
35
34
33
32

1-8

1
2
3
4
5
6
7
8

43
42
41
40
39
38
37
36

2-9

2
3
4
5
6
7
8
9

37
36
35
34
33
32
31
30

40-44

1-3

40
41
42
43
44

1
2
3

P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)

P1.0-P1.7

Port 0 (AD0-7) - I/O. Port 0 is an open-drain 8-bit bi-

directional I/O port. As an alternate function Port 0 can

function as the multiplexed address/data bus to access off-

chip memory. During the time when ALE is high, the LSB

of a memo ry address is presented. When ALE falls to a

logic 0, the port transitions to a bi-directional data bus.

This bus is used to read external ROM and read/write

external RAM memory or peripherals. When used as a

memory bus, the port provides active high drivers. The

reset condition of Port 0 is tri-state. Pullup resistors are

required when using Port 0 as an I/O port.

Port 1 - I/O. Port 1 functions as both an 8-bit bi-

directional I/O port and an alternate functional interface

for Timer 2 I/O, new External Interrupts, and new Serial

Port 1. The reset condition of Port 1 is with all bits at a

logic 1. In this state, a weak pullup holds the port high.

This condition also serves as an input state, a weak pullup

holds the port high. This condition also serves as an input

mode, since any external circuit that writes to the port will

overcome the weak pullup. When software writes a 0 to

any port pin, the DS87C520/DS83C520 will activate a

strong pulldown that remains on until either a 1 is written

or a reset occurs. Writing a 1 after the port has been at 0

will cause a strong transition driver to turn on, followed by

a weaker sustaining pullup. Once the momentary strong

driver turns off, the port again becomes the output high

(and input) state. The alternate modes of Port 1 are out-

lines as follows.

Port Alternate Function

P1.0 T2 External I/O for Timer/Counter 2

P1.1 T2EX EX Timer/Counter 2

Capture/Reload Trigger

P1.2 RXD1 Serial Port 1 Input

P1.3 TXD1 Serial Port 1 Output

P1.4 INT2 External Interrupt 2 (Positive Edge

Detect)

P1.5 INT3 External Interrupt 3 (Negative

Edge Detect)

P1.6 INT4 External Interrupt 4 (Positive Edge

Detect)

P1.7 INT5 External Interrupt 5 (Negative

Edge Detect)

4 of 42

DESCRIPTION

DIP PLCC TQFP SIGNAL

21
22
23
24
25
26
27
28

10-17

10
11
12
13
14
15
16
17

31 35 29

- 12

24
25
26
27
28
29
30
31

11,

13-19

11
13
14
15
16
17
18
19

34

18
19
20
21
22
23
24
25

5, 7-13

5
7
8

9
10
11
12
13

6
28

DS87C520/DS83C520

DESCRIPTION

NAME

P2.0 (A8)

P2.1 (A9)
P2.2(A10)
P2.3(A11)
P2.4(A12)
P2.5(A13)
P2.6(A14)
P2.7(A15)

P3.0-P3.7

Port 2 (A8 -15) - I/O. Port 2 is a bi-directional I/O port.
The reset condition of Port 2 is logic high. In this state, a
weak pullup holds the port high. This condition also serves
as an input mode, since any external circuit that writes to
the port will overcome the weak pullup. When software
writes a 0 to any port pin, the DS87C520/DS83C520 will
activate a strong pulldown that remains on until either a 1
is written or a reset occurs. Writing a 1 after th e port has
been at 0 will cause a strong transition driver to turn on,
followed by a weaker sustaining pullup. Once the
momentary strong driver turns off, the port again becomes
both the output high and input state. As an alternate
function Port 2 can function as MSB of the external
address bus. This bus can be used to read external ROM
and read/write external RAM memory or peripherals.
Port 3 - I/O. Port 3 functions as both an 8-bit bi­directional I/O port and an alternate functional interface
for External Interrupts, Serial Port 0, Timer 0 and 1 Inputs,

and RD and WR strobes. The reset condition of Port 3 is
with all bits at a logic 1. In this state, a weak pullup holds
the port high. This condition also serves as an input mode,
since any external circuit that writes to the port will
overcome the weak pullup. When software writes a 0 to
any port pin, the DS87C520/DS83C520 will activate a
strong pulldown that remains on until either a 1 is written
or a reset occurs. Writing a 1 after the port has been at 0
will cause a strong transition driver to turn on, followed by
a weaker sustaining pullup. Once the momentary strong
driver turns off, the port again becomes both the output
high and input state. The alternate modes of Port 3 are
outlined below.

Port Alternate Mode

P3.0 RXD0 Serial Port 0 Input
P3.1 TXD0 Serial Port 0 Output

P3.2 INT0 External Interrupt 0
P3.3 INT1 External Interrupt 1

P3.4 T0 Timer 0 External Input
P3.5 T1 Timer 1 External Input

P3.6 WR External Data Memory Write Strobe
P3.7 RD External Data Memory Read Strobe

EA EA - Input. Connect to ground to force the

DS87C520/DS83C520 to use an external ROM. The
internal RAM is still accessible as determined by register

settin gs. Connect EA to VCC to use internal ROM.

NC NC - Reserved. These pins should not be connected. They

are reserved for use with future devices in this family.

5 of 42

DS87C520/DS83C520

COMPATIBILITY

The DS87C520/DS83C520 is a fully static CMOS 8051 compatible microcontroller designed for high
performance. In most cases the DS87C520/DS83C520 can drop into an existing socket for the 8xc51
family to improve the operation significantly. While remaining familiar to 8051 family users, it has many
new features. In general, software written for existing 8051 based systems works without modification
on the DS87C520/DS83C520. The exception is critical timing since the High-Speed Micro performs its
instructions much faster than the original for any given crystal selection. The DS87C520/DS83C520 runs
the standard 8051 family instruction set and is pin compatible with DIP, PLCC or TQFP packages.

The DS87C520/DS83C520 provides three 16-bit timer/ counters, full-duplex serial port (2), 256 bytes of
direct RAM plus 1 kB of extra MOVX RAM. I/O ports have the same operation as a standard 8051
product. Timers will default to a 12-clock per cycle operation to keep their timing compatible with
original 8051 family systems. However, timers are individually programmable to run at the new 4 clocks
per cycle if desired. The PCA is not supported.

The DS87C520/DS83C520 provides several new hardware features implemented by new Special
Function Registers. A summary of these SFRs is provided below.

PERFORMANCE OVERVIEW

The DS87C520/DS83C520 features a high-speed 8051 compatible core. Higher speed comes not just
from increasing the clock frequency, but from a newer, more efficient design.

This updated core does not have the dummy memory cycles that are present in a standard 8051. A
conventional 8051 generates machine cycles using the clock frequency divided by 12. In the
DS87C520/DS83C520, the same machine cycle takes 4 clocks. Thus the fastest instruction, 1 machine
cycle, executes three times faster for the same crystal frequency. Note that these are identical instructions.
The majority of instructions on the DS87C520/DS83C520 will see the full 3 to 1 speed improvement.
Some instructions will get between 1.5 and 2.4 to 1 improvement. All instructions are faster than the
original 8051.

The numerical average of all opcodes gives approximately a 2.5 to 1 speed improvement. Improvement of
individual programs will depend on the actual instructions used. Speed-sensitive applications would make
the most use of instructions that are three times faster. However, the sheer number of 3 to 1 improved
opcodes makes dramatic speed improvements likely for any code. These architecture improvements
produce a peak instruction cycle in 121 ns (8.25 MIPs). The Dual Data Pointer feature also allows the
user to eliminate wasted instructions when moving blocks of memory.

INSTRUCTION SET SUMMARY

All instructions perform the same functions as their 8051 counterparts. Their effect on bits, flags, and
other status functions is identical. However, the timing of each instruction is different. This applies both
in absolute and relative number of clocks.

For absolute timing of real-time events, the timing of software loops can be calculated using a table in the
High-Speed Microcontroller User’s Guid e. However, counter/timers default to run at the older 12 clocks
per increment. In this way, timer-based events occur at the standard intervals with software executing at
higher speed. Timers optionally can run at 4 clocks per increment to take advantage of faster processor
operation.

6 of 42

DS87C520/DS83C520

The relative time of two instructions might be different in the new architecture than it was previously. For
example, in the original architecture, the “MOVX A, @DPTR” instruction and the “MOV direct, direct”
instruction used two machine cycles or 24 oscillator cycles. Therefore, they required the same amount of
time. In the DS87C520/DS83C520, the MOVX instruction takes as little as two machine cycles or eight
oscillator cycles but the “MOV direct, direct” uses three machine cycles or 12 oscillator cycles. While
both are faster than their original counterparts, they now have different execution times. This is because
the DS87C520/DS83C520 usually uses one instruction cycle for each instruction byte. The user
concerned with precise program timing should examine the timing of each instruction for familiarity with
the changes. Note that a machine cycle now requires just 4 clocks, and provides one ALE pulse per cycle.
Many instructions require only one cycle, but some require five. In the original architecture, all were one
or two cycles except for MUL and DIV. Refer to the High-Speed Microcontroller User’s Guide for details
and individual instruction timing.

SPECIAL FUNCTION REGISTERS

Special Function Registers (SFRs) control most special features of the DS87C520/DS83C520. This
allows the DS87C520/DS83C520 to have many new features but use the same instruction set as the 8051.
When writing software to use a new feature, an equate statement defines the SFR to an assembler or
compiler. This is the only change needed to access the new function. The DS87C520/DS83C520
duplicates the SFRs contained in the standard 80C52. Table 2 shows the register addresses and bit
locations. The High-Speed Microcontroller User’s Guide describes all SFRs.

7 of 42

DS87C520/DS83C520

SPECIAL FUNCTION REGISTER LOCATIONS Table 2

* New functions are in bold

REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ADDRESS

P0
SP
DPL
DPH

DPL1
DPH1
DPS

PCON
TCON
TMOD
TL0
TL1
TH0
TH1

CKCON

PORT1

EXIF

SCON0
SBUF0
P2
IE
SADDR0
SADDR1
P3
IP
SADEN0
SADEN1

SCON1
SBUF1
ROMSIZE
PMR
STATUS
TA

T2CON
T2MOD
RCAP2L
RCAP2H
TL2
TH2
PSW

WDCON

ACC

EIE

B

EIP

P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 80h

81h
82h
83h
84h
85h

0 0 0 0 0 0 0 SEL 86h

SMOD_0 SMOD0 - - GF1 GF0 STOP IDLE 87h

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 88h

GATE

8Ah
8Bh
8Ch
8Dh

WD1 WD0 T2M T1M T0M MD2 MD1 MD0 8Eh

P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 90h

IE5 IE4 IE3 IE

SM0/FE_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 98h

99h

P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 A0h

EA ES1 ET2 ES0 ET1 EX1 ET0 EX0 A8h

A9h
AAh

P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 B0h

- PS1 PT2 PS0 PT1 PX1 PT0 PX0 B8h
B9h
BAh

SM0/FE_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 R1_1 C0h

SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0 C1h

- - - - - RMS2 RMS1 RMS0 C2h

CD1 CD0 SWB - XTOFF ALEOFF DME1 DME0 C4h

PIP HIP LIP XTUP SPTA1 SPTA1 SPTA0 SPRA0 C5h

C7h

TF2 EXF2 RCLK TCLK EXEN2 TR2

- - - - - - T2OE DCEN C9h
CAh
CBh
CCh
CDh

CY AC F0 RS1 RS0 OV FL P D0h

SMOD_1 POR EPFI PFI WDIF WTRF EWT RWT D8h

E0h

- - - EWDI EX5 EX4 EX3 EX2 E8h
F0h

- - - PWDI PX5 PX4 PX3 PX2 F8h

C/T

M1 M0 GATE

XT/ RG

C/T

RGMD RGSL BGS 91h

M1 M0 89h

C/T2 C/ RL2

C8h

8 of 42

DS87C520/DS83C520

MEMORY RESOURCES

Like the 8051, the DS87C520/DS83C520 uses three memory areas. The total memory configuration of
the DS87C520/DS83C520 is 16 kB of ROM, 1 kB of data SRAM and 256 bytes of scratchpad or direct
RAM. The 1 kB of data space SRAM is read/write accessible and is memory mapped. This on-chip
SRAM is reached by the MOVX instruction. It is not used fo r executable memory. The scratchpad area is
256 bytes of register mapped RAM and is identical to the RAM found on the 80C52. There is no conflict
or overlap among the 256 bytes and the 1 kB as they use different addressing modes and separate
instructions.

OPERATIONAL CONSIDERATION

The erasure window of the windowed CERDIP should be covered without regard to the
programmed/unprogrammed state of the EPROM. Otherwise, the device may not meet the AC and DC
parameters listed in the datasheet.

PROGRAM MEMORY ACCESS

On-chip ROM begins at address 0000h and is contiguous through 3FFFh (16 kB). Exceeding the
maximum address of on-chip ROM will cause the device to access off-chip memory. However, the
maximum on-chip decoded address is selectable by software using the ROMSIZE feature. Software can
cause the DS87C520/DS83C520 to behave like a device with less on-chip memory. This is beneficial
when overlapping external memory, such as Flash, is used. The maximum memory size is dynamically
variable. Thus a portion of memory can be removed from the memory map to access off-chip memory,
then restored to access on-chip memory. In fact, all of the on-chip memory can be removed from the
memory map allowing the full 64 kB memory space to be addressed from off-chip memory. ROM
addresses that are larger than the selected maximum are automatically fetched from outside the part via
Ports 0 and 2. A depiction of the ROM memory map is shown in Figure 2.

The ROMSIZE register is used to select the maximum on-chip decoded address for ROM. Bits RMS2,
RMS1, RMS0 have the following affect.

RMS2 RMS1 RMS0 Maximum on-chip ROM Address

0 0 0 0 kB
0 0 1 1 kB/03FFh
0 1 0 2 kB/07FFh
0 1 1 4 kB/0FFFh
1 0 0 8 kB/1FFFh
1 0 1 16 kB (default)/3FFFh
1 1 0 Invalid - reserved
1 1 1 Invalid - reserved

The reset default condition is a maximum on-chip ROM address of 16 kB. Thus no action is required if
this feature is not used. When accessing external program memory, the first 16 kB would be inaccessible.
To select a smaller effective ROM size, software must alter bits RMS2-RMS0. Altering these bits
requires a Timed Access procedure as explained later.

Care should be taken so that changing the ROMSIZE register does not corrupt program execution. For
example, assume that a DS87C520/DS83C520 is executing instructions from internal program memory
near the 12 kB boundary (~3000h) and that the ROMSIZE register is currently configured for a 16 kB
internal program space. If software reconfigures the ROMSIZE register to 4 kB (0000h-0FFFh) in the
current state, the device will immediately jump to external program execution because program code

9 of 42

DS87C520/DS83C520

from 4 kB to 16 kB (1000h-3FFFh) is no longer located on-chip. This could result in code misalignment
and execution of an invalid instruction. The recommended method is to modify the ROMSIZE register
from a location in memory that will be internal (or external) both before and after the operation. In the
above example, the instruction which modifies the ROMSIZE register should be located below the 4 kB
(1000h) boundary, so that it will be unaffected by the memory modification. The same precaution should
be applied if the internal program memory size is modified while executing from external program
memory.

Off-chip memory is accessed using the multiple xed address/data bus on P0 and the MSB address on P2.
While serving as a memory bus, these pins are not I/O ports. This convention follows the standard 8051
method of expanding on-chip memory. Off-chip ROM access also occurs if the EA pin is a logic 0. EA

overrides all bit settings. The PSEN signal will go active (low) to serve as a chip enable or output enable
when Ports 0 and 2 fetch from external ROM.

ROM MEMORY MAP Figure 2

ROM SIZ E ADJUSTABLE ROM SIZE IGNORED
DEFAULT = 16K BYTES

DATA MEMORY ACCESS

Unlike many 8051 derivatives, the DS87C520/DS83C520 contains on-chip data memory. It also contains
the standard 256 bytes of RAM accessed by direct instructions. These areas are separate. The MOVX
instruction accesses the on-chip data memory. Although physically on-chip, software treats this area as
though it was located off-chip. The 1 kB of SRAM is between address 0000h and 03FFh.

Access to the on-chip data RAM is optional under software control. When enabled by software, the data
SRAM is between 0000h and 03FFh. Any MOVX instruction that uses this area will go to the on-chip
RAM while enabled. MOVX addresses greater tha n 03FFh automatically go to external memory through
Ports 0 and 2.

When disabled, the 1 kB memory area is transparent to the system memory map. Any MOVX directed to
the space between 0000h and FFFFh goes to the expanded bus on Ports 0 and 2. This also is the default
condition. This default allows the DS87C520/DS83C520 to drop into an existing system that uses these
addresses for other hardware and still have full compatibility.

The on-chip data area is software selectable using 2 bits in the Power Mana gement Register at location
C4h. This selection is dynamically programmable. Thus access to the on-chip area becomes transparent
to reach off-chip devices at the same addresses. The control bits are DME1 (PMR.1) and DME0
(PMR.0). They have the following operation:

10 of 42

DS87C520/DS83C520

DATA MEMORY ACCESS CONTROL Table 3

DME1 DME0 DATA MEMEORY ADDRESS MEMORY FUNCTION

0 0 0000h-FFFFh External Data Memory *Default condition
0 1 0000h-03FFh

0400h-FFFFh
1 0 Reserved Reserved
1 1 0000h-03FFh

0400h-FFFBh

FFFCh

FFFDh-FFFFh

Internal SRAM Data Memory
External Data Memory

Internal SRAM Data Memory
Reserved - no external access
Read access to the status of lock bits
Reserved - no external access

Notes on the status byte read at FFFCh with DME1, 0 = 1, 1: Bits 2-0 reflect the progra mmed status of
the security lock bits LB2 -LB0. They are individually set to a logic 1 to correspond to a security lock bit
that has been programmed. These status bits allow software to verify that the part has been locked before
running if desired. The bits are read only.

Note: After internal MOVX SRAM has been initialized, changing DME0/1 bits will have no effect on the
contents of the SRAM.

STRETCH MEMORY CYCLE

The DS87C520/DS83C520 allows software to adjust the speed of off-chip data memory access. The
microcontroller is capable of performing the MOVX in as few as two instruction cycles. The on-chip
SRAM uses this speed and any MOVX instruction directed internally uses two cycles. However, the time
can be stretched for interface to external devices. This allows access to both fast memory and slow
memory or peripherals with no glue logic. Even in high-speed systems, it may not be necessary or
desirable to perform off-chip data memory access at full speed. In addition, there are a variety of memory
mapped peripherals such as LCDs or UARTs that are slow.

The Stretch MOVX is controlled by the Clock Control Register at SFR location 8Eh as described below.
It allows the user to select a Stretch value between 0 and 7. A Stretch of 0 will result in a two -machine
cycle MOVX. A Stretch of 7 will result in a MOVX of nine machine cycles. Software can dynamically
change this value depending on the particular memory or peripheral.

On reset, the Stretch value will default to a 1, resulting in a three-cycle MOVX for any external access.
Therefore, off-chip RAM access is not at full speed. This is a convenience to existing designs that may
not have fast RAM in place. Internal SRAM access is always at full speed regardless of the Stretch
setting. When desiring maximum speed, software should select a Stretch value of 0. When using very
slow RAM or peripherals, select a larger Stretch value. Note that this affects data memory only and the
only way to slow program memory (ROM) access is to use a slower crystal.

Using a Stretch value between 1 and 7 causes the microcontroller to stretch the read/write strobe and all
related timing. Also, setup and hold times are increased by 1 clock when using any Stretch greater than 0.
This results in a wider read/write strobe and relaxed interface timing, allowing more time for
memory/peripherals to respond. The timing of the variable speed MOVX is in the Electrical
Specifications. Table 4 shows the resulting strobe widths for each Stretch value. The memory Stretch
uses the Clock Control Special Function Register at SFR location 8Eh. The Stretch value is selected using
bits CKCON.2-0. In the table, these bits are referred to as M2 through M0. The first Stretch (default)
allows the use of common 120 ns RAMs without dramatically lengthening the memory access.

11 of 42

DS87C520/DS83C520

DATA MEMORY CYCLE STRETCH VALUES Table 4

CKCON.2-0 RD OR WR STROBE STROBE WIDTH TIME
M2 M1 M0 MEMORY CYCLES WIDTH IN CLOCKS @ 33 MHz

0 0 0 2 (forced internal) 2 60 ns
0 0 1 3 (default external) 4 121 ns
0 1 0 4 8 242 ns
0 1 1 5 12 364 ns
1 0 0 6 16 485 ns
1 0 1 7 20 606 ns
1 1 0 8 24 727 ns
1 1 1 9 28 848 ns

DUAL DATA POINTER

The timing of block moves of data memory is faster using the Dual Data Pointer (DPTR). The standard
8051 DPTR is a 16-bit value that is used to address off-chip data RAM or peripherals. In the
DS87C520/DS83C520, this data pointer is called DPTR0, located at SFR addresses 82h and 83h. These
are the original locations. Using DPTR requires no modification of standard code. The new DPTR at
SFR 84h and 85h is called DPTR1. The DPTR Select bit (DPS ) chooses the active pointer. Its location is
the lsb of the SFR location 86h. No other bits in register 86h have any effect and are 0. The user switches
between data pointers by toggling the lsb of register 86h. The increment (INC) instruction is the fastest
way to accomplish this. All DPTR-related instructions use the currently selected DPTR for any activity.
Therefore it takes only one instruction to switch from a source to a destination address. Using the Dual
Data Pointer saves code from needing to save source and destination addresses when doing a block move.
The software simply switches between DPTR0 and 1 once software loads them. The relevant register
locations are as follows:

DPL 82h Low byte original DPTR
DPH 83h High byte original DPTR
DPL1 84h Low byte new DPTR
DPH1 85h High byte new DPTR
DPS 86h DPTR Select (lsb)

POWER MANAGEMENT

Along with the standard Idle and power down (Stop) modes of the standard 80C52, the
DS87C520/DS83C520 provides a new Power Management Mode. This mode allows the processor to
continue functioning, yet to save power compared with full operation. The DS87C520/DS83C520 also
features several enhancements to Stop mode that make it more useful.

POWER MANAGEMENT MODE (PMM)

Power Management Mode offers a complete scheme of reduced internal clock speeds that allow the CPU
to run software but to use substantially less power. During default operation, the DS87C520/DS83C520
uses four clocks per machine cycle. Thus the instruction cycle rate is Clock/4. At 33 MHz crystal speed,
the instruction cycle speed is 8.25 MHz (33/4). In PMM, the microcontroller continues to operate but uses
an internally divided version of the clock source. This creates a lower power state without external
components. It offers a choice of two reduced instruction cycle speeds (and two clock sources - discussed
below). The speeds are (Clock/64) and (Clock/1024).

12 of 42

DS87C520/DS83C520

Software is the only mechanism to invoke the PMM. Table 5 illustrates the instruction cycle rate in
PMM for several common crystal frequencies. Since power consumption is a direct function of operating
speed, PMM 1 eliminates most of the power consumption while still allowing a reasonable speed of
processing. PMM 2 runs very slow and provides the lowest power consumption without stopping the
CPU. This is illustrated in Table 6.

Note that PMM provides a lower power condition than Idle mode. This is because in Idle mode, all
clocked functions such as timers run at a rate of crystal divided by 4. Since wake-up from PMM is as fast
as or faster than from Idle and PMM allows the CPU to operate (even if doing NOPs), there is little
reason to use Idle mode in new designs.

MACHINE CYCLE RATE Table 5

CRYSTAL SPEED FULL OPERATION

(4 CLOCKS)

11.0592 MHz 2.765 MHz 172.8 kHz 10.8 kHz
16 MHz 4.00 MHz 250.0 kHz 15.6 kHz
25 MHz 6.25 MHz 390.6 kHz 24.4 kHz
33 MHz 8.25 MHz 515.6 kHz 32.2 kHz

PMM1

(64 CLOCKS)

PMM2

(1024 CLOCKS)

TYPICAL OPERATING CURRENT IN PMM Table 6

CRYSTAL SPEED FULL OPERATION

(4 CLOCKS)

11.0592 MHz 13.1 mA 5.3 mA 4.8 mA
16 MHz 17.2 mA 6.4 mA 5.6 mA
25 MHz 25.7 mA 8.1 mA 7.0 mA
33 MHz 32.8 mA 9.8 mA 8.2 mA

PMM1

(64 CLOCKS)

PMM2

(1024 CLOCKS)

CRYSTALESS PMM

A major component of power consumption in PMM is the crystal amplifier circuit. The
DS87C520/DS83C520 allows the user to switch CPU operation to an internal ring oscillator and turn off
the crystal amplifier. The CPU would then have a clock source of approximately 2-4 MHz, divided by
either 4, 64, or 1024. The ring is not accurate, so software can not perform precision timing. However,
this mode allows an additional saving of between 0.5 and 6.0 mA, depending on the actual crystal
frequency. While this saving is of little use when running at 4 clocks per instruction cycle, it makes a
major contribution when running in PMM1 or PMM2.

PMM OPERATION

Software invokes the PMM by setting the appropriate bits in the SFR area. The basic choices are divider
speed and clock source. There are three speeds (4, 64, and 1024) and two clock sources (crystal and ring).
Both the decisions and the controls are separate. Software will typically select the clock speed first. Then,
it will perform the switch to ring operation if des ired. Lastly, software can disable the crystal amplifier if
desired.

There are two ways of exiting PMM. Software can remove the condition by reversing the procedure that
invoked PMM or hardware can (optionally) remove it. To resume operation at a divide by 4 rate under
software control, simply select 4 clocks per cycle, then crystal based operation if relevant. When
disabling the crystal as the time base in favor of the ring oscillator, there are timing restrictions associated
with restarting the crystal operation. Details are described below.

13 of 42