Dallas Semiconductor DS877C550-QNL, DS877C550-QCL, DS877C550-KCL, DS877C550-FNL, DS877C550-FCL Datasheet

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FEATURES

§ 87C52-Compatible

- 8051 pin- and instruction set-compatible

- Three 16-bit timer/counters

- 256 bytes scratchpad RAM

§ On-chip Memory

- 8 kbytes EPROM (OTP & Windowed Packages)

- 1 kbyte extra on-chip SRAM for MOVX access

§ On-chip Analog to Digital Converter

- Eight channels of analog input, 10-bit resolution

- Fast conversion time

- Selectable internal or external reference voltage

§ Pulse Width Modulator Outputs

- Four channels of 8-bit PWM

- Channels cascadable to 16-bit PWM

§ 4 Capture + 3 Compare Registers

§ 55 I/O Port Pins

§ New Dual Data Pointer Operation

- Either data pointer can be incremented or

decremented

§ ROMSIZE Feature

- Selects effective on-chip ROM size from 0 to 8k

- Allows access to entire external memory map

- Dynamically adjustable by software

§ High-Speed Architecture

- 4 clocks/machine cycle (8051 = 12)

- Runs DC to 33 MHz clock rates

- Single-cycle instruction in 121 ns

- New Stretch Cycle feature allows access to

fast/slow memory or peripherals

§ Unique Power Savings Modes

§ EMI Reduction Mode disables ALE when not

needed

§ High integration controller includes:

- Power-fail reset

- Early-warning power-fail interrupt

- Two full-duplex hardware serial ports

- Programmable watchdog timer

§ 16 total interrupt sources with 6 external

Available in 68-pin PLCC, 80-pin PQFP, and
68-pin windowed CLCC

PIN ASSIGNMENT

DS87C550

EPROM High-Speed

Micro with A/D and PWM

www.dalsemi.com

9

1

61

27 43

10

26

60

44

68-Pin PLCC

68-Pin WINDOWED CLCC

DALLAS

DS87C550

1

24

64

41

4025

6580

DALLAS

DS87C550

80-Pin PQFP

DS87C550

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DESCRIPTION

The DS87C550 EPROM High-Speed Micro with A/D and PWM is a member of the fastest 100% 8051­compatible microcontroller family available. It features a redesigned processor core that removes wasted
clock and memory cycles. As a result, it executes 8051 instructions up to three times faster than the
original architecture for the same crystal speed. The DS87C550 also offers a maximum crystal speed of
33 MHz, resulting in apparent execution speeds of up to 99 MHz.

The DS87C550 uses an industry standard 8051 pin-out and includes standard resources such as three
timer/counters, and 256 bytes of scratchpad RAM. This device also features 8 kbytes of EPROM with an
extra 1 kbyte of data RAM (in addition to the 256 bytes of scratchpad RAM), and 55 I/O ports pins. Both
One-Time-Programmable (OTP) and windowed packages are available.

Besides greater speed, the DS87C550 includes a second full hardware serial port, seven additional
interrupts, a programmable watchdog timer, brownout monitor, and power-fail reset.

The DS87C550 also provides dual data pointers (DPTRs) to speed block data memory moves. The user
can also dynamically adjust the speed of external accesses between two and 12 machine cycles for
flexibility in selecting memory and peripherals.

Power Management Mode (PMM) is useful for portable or battery-powered applications. This feature
allows software to select a lower speed clock as the main time base. While normal operation has a
machine cycle rate of 4 clocks per cycle, the PMM allows the processor to run at 1024 clocks per cycle.
For example, at 12 MHz, standard operation has a machine cycle rate of 3 MHz. In Power Management
Mode, software can select an 11.7 kHz (12 MHz/1024) machine cycle rate. There is a corresponding
reduction in power consumption due to the processor running slower.

The DS87C550 also offers two features that can significantly reduce electromagnetic interference (EMI).
One EMI reduction feature allows software to select a reduced emission mode that disables the ALE
signal when it is unneeded. The other EMI reduction feature controls the current to the address and data
pins interfacing to external devices producing a controlled transition of these signals.

ORDERING INFORMATION

PART NUMBER PACKAGE MAX. CLOCK SPEED TEMPERATURE RANGE

DS87C550-QCL 68-pin PLCC 33 MHz 0°C to +70°C
DS87C550-FCL 80-pin PQFP 33 MHz 0°C to +70°C
DS87C550-QNL 68-pin PLCC 33 MHz -40°C to +85°C
DS87C550-FNL 80-pin PQFP 33 MHz -40°C to +85°C
DS87C550-KCL 68-pin windowed CLCC 33 MHz 0°C to 70°C

DS87C550

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DS87C550 BLOCK DIAGRAM Figure 1

DS87C550

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PIN DESCRIPTION Table 1

PLCC/

CLCC QFP SIGNAL NAME DESCRIPTION

2 72 V

CC

VCC - Digital +5V power input.

36
37

34
35

GND GND – Digital ground.

15 9 RST RST - I/O. The RST input pin contains a Schmitt voltage input to recognize

external active high Reset inputs. The pin also employs an internal pulldown
resistor to allow for a combination of wired OR external Reset sources. An RC is
not required for power-up, as the DS87C550 provides this function internally.
This pin also acts as an output when the source of the reset is internal to the device
(i.e., watchdog timer, power-fail, or crystal-fail detect). In this case, the RST pin
will be held high while the processor is in a Reset state, and will return to low as
the processor exits this state. When this output capability is used, the RST pin

should not be connected to an RC network or a logic output driver.
35
34

32
31

XTAL1
XTAL2

Input - The crystal oscillator pins XTAL1 and XTAL2 provide support for

fundamental mode, parallel resonant, AT cut crystals. XTAL1 acts also as an input

if there is an external clock source in place of a crystal. XTAL2 serves as the

output of the crystal amplifier. Note that this output cannot be used to drive any

additional load when a crystal is attached as this can disturb the oscillator circuit.
47 48

PSEN PSEN

- Output. The Program Store Enable output. This signal is commonly

connected to optional external ROM memory as a chip enable.

PSEN

will provide
an active low pulse during a program byte access, and is driven high when not
accessing external program memory.

48 49 ALE ALE - Output. The Address Latch Enable output functions as a clock to latch the

external address LSB from the multiplexed address/data bus on Port 0. This signal
is commonly connected to the latch enable of an external 373 family transparent
latch. ALE is driven high when the DS87C550 is in a Reset condition. ALE can
also be disabled and forced high using the EMI reduction mode ALEOFF.

49 50

EA

EA - Input. An active low input pin that when connected to ground will force the

DS87C550 to use an external program memory. The internal RAM is still
accessible as determined by register settings. EA should be connected to VCC to

use internal program memory. The input level on this pin is latched at reset.

16-23 10-17 P1.0-P1.7 Port 1 - I/O. Port 1 functions as both an 8-bit, bi-directional I/O port and an

alternate functional interface for several internal resources. The reset condition of
Port 1 is all bits at logic 1. In this state, a weak pullup holds the port high. This
condition allows the pins to serve as both input and output. Input is possible since
any external circuit whose output drives the port will overcome the weak pullup.
When software writes a 0 to any Port 1 pin, the DS87C550 will activate a strong
pulldown that remains on until either a 1 is written or a reset occurs. Writing a 1
after the port has been at 0 will cause a strong transition driver to turn on, followed
by a weaker sustaining pullup. Once the momentary strong driver turns off, the
port again returns to a weakly held high output (and input) state. The alternate
functions of Port 1 pins are detailed below. Note that when the Capture/Compare
functions of timer 2 are used, the interrupt input pins become capture trigger
inputs.

Port Alternate Function

16 10 P1.0 INT2/CT0 External Interrupt 2/Capture Trigger 0
17 11 P1.1 INT3/CT1 External Interrupt 3/Capture Trigger 1
18 12 P1.2 INT4/CT2 External Interrupt 4/Capture Trigger 2
19 13 P1.3 INT5/CT3 External Interrupt 5/Capture Trigger 3
20 14 P1.4 T2 External I/O for Timer/Counter 2
21 15 P1.5 T2EX Timer/Counter 2 Capture/Reload Trigger
22 16 P1.6 RXD1 Serial Port 1 Input
23 17 P1.7 TXD1 Serial Port 1 Output

DS87C550

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PLCC/

CLCC QFP SIGNAL NAME DESCRIPTION

50-57

57
56
55
54
53
52
51
50

51-58

58
57
56
55
54
53
52
51

P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)

Port 0-I/O - AD0-7. Port 0 is an open-drain 8-bit, bi-directional general-purpose
I/O port. When used in this mode pullup resistors are required to provide a logic 1
output. As an alternate function, Port 0 operates as a multiplexed address/data bus
to access off-chip memory or peripherals. In this mode, the LSB of the memory
address is output on the bus during the time that ALE is high. When ALE falls to
a logic 0, the port transitions to a bi-directional data bus. In this mode, the port
provides active high drivers for logic 1 output. The reset condition of Port 0 is tri­state (i.e., the open drain devices are off).

39-46

39
40
41
42
43
44
45
46

38-42
45-47

38
39
40
41
42
45
46
47

P2.0 (A8)

P2.1 (A9)
P2.2 (A10)
P2.3 (A11)
P2.4 (A12)
P2.5 (A13)
P2.6 (A14)
P2.7 (A15)

Port 2-I/O Address A15:A8. Port 2 functions as an 8-bit bi-directional I/O port
or alternately as an external address bus (A15-A8). The reset condition of Port 2 is
logic high I/O state. In this state, weak pullups hold the port high allowing the
pins to be used as an input or output as described above for Port 1. As an alternate
function Port 2 can function as MSB of the external address bus. This bus can be
used to read external memory or peripherals.

24-31 18-20

23-27

P3.0-P3.7 Port 3 - I/O. Port 3 functions as an 8-bit bi-directional I/O port or alternately as

an interface for External Interrupts, Serial Port 0, Timer 0 & 1 Inputs, and RD and

WR

strobes. When functioning as an I/O port, these pins operate as indicated

above for Port 1. The alternate modes of Port 3 are detailed below.

Port Alternate Mode

24 18 P3.0 RXD0 Serial Port 0 Input
25 19 P3.1 TXD0 Serial Port 0 Output
26 20

P3.2

INT0

External Interrupt 0

27 23

P3.3

INT1

External Interrupt 1
28 24 P3.4 T0 Timer 0 External Input
29 25 P3.5 T1 Timer 1 External Input
30 26

P3.6

WR

External Data Memory Write Strobe
31 27

P3.7 RD External Data Memory Read Strobe

7-14 80

1-2
4-8

P4.0-P4.7 Port 4 - I/O. Port 4 functions as an 8-bit bi-directional I/O port or alternately as

an interface to Timer 2’s Capture Compare functions. When functioning as an I/O
port, these pins operate as indicated in the Port 1 description. The alternate modes
of Port 4 are detailed below.

Port 4 Alternate Mode

7 80 P4.0 CMSR0 Timer 2 compare match set/reset output 0
8 1 P4.1 CMSR1 Timer 2 compare match set/reset output 1

9 2 P4.2 CMSR2 Timer 2 compare match set/reset output 2
10 4 P4.3 CMSR3 Timer 2 compare match set/reset output 3
11 5 P4.4 CMSR4 Timer 2 compare match set/reset output 4
12 6 P4.5 CMSR5 Timer 2 compare match set/reset output 5
13 7 P4.6 CMT0 Timer 2 compare match toggle output 0
14 8 P4.7 CMT1 Timer 2 compare match toggle output 1

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PLCC/

CLCC QFP SIGNAL NAME DESCRIPTION

1,

62-68

64-71 P5.0-P5.7 Port 5 - I/O. Port 5 functions as an open-drain 8-bit bi-directional I/O port or

alternately as an interface to the A/D converter. When used for general purpose
I/O, these pins operate in a quasi-bi-directional mode. Writing a logic 1 to these
pins (reset condition) will cause them to tri-state. This allows the pins to serve as
inputs since the tri-state condition can be driven by an external device. If a logic 0
is written to a pin, it is pulled down internally and therefore serves as an output
pin containing a logic 0. Because these pins are open-drain, external pullup
resistors are required to create a logic 1 level when they are used as outputs. As
an alternate function Port 5 pins operate as the analog inputs for the A/D
converter as described below.

Port Alternate Mode

1 71 P5.0 ADC0 Analog to Digital Converter input channel 0
68 70 P5.1 ADC1 Analog to Digital Converter input channel 1
67 69 P5.2 ADC2 Analog to Digital Converter input channel 2
66 68 P5.3 ADC3 Analog to Digital Converter input channel 3
65 67 P5.4 ADC4 Analog to Digital Converter input channel 4
64 66 P5.5 ADC5 Analog to Digital Converter input channel 5
63 65 P5.6 ADC6 Analog to Digital Converter input channel 6
62 64 P5.7 ADC7 Analog to Digital Converter input channel 7

3-6, 32

33, 38

28, 29

37

74-77

P6.0-P6.5

P6.7

Port 6 - I/O. Port 6 functions as an 6-bit bi-directional I/O port or alternately as
an interface to the PWM and A/D on-board peripherals. As an I/O port, these pins
operate as described in Port 1. The alternate modes of Port 6 are detailed below.

Port Alternate Function

4 75 P6.0 PWMO0 PWM channel 0 output

5 76 P6.1 PWMO1 PWM channel 1 output
32 28 P6.2 PWMO2 PWM channel 2 output
33 29 P6.3 PWMO3 PWM channel 3 output

6 77 P6.4 PWMC0 PWM0 clock input
38 37 P6.5 PWMC1 PWM1 clock input

3 74 P6.7 STADC External A/D conversion start signal (active low)
59 60 A

vref+

A/D +Reference - Input. When selected, supplies the positive reference voltage
for the A/D converter. This signal should be isolated from digital VCC to prevent
noise from affecting A/D measurements.

58 59 A

vref-

A/D -Reference - Input. When selected, supplies the negative reference voltage
for the A/D converter. This signal should be isolated from digital GND to prevent
noise from affecting A/D measurements.

61 63 A

VCC

Analog V

CC

60 61 A

VSS

Analog Ground

3, 21
22, 30
33, 36
43, 44
62, 73
78, 79

NC NC-Reserved. These pins should not be connected. They are reserved for use

with future devices in this family.

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COMPATIBILITY

The DS87C550 is a fully static, CMOS 8051-compatible microcontroller designed for high performance.
While remaining familiar to 8051 family users, it has many new features. With very few exceptions,
software written for existing 8051-based systems works without modification on the DS87C550. The
exception is critical timing since the High Speed Micro performs its instructions much faster than the
original for any given crystal selection. The DS87C550 runs the standard 8051 family instruction set and
is pin-compatible with existing devices with similar features in PLCC or QFP packages.

The DS87C550 provides three 16-bit timer/counters, two full-duplex serial ports, 256 bytes of direct
RAM plus 1 kbyte of extra MOVX RAM. I/O ports have the same operation as a standard 8051 product.
Timers will default to a 12 clock per cycle operation to keep their timing compatible with original 8051
family systems. However, timers are individually programmable to run at the new 4 clocks per cycle if
desired.

The DS87C550 provides several new hardware features implemented by new Special Function Registers.
A summary of all SFRs is provided in Table 2.

PERFORMANCE OVERVIEW

The DS87C550 features a high-speed, 8051-compatible core. Higher speed comes not just from
increasing the clock frequency, but from a newer, more efficient design.

This updated core does not have the dummy memory cycles that are present in a standard 8051. A
conventional 8051 generates machine cycles using the clock frequency divided by 12. In the DS87C550,
the same machine cycle takes 4 clocks. Thus the fastest instruction, 1 machine cycle, executes three times
faster for the same crystal frequency. Note that these are identical instructions. The majority of
instructions on the DS87C550 will see the full 3 to 1 speed improvement. However, some instructions
will achieve between 1.5 and 2.4 to 1 improvement. Regardless of specific performance improvements,
all instructions are faster than the original 8051.

The numerical average of all opcodes gives approximately a 2.5 to 1 speed improvement. Improvement of
individual programs will depend on the actual mix of instructions used. Speed sensitive applications
would make the most use of instructions that are 3 times faster. However, the sheer number of 3 to 1
improved opcodes makes dramatic speed improvements likely for any arbitrary combination of
instructions. These architecture improvements and the sub-micron CMOS design produce a peak
instruction cycle in 121 ns (8.25 MIPs). The Dual Data Pointer feature also allows the user to eliminate
wasted instructions when moving blocks of memory.

INSTRUCTION SET SUMMARY

All instructions in the DS87C550 perform exactly the same functions as their 8051 counterparts. Their
effect on bits, flags, and other status functions is identical. However, the timing of each instruction is
different. This applies both in absolute and relative number of clocks.

For absolute timing of real-time events, the timing of software loops can be calculated using a table in the
High Speed Micro User’s Guide. However, counter/timers default to run at the old 12 clocks per
increment. In this way, timer-based events occur at the standard intervals with software executing at
higher speed. Timers optionally can run at 4 clocks per increment to take advantage of faster processor
operation.

The relative time of two instructions might be different in the new architecture than it was previously. For
example, in the original architecture, the “MOVX A, @DPTR” instruction and the “MOV direct, direct”

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instruction used two machine cycles or 24 oscillator cycles. Therefore, they required the same amount of
time. In the DS87C550, the MOVX instruction takes as little as two machine cycles or eight oscillator
cycles, but the “MOV direct, direct” uses three machine cycles or 12 oscillator cycles. While both are
faster than their original counterparts, they now have different execution times. This is because the
DS87C550 usually uses one instruction cycle for each instruction byte. Examine the timing of each
instruction for familiarity with the changes. Note that a machine cycle now requires just 4 clocks, and
provides one ALE pulse per cycle. Many instructions require only one cycle, but some require five. In the
original architecture, all were one or two cycles except for MUL and DIV. Refer to the High Speed Micro
User’s Guide for details and individual instruction timing.

SPECIAL FUNCTION REGISTERS

Special Function Registers (SFRs) control most special features of the DS87C550. This allows the
DS87C550 to have many new features but use the same instruction set as the 8051. When writing
software to use a new feature, an equate statement defines the SFR to an assembler or compiler. This is
the only change needed to access the new function. The DS87C550 duplicates the SFRs contained in the
standard 80C52. Table 2 shows the register addresses and bit locations. Many are standard 80C52
registers. The High Speed Micro User’s Guide describes all SFRs in full detail.

SPECIAL FUNCTION REGISTER LOCATION: Table 2

REGISTER BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 ADDRESS

PORT0 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 80h

SP 81h
DPL 82h
DPH 83h

DPL1 84h

DPH1 85h

DPS ID1 ID0 TSL - - - - SEL 86h

PCON SMOD_0 SMOD0 OFDF OFDE GF1 GF0 STOP IDLE 87h
TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 88h

TMOD GATE

C/T

M1 M0 GATE

C/T

M1 M0 89h
TL0 8Ah
TL1 8Bh

TH0 8Ch
TH1 8Dh

CKCON WD1 WD0 T2M T1M T0M MD2 MD1 MD0 8Eh

PORT1 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 90h

RCON - - - - CKRDY RGMD RGSL BGS 91h

SCON0

SM0/FE_0

SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 98h

SBUF0 99h

PMR CD1 CD0 SWB CTM

4X/2X

ALEOFF DEM1 DME0 9Fh

PORT2 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 A0h
SADDR0 A1h
SADDR1 A2h

IE EA EAD ES1 ES0 ET1 EX1 ET0 EX0 A8h
CMPL0 A9h
CMPL1 AAh
CMPL2 ABh

CPTL0 ACh
CPTL1 ADh
CPTL2 AEh
CPTL3 AFh
PORT3 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 B0h

ADCON1

STRT/BSY

EOC CONT/SS ADEX WCQ WCM ADON WCIO B2h

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SPECIAL FUNCTION REGISTER LOCATION: Table 2 cont’d

REGISTER BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 ADDRESS

ADCON2 OUTCF MUX2 MUX1 MUX0 APS3 APS2 APS1 APS0 B3h

ADMSB B4h

ADLSB B5h

WINHI B6h

WINLO B7h

IP - PAD PS1 PS0 PT1 PX1 PT0 PX0 B8h

SADEN0 B9h
SADEN1 BAh

T2CON TF2 EXF2 RCLK TCLK EXEN2 TR2

C/T2

RL2

BEh

T2MOD - - - - - - T2OE DCEN BFh

PORT4 CMT1 CMT0 CMSR5 CMSR4 CMSR3 CMSR2 CMSR1 CMSR0 C0h

ROMSIZE

- - - - - RMS2 RMS1 RMS0 C2h

PORT5 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 C4h

STATUS PIP HIP LIP - SPTA1 SPRA1 SPTA0 SPRA0 C5h

TA C7h

T2IR - CM2F CM1F CM0F IE5/CF3 IE4/CF2 IE3/CF1 IE2/CF0 C8h
CMPH0 C9h
CMPH1 CAh
CMPH2 CBh

CPTH0 CCh
CPTH1 CDh
CPTH2 CEh
CPTH3 CFh

PSW CY AC F0 RS1 RS0 OV F1 P D0h

PW0FG D2h
PW1FG D3h
PW2FG D4h
PW3FG D5h

PWMADR

ADRS - - - - - PWE1 PWE0 D6h

SCON1

SM0/FE_1

SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1 D8h

SBUF1 D9h

PWM0 DCh
PWM1 DDh
PWM2 DEh
PWM3 DFh

ACC E0h

PW01CS PW0S2 PW0S1 PW0S0 PW0EN PW1S2 PW1S1 PW1S0 PW1EN E1h
PW23CS PW2S2 PW2S1 PW2S0 PW2EN PW3S2 PW3S1 PW3S0 PW3EN E2h

PW01CON

PW0F PW0DC PW0OE PW0T/C PW1F PW1DC PW1OE PW1T/C E3h

PW23CON

PW2F PW2DC PW2OE PW2T/C PW3F PW3DC PW3OE PW3T/C E4h

RLOADL E6h

RLOADH

E7h

EIE ET2 ECM2 ECM1 ECM0 EX5/EC3 EX4/EC2 EX3/EX1

EX2/EC0

E8h

T2SEL TF2S TF2BS - TF2B - - T2P1 T2P0 EAh

CTCON

CT3

CT3

CT2

CT2

CT1

CT1

CT0

CT0 EBh

TL2 ECh

TH2 EDh
SETR TGFF1 TGFF0 CMS5 CMS4 CMS3 CMS2 CMS1 CMS0 EEh
RSTR CMTE1 CMTE0 CMR5 CMR4 CMR3 CMR2 CMR1 CMR0 EFh

B F0h

PORT6 STADC - PWMC1 PWMC0 PWMO3 PWMO2 PWMO1 PWMO0 F1h

EIP PT2 PCM2 PCM1 PCM0 PX5/PC3 PX4/PC2 PX3/PC1

PX2/PC0

F8h

WDCON SMOD_1 POR EPFI PFI WDIF WTRF EWT RWT FFh

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MEMORY RESOURCES

As is convention within the 8051 architecture, the DS87C550 uses three memory areas. The total memory
configuration of the DS87C550 is 8 kbytes of EPROM, 1 kbyte of data SRAM and 256 bytes of
scratchpad or direct RAM. The 1 kbyte of data space SRAM is read/write accessible and is memory
mapped. This on-chip SRAM is reached by the MOVX instruction. It is not used for executable
memory. The scratchpad area is 256 bytes of register mapped RAM and is identical to the RAM found on
the 80C52. There is no conflict or overlap among the 256 bytes and the 1k as they use different
addressing modes and separate instructions.

OPERATIONAL CONSIDERATION

The erasure window of the windowed CLCC package should be covered without regard to the
programmed/unprogrammed state of the EPROM. Otherwise, the device may not meet the AC and DC
parameters listed in the datasheet.

PROGRAM MEMORY

On-chip ROM begins at address 0000h and is contiguous through 1FFFh (8k). Exceeding the maximum
address of on-chip ROM will cause the DS87C550 to access off-chip memory. However, the maximum
on-chip decoded address is selectable by software using the ROMSIZE feature. Software can cause the
DS87C550 to behave like a device with less on-chip memory. This is beneficial when overlapping
external memory, such as Flash, is used.

With the ROMSIZE feature the maximum on-chip memory size is dynamically variable. Thus a portion
of on-chip memory can be removed from the memory map to access off-chip memory, then restored to
access on-chip memory. In fact, all of the on-chip memory can be removed from the memory map,
allowing the full 64k memory space to be addressed as off-chip memory. ROM addresses that are larger
than the selected maximum are automatically fetched from outside the part via Ports 0 & 2. A depiction
of the ROM memory map is shown in Figure 2.

The ROMSIZE register is used to select the maximum on-chip decoded address for ROM. Bits RMS2,
RMS1, RMS0 (ROMSIZE2:0) have the following effect.

Maximum on-chip

RMS2 RMS1 RMS0 ROM Address

0 0 0 0k
0 0 1 1k (0h - 03FFh)
0 1 0 2k (0h - 07FFh)
0 1 1 4k (0h - 0FFFh)

1 0 0 8k (0h – 1FFFh) default

1 0 1 invalid - reserved
1 1 0 invalid - reserved
1 1 1 invalid - reserved

The reset default condition is a maximum on-chip ROM address of 8 kbytes. Thus no action is required if
this feature is not used. Therefore when accessing external program memory, the first 8 kbytes would be
inaccessible. To select a smaller effective ROM size, software must alter bits RMS2-RMS0. Altering
these bits requires a Timed Access procedure as explained below. The ROMSIZE register should be
manipulated from a safe area in the program memory map. This is a program memory address that will
not be affected by the change. For example, do not select a maximum ROM size of 4k from an internal
ROM address of 5k. This would cause the current address to switch from internal to external and
potentially cause invalid operation. Similarly, do not instantly switch from external to internal memory.

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For example, do not select a maximum ROM address of 8k from an external ROM address of 7k (if
ROMSIZE is set for 4k or less).

Off-chip memory is accessed using the multiplexed address/data bus on P0 and the MSB address on P2.
While serving as a memory bus, these pins are not available as I/O ports. This convention follows the
standard 8051 method of expanding on-chip memory. Off-chip ROM access also occurs if the EA pin is
logic 0. EA overrides all bit settings. The PSEN signal will go active (low) to serve as a chip enable or
output enable when Ports 0 & 2 fetch from external ROM.

ROM MEMORY MAP Figure 2

DATA MEMORY

Unlike many 8051 derivatives, the DS87C550 contains additional on-chip data memory. In addition to
the standard 256 bytes of data RAM accessed by direct instructions, the DS87C550 contains another 1
kbyte of data memory that is accessed using the MOVX instruction. Although physically on-chip,
software treats this area as though it was located off-chip. The 1 kbyte of SRAM is permanently located
from address 0000h to 03FFh (when enabled).

Access to the on-chip data RAM is optional under software control. When enabled by software, the data
SRAM is between 0000h and 03FFh. Any MOVX instruction that uses this area will go to the on-chip
RAM while enabled. MOVX addresses greater than 1k automatically go to external memory through
Ports 0 & 2.

When disabled, the 1k memory area is transparent to the system memory map. Any MOVX directed to
the space between 0000h and FFFFh goes to the expanded bus on Ports 0 & 2. This also is the default
condition. This default allows the DS87C550 to drop into an existing system that uses these addresses for
other hardware and still have full compatibility.

The on-chip data area is software selectable using two bits in the Power Management Register (DME1,
DME0). This selection is dynamically programmable. Thus access to the on-chip area becomes
transparent to reach off-chip devices at the same addresses. These bits have the following operation:

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DATA MEMORY ACCESS CONTROL Table 3

DME1 DME0 DATA MEMORY ADDRESS MEMORY FUNCTION

0 0 0000h - FFFFh External Data Memory *Default condition
0 1 0000h - 03FFh

0400h - FFFFh

Internal SRAM Data Memory

External Data Memory
1 0 Reserved Reserved
1 1 0000h - 03FFh

0400h – FFFBh

FFFCh

FFFDh - FFFFh

Internal SRAM Data Memory

Reserved - no external access

Read access to the status of lock bits

Reserved

Notes on the status byte read at FFFCh with DME1, 0 = 1, 1: bits 2-0 reflect the programmed status of the
security lock bits LB2-LB0. They are individually set to a logic 1 to correspond to a security lock bit that
has been programmed. These status bits allow software to verify that the part has been locked before
running if desired. The bits are read only.

STRETCH MEMORY CYCLE

The DS87C550 allows software to adjust the speed of off-chip data memory and/or peripheral access by
adjusting the number of machine cycles it takes to execute a MOVX instruction. The micro is capable of
performing the MOVX in as little as two machine cycles. The on-chip SRAM uses this speed and any
MOVX instruction directed internally always uses two cycles. However, the time for the instruction
execution can be stretched for slower interface to external devices. This allows access to both fast
memory and slow memory or peripherals with no glue logic. Even in high-speed systems, it may not be
necessary or desirable to perform off-chip data memory access at full speed. In addition, there are a
variety of memory mapped peripherals such as LCDs or UARTs that are slow and require more time to
access.

The Stretch MOVX function is controlled by the MD2-MD0 SFR bits in the Clock Control Register
(CKCON.2-0) as described below. They allow the user to select a Stretch value between 0 and 7. A
Stretch of 0 will result in a two-machine cycle MOVX instruction. A Stretch of 7 will result in a MOVX
of 12 machine cycles. Software can dynamically change the stretch value depending on the particular
memory or peripheral being accessed. The default stretch of one allows the use of commonly available
SRAMs without dramatically lengthening the memory access times.

Note that the STRETCH MOVX function is slightly different in the DS87C550 than in earlier members
of the high-speed microcontroller family. In all members of this family (including the DS87C550),
increasing the stretch value from 0 to 1 causes setup and hold times to be increased by 1 crystal clock
each. In older members of the family, there is no further change in setup and hold times regardless of the
number of stretch cycles selected. In the DS87C550 however, when a stretch value of 4 or above is
selected, the timing of the interface changes dramatically to allow for very slow peripherals. First, the
ALE signal is increased by 1 machine cycle. This increases the address setup time into the peripheral by
this amount. Next, the address is held on the bus for one additional machine cycle, increasing the address
hold time by this amount. The Read or Write signal is then increased by a machine cycle. Finally, the data
is held on the bus (for a write cycle) one additional machine cycle, thereby increasing the data hold time
by this amount. For every Stretch value greater than 4, the setup and hold times remain constant, and only
the width of the read or write signal is increased.

On reset, the Stretch value will default to a 1, resulting in a three-cycle MOVX for any external access.
Therefore, the default off-chip RAM access is not at full speed. This is a convenience to existing designs
that may not have fast RAM in place. Internal SRAM access is always at full speed regardless of the

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Stretch setting. When maximum speed is desired, software should select a Stretch value of 0. When using
very slow RAM or peripherals, the application software can select a larger Stretch value. Note that this
affects data memory accesses only and that there is no way to slow the accesses to program memory other
than to use a slower crystal (or external clock).

The specific timing of the variable speed Stretch MOVX is provided in the Electrical Specifications
section of this data sheet. Table 4 shows the resulting MOVX instruction timing and the read or write
strobe widths for each Stretch value.

DATA MEMORY CYCLE STRETCH VALUES Table 4

CKCON.2-0 MOVX MACHINE

RD

OR

WR

STROBE WIDTH

M2 M1 M0 CYCLES IN MACHINE CYCLES

0 0 0 2 (forced internal) 0.5
0 0 1 3 (default external) 1
0 1 0 4 2
0 1 1 5 3
1 0 0 9 4
1 0 1 10 5
1 1 0 11 6
1 1 1 12 7

Dual Data Pointer With Inc/Dec

The DS87C550 contains several new, unique features that are associated with the Data Pointer register. In
the original 8051 architecture, the DPTR was a 16-bit value that was used to address off-chip data RAM
or peripherals. To improve the efficiency of data moves, the DS87C550 contains two Data Pointer
registers (DPTR0 and DPTR1). By loading one DPTR with the source address and the other with the
destination address, block data moves can be made much more efficient. Since DPTR0 is located at the
same address as the single DPTR in the original 8051 architecture, code written for the original
architecture will operate normally on the DS87C550 with no modification necessary.

The second data pointer, DPTR1 is located at the next two register locations (up from DPTR0) and is
selected using the data pointer select bit SEL (DPS.0). If SEL = 0, then DPTR0 is the active data pointer.
Conversely, if SEL = 1, then DPTR1 is the active data pointer. Any instruction that reference the DPTR
(ex. MOVX A, @ DPTR) refers to the active data pointer as determined by the SEL bit. Since the bit
adjacent to SEL in the DPS register is not used, the fastest means of changing the SEL (and thereby
changing the active data pointer) is with an INC instruction. Each INC DPS Instruction will toggle the
active data pointer.

Unlike the standard 8051, the DS87C550 has the ability to decrement as well as increment the data
pointers without additional instructions. When the INC DPTR instruction is executed, the active DPTR is
incremented or decremented according to the ID1, ID0 (DPS.7-6), and SEL (DPS.0) bits as shown. The
inactive DPTR is not affected.

ID1 ID0 SEL RESULT OF INC DPTR

X 0 0 INCREMENT DPTR0
X 1 0 DECREMENT DPTR0

0 X 1 INCREMENT DPTR1
1 X 1 DECREMENT DPTR1

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Another useful feature of the device is its ability to automatically switch the active data pointer after a
DPTR-based instruction is executed. This feature can greatly reduce the software overhead associated
with data memory block moves, which toggle between the source and destination registers. When the
Toggle Select bit (TSL;DPS.5) is set to 1, the SEL bit (DPS.0) is automatically toggled every time one of
the following DPTR related instructions are executed:

§ INC DPTR

§ MOV DPTR, #data16

§ MOVC A, @A+DPTR

§ MOVX A, @DPTR

§ MOVX @DPTR, A

As a brief example, if TSL is set to 1, then both data pointers can be updated with the two instruction
series shown.

INC DPTR
INC DPTR

With TSL set, the first increment instruction increments the active data pointer, and then causes the SEL
bit to toggle making the other DPTR active. The second increment instruction increments the newly
active data pointer and then toggles SEL to make the original data pointer active again.

CLOCK CONTROL and POWER MANAGEMENT

The DS87C550 includes a number of unique features that allow flexibility in selecting system clock
sources and operating frequencies. To support the use of inexpensive crystals while allowing full-speed
operation, a clock multiplier is included in the processor’s clock circuit. Also, along with the Idle and
power-down (Stop) modes of the standard 80C52, the DS87C550 provides a new Power Management
mode. This mode allows the processor to continue instruction execution at a very low speed to
significantly reduce power consumption (below even idle mode). The DS87C550 also features several
enhancements to Stop mode that make this extremely low power mode more useful. Each of these
features is discussed in detail below.

SYSTEM CLOCK CONTROL

As mentioned previously, the DS87C550 contains special clock control circuitry that simultaneously
provides maximum timing flexibility and maximum availability and economy in crystal selection. There
are two basic functions to this circuitry: a frequency multiplier and a clock divider. By including a
frequency multiplier circuit, full-speed operation of the processor may be achieved with a lower
frequency crystal. This allows the user the ability to choose a more cost-effective and easily obtainable
crystal than would be possible otherwise.

The logical operation of the system clock divide control function is shown in Figure 3. The clock signal
from the crystal oscillator (or external clock source) is provided to the frequency multiplier module, to a
divide-by-256 module, and to a 3-to-1 multiplexer. The output of this multiplexer is considered the
system clock. The system clock provides the time base for timers and internal peripherals, and feeds the
CPU State Clock Generation circuitry. This circuitry divides the system clock by 4, and it is the four
phases of this clock that make up the instruction execution clock. The four phases of a single instruction
execution clock are also called a single machine cycle clock. Instructions in the DS87C550 all use the
machine cycle as the fundamental unit of measure and are executed in from one to five of these machine
cycles. It is important to note the distinction between the system clock and the machine cycle clock as
they are often confused, creating errors in timing calculations. In performing timing calculations, it is

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important to remember that all timers and internal peripherals operate off of some version of the system
clock while the instruction execution engine always operates off of the machine cycle clock.

When CD1 and CD0 (PMR.7-6) are both cleared to a logic 0, the multiplexer selects the frequency
multiplier output. The frequency multiplier can supply a clock that is 2 times or 4 times the frequency of
the incoming signal. If the times-4 multiplier is selected by setting the 4X/

2X

bit (PMR.3) to 1, for
example, the incoming signal is multiplied by 4. This 4X clock is then passed through the multiplexer,
and then output to the CPU State Clock Generation circuits. These CPU State Clock Generation circuits
always divide the incoming clock by 4 to arrive at the four states (called a machine cycle) necessary for
correct processor operation. In this example, since the clock multiplier multiplies by four and the CPU
State Clock Generation circuit divides by 4, the apparent instruction execution speed is 1 external (or
crystal oscillator) clock per instruction. If the 4X/2X bit is set to 0, then the apparent instruction
execution speed is 2 clocks per instruction.

It is important to note that the clock multiplier function does not increase the maximum clock (system
clock) rate of the device. The DS87C550 operates at a maximum system clock rate of 33 MHz. Therefore,
the maximum crystal frequency is 8.25 MHz when a clock multiplier of 4 is used, and is 16.5 MHz when
a clock multiplier of 2 is used. The purpose of the clock multiplier is to simplify crystal selection when
maximum processor operation is desired. Specifically, an 8.25 MHz fundamental mode, AT cut, parallel
resonant crystal is much easier to obtain than the same crystal at 33 MHz. Most crystals in that frequency
range tend to be third overtone type.

As illustrated in Figure 3, the programmable Clock Divide control bits CD1-CD0 (PMR.7-6) provide the
processor with the ability to adapt to different crystal (and external clock) frequencies and also to allow
extreme division of the incoming clock providing lower power operation when desired. The effect of
these bits is shown in Table 5.

CD1:CD0 OPERATION Table 5

CD1 CD0 Instruction Execution

0 0 Frequency multiplier (1 or 2 clocks per machine cycle)
0 1 Reserved

1 0

Clock divided by 4 (4 clocks per machine cycle) Default

1 1 Clock divided by 1024 (1024 clocks per machine cycle)

Besides the ability to use a multiplied clock signal, the normal mode of operation, i.e. the reset default
condition (CD1 = 1, CD0 = 0) passes the incoming crystal or external oscillator clock signal straight
through as the system clock. Because of the CPU State Clock generation circuitry’s normal divide-by-4
function, the default execution speed of the DS87C550’s basic instruction is one-fourth the clock
frequency.

The selection of instruction cycle rate takes effect after a delay of one machine cycle. Note that the clock
divider choice applies to all functions including timers. Since baud rates are altered, it may be difficult to
conduct serial communication while in divide-by-1024 mode. This is simplified by the use of switchback
mode (described later) included on the DS87C550.