Dallas Semiconductor DS80CH11-E02 Datasheet

DS80CH11

System Energy Manager

DS80CH11

011200 1/88

PRODUCT SPECIFICATION

V2.1

DS80CH11

011200 2/88

1.0 GENERAL DESCRIPTION 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 OVERVIEW 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 DETAILED FEATURE SUMMARY 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 CONVENTIONS 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 ADDITIONAL REFERENCES 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.0 PIN DESCRIPTION 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 PIN FUNCTION SUMMARY 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 PIN CHARACTERISTICS 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.0 CORE MICROCONTROLLER 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 CORE MICRO OVERVIEW 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 INSTRUCTION SET SUMMARY 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 SPEED IMPROVEMENT 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4 INSTRUCTION SET ADDITIONAL REFERENCES 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5 RESET 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6 INTERRUPT CONTROL 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.0 MEMORY RESOURCES 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1 OVERVIEW 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2 DATA MEMORY ACCESS 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.1 Stretch Memory Cycle 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.2 Dual Data Pointer 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3 EXTERNAL MEMORY INTERFACE 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4 DIRECT (SCRATCHPAD) RAM ACCESS 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5 SPECIAL FUNCTION REGISTERS 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.0 CORE I/O RESOURCES 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1 PROGRAMMABLE TIMERS 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2 SERIAL PORTS 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3 WATCHDOG TIMER 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4 PARALLEL I/O PORTS 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4.1 Alternate Pin Function Summary 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.0 2–Wire SERIAL INTERFACE 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1 INTRODUCTION 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2 REGISTER DESCRIPTION 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2.1 2WFSx – 2–Wire Frequency Select Registers 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2.2 2WDATx – 2–Wire Data I/O Registers 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2.3 2WSADRx – 2–Wire Slave Address Registers 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2.4 2WCONx – 2–Wire Control Registers 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2.5 2WSTAT1x – 2–Wire Status Register 1 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2.6 2WSTAT2x – 2–Wire Status Register 2 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3 OPERATION DESCRIPTION 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3.1 Master Transmit 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3.2 Master Receive 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3.3 Slave Receive 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TABLE OF CONTENTS

DS80CH11

011200 3/88

6.3.4 Slave Transmit 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3.5 Bus Monitor Mode Operation 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.0 A/D CONVERTER 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1 OVERVIEW 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2 ANALOG POWER / SLEEP MODE 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.3 REFERENCE OPTION 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.4 SAR A/D CONVERTER 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.5 CONVERSION TIME 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.6 WINDOW COMPARATOR 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.7 A/D OPERATION 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.8 A/D SPECIAL FUNCTION REGISTERS 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.8.1 ADCON1 – A/D Control Register 1 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.8.2 ADCON2 – A/D Control Register 2 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.8.3 ADMSB – A/D Result Most Significant Byte 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.8.4 ADLSB – A/D Result Least Significant Byte 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.8.5 WINHI – A/D Window Comparator High Byte 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.8.6 WINLO – A/D Window Comparator Low Byte 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.0 ACTIVITY MONITOR/LED CONTROL 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.1 OVERVIEW 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.2 ACTIVITY MONITOR INPUT OPERA TION 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.3 AME – ACTIVITY MONITOR ENABLE REGISTER 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.4 AMQ – ACTIVITY MONITOR QUALIFIER REGISTER 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.5 AMP – ACTIVITY MONITOR POLARITY REGISTER 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.6 AMF – ACTIVITY MONITOR FLAG REGISTER 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.7 LED CONTROL 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.0 HOST INTERFACE PORTS 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.1 OVERVIEW 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.2 REGISTER MAPPING 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.3 KBDIN / PMDIN – DATA REGISTERS 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.4 KBSTAT / PMSTAT – STATUS REGISTERS 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.5 KBDOUT / PMDOUT – OUTPUT DATA REGISTERS 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.0 KEYBOARD SCANNING PORTS 59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.1 OVERVIEW 59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.2 KEY SCAN OUTPUTS 59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.3 KEY SCAN INPUTS 59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.4 KDE – KEY DETECT ENABLE REGISTER 59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.5 KDF – KEYBOARD DETECT FLAG REGISTER 59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.0 PULSE WIDTH MODULAT ORS 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.1 FUNCTION OVERVIEW 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.2 PRESCALER 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.3 PWM CLOCK GENERATORS 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.4 PWM PULSE GENERAT ORS 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.5 PWM SPECIAL FUNCTION REGISTERS 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.5.1 PW01CS / PW23CS – PWM 0, 1 / PWM 2, 3 Clock Select Registers 62. . . . . . . . . . . . . .

11.5.2 PW01CON / PW23CON – PWM 0, 1 / PWM 2, 3 Control Register 63. . . . . . . . . . . . . . . .

11.5.3 PWnFG – PWM n Frequency Generator Registers 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.5.4 PWMn – PWM n Value Registers 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.0 MICROCONTROLLER POWER MANAGEMENT 66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.1 POWER–DOWN / POWER–UP OPERATION 66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DS80CH11

011200 4/88

12.1.1 Microcontroller Power Fail Reset 66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.2 LOW POWER OPERATING MODES 66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.2.1 Slow Clock Mode 66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.2.1.1 Crystaless Slow Clock Mode 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.2.1.2 Slow Clock Mode Operation 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.2.1.3 Clock Divider 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.2.1.4 Switchback 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.2.1.5 Status 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.2.1.6 Crystal / Ring Operation 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.2.2 Idle Mode 71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.2.3 Stop Mode and Enhancements 71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.0 +5.0V ELECTRICAL SPECIFICATIONS 74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.1 ABSOLUTE MAXIMUM RATINGS* 74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.2 MICROCONTROLLER DC ELECTRICAL CHARACTERISTICS 74. . . . . . . . . . . . . . . . . . . . . . . . . .

13.3 MICROCONTROLLER AC ELECTRICAL CHARACTERISTICS 76. . . . . . . . . . . . . . . . . . . . . . . . . .

13.3.1 External Program Memory Characteristics 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.3.2 MOVX Using Stretch Memory Cycles 77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.3.3 External Clock Characteristics 78. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.3.4 Serial Port Mode 0 Timing Characteristics 78. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.3.5 Power Cycle Timing Characteristics 79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.4 SYSTEM INTERFACE DC ELECTRICAL CHARACTERISTICS 83. . . . . . . . . . . . . . . . . . . . . . . . . .

13.5 HOST I/F AC TIMING CHARACTERISTICS 84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.6 2–Wire AC TIMING CHARACTERISTICS 86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.7 A/D CONVERTER SPECIFICATIONS 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.7.1 Absolute Maximum Ratings 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.7.2 A/D Electrical Characteristics 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DS80CH11

011200 5/88

1.0 GENERAL DESCRIPTION

1.1 OVERVIEW

The System Energy Manager is a highly integrated
microcontroller that provides several key features for
systems including key scanning and control, battery
and power management, as well as two 2–Wire serial
I/O Ports. It incorporates the Dallas 8051–compatible
high–speed microcontroller core which has been rede­signed to eliminate wasted clock and memory cycles.
Every standard 8051 instruction is executed between

1.5 and 3 times faster than the original for the same
crystal speed. Looking at it another way, the high–
speed core achieves the same throughput as a stan­dard 8051 while using much less power as a result of
fewer required clock cycles. As a result, the firmware
can easily support many tasks required by mobile sys­tems within a single component.

The controller is designed to off–load battery and power
management tasks from the host CPU and thereby
make possible an efficient solution for systems. In addi­tion to the microcontroller core, it incorporates an
8–channel, 10–bit A/D converter with external refer­ence so that its firmware can perform battery manage­ment tasks without burdening the host CPU. A four–

channel 8–bit pulse–width modulator allows digital
control of functions such as LCD contrast and bright­ness. An 8–bit port is provided for key scan inputs. A
total of 88 parallel I/O pins are available for key scan­ning, system configuration, and power management
control.

The System Energy Manager scans a key matrix and
interfaces to the host CPU via an 8042–compatible port.
The benefits of sophisticated power management and
permanently powered functions are thereby attained
without adding to the system’s chip count.

Two 2–wire, bi–directional serial buses are incorpo­rated to facilitate the management of slave peripheral
devices on the motherboard, such as digital tempera­ture sensors and potentiometers, and to support exter­nal low–speed I/O devices such as monitor configura­tion channels, pen tablets, and joysticks.

Because a direct interface to the X–bus is provided, the
controller is not dependent on a particular core logic
chip or chip set. Independent chip select inputs for the
keyboard controller, power management #1, and power
management #2 registers are provided.

DS80CH11

011200 6/88

CONTROLLER BLOCK DIAGRAM Figure 1–1

VCC

P7.7 /
AMI.7 /
LED.7

uC

CLK OSC.

VPFW

VRST

GND

XTAL1 XTAL2

PORT 7 /

ACT. MONITOR /

LED CONTROL

P7.0 /
AMI.0 /
LED.0

TIMING /

BUS CONTROL

ALE

PSEN

RST

P3.7 / RD

PORT 3

P3.6 / WR

P3.5 / T1

P3.4 / T0
P3.3 / INT1
P3.2 / INT0

P3.1 / TXD0
P3.0 / RXD0

P1.7

PORT 1

P1.6

P1.3 / SDA1
P1.2 / SCL1
P1.1 / T2EX

P1.0 / T2

P6.7 / SOC

PORT 6 /

P6.6
P6.5 / PWI.1
P6.4 / PWI.0

P6.3 / PWO.3

P6.2 / PWO.2

P6.1 / PWO.1
P6.0 / PWO.0

PWM I/O

P1.5 / SDA2

P1.4 / SCL2

PORT 0

PORT 2

PORT 4 /

KEYBOARD

IN

PORT 8/

KEYBOARD

OUT

P0.7 /

AD7

P0.0 /

AD0

P2.7 /

A15

P2.0 /A8P4.7 /

KSI.7

P4.0 /
KSI.0

P8.7/

KS0.7

P8.0/

KS0.0

P9.7/

KS0.15

P9.0/

KS0.8

PORT 5 /

10–BIT ADC

P5.0 / AI.0

P5.7 / AI.7

AGND

AVCC

VRL

VRH

PM1C

PC I/F

uC I/F

KBC

PC I/F

uC I/F

KBC

OUTPUT

STATUS

KBC

INPUT

SD7–SD0

IOW

IOR

A0

KBCS

KBOBF

SMI1

PM1CS

4 MHz

RING OSC.

SYS. CLOCK

CONTROL

WATCHDOG

TIMER

TIMER 2
TIMER 1
TIMER 0

INT 1
INT 0

8051

UART

ACC. BUS

SIO2

ACC. BUS

SIO1

SCRATCHPAD

REGISTERS
(256 BYTES)

POWER MON./

CONTROL

HVCC

HGND

SPECIAL

HIGH SPEED

256 x 8

FUNCTION

REGISTERS

80C520

CPU CORE

DATA

RAM

POWER

CONTROL

3

3

PORT 9/

KEYBOARD

OUT

P10.7

PORT 10

P10.0

PM1C

PM1C

PM2C

PC I/F

uC I/F

PM2C

PM2C

STATUS

OUTPUT

INPUT

PM2CS

SMI2

STATUS

OUTPUT

INPUT

DS80CH11

011200 7/88

1.2 DETAILED FEATURE SUMMARY

• High Speed 80C32 Compatible Core:

– High performance 4 clocks / machine cycle

(8032 = 12)

– Low Power: typically 1/3 power for equivalent

8032 throughput
– Maximum clock speed up to 25 MHz at 5.0V
– Ultra–low stop mode power (typ. 1 uA) and

“IDLE” mode (typ. 10 mA)
– Multiple wake–up sources from STOP including

key scan, 2–wire, host I/F, or external interrupt
– Three 16–bit timers, 1 serial port
– 256 byte scratchpad
– 256 bytes MOVX RAM

• Keyboard Control:

– Replaces 8042 and key scan microcontroller
– 2 Parallel I/O ports for key scan outputs
– One interrupt–driven 8–bit input port to initiate

key–scan sequence

• Input/Output:

– Total of eleven 8–bit I/O ports; all pins can be

individually programmed to serve as general

purpose digital input/output.
– Each 8–bit port supports one or more special

functions:

Port 0, 2, 3: External program / data memory

interface

Port 1, 3: UART, 2–Wire serial, timers, and

external interrupt I/O.

Port 4, 8, 9: Key scan input / output
Port 5: A/D inputs
Port 6: PWM Outputs
Port 7: Activity monitor, LED Control
Port 10: GPIO

• Analog Input/Output:

– Eight–channel, 10–bit A/D with power down

mode supports charging NiMH rechargeable

cells

– 4–channel, 8–bit PWM supports LCD brightness

and contrast control

• 2–Wire Bi–directional Serial Buses

– Master/slave multi–drop operation
– Manages on–board slaves or external I/O

devices

• Power Control

– Generates system power on reset
– Programmable power down pin states

1.3 CONVENTIONS

The following conventions are used throughout this
specification:

• “SEM” is the short form name used to indicate the

System Energy Manager.

• Signals that are active low are followed by a pound

symbol (#) or backslash (\), or are indicated with an
overbar.

• If a range of signals is described, such as SA0 through

SA10, the range is given as SA10–0, with the most–
significant digit first and the least–significant digit last,
separated by a hyphen.

• Numbers written in this specification can be written as

decimal, hexadecimal, or binary . Hexadecimal num­bers are followed by an “H” suffix. Binary numbers are
followed by a “B” suffix. For example, decimal
27 = 1BH = 00011011B.

1.4 ADDITIONAL REFERENCES

The SEM incorporates the Dallas 8051 compatible High
Speed Micro core including the CPU and many of its
core peripherals. The operational details of these ele­ments are contained in the Dallas High Speed Micro
User’s Guide.

DS80CH11

011200 8/88

2.0 PIN DESCRIPTION

128–TQFP PIN ASSIGNMENT Figure 2–1

VRST
VPFW
P3.5 / T1
P3.4 / T0
P3.3 / INT1
P3.2 / INT0
P3.1 / TXD0
P3.0 / RXD0
P1.7
P1.6
P1.5 / SDA2
P1.4 / SCL2
P1.3 / SDA1
P1.2 / SCL1
P1.1 / T2EX
P1.0 / T2
GND
VCC
P4.7 / KSI.7
P4.6 / KSI.6
P4.5 / KSI.5
P4.4 / KSI.4
P4.3 / KSI.3
P4.2 / KSI.2
P4.1 / KSI.1
P4.0 / KSI.0
P7.7 / AMI.7 / LED.7
P7.6 / AMI.6 / LED.6
P7.5 / AMI.5 / LED.5
P7.4 / AMI.4 / LED.4
P7.3 / AMI.3 / LED.3
P7.2 / AMI.2 / LED.2
P7.1 / AMI.1 / LED.1
P7.0 / AMI.0 / LED.0
HVCC
P10.7
P10.6
P10.5

P9.7 / KSO.15
P9.6 / KSO.14
P9.5 / KSO.13
P9.4 / KSO.12

P9.3 / KSO.11
P9.2 / KSO.10

P9.1 / KSO.9
P9.0 / KSO.8
P8.7 / KSO.7
P8.6 / KSO.6
P8.5 / KSO.5
P8.4 / KSO.4
P8.3 / KSO.3
P8.2 / KSO.2
P8.1 / KSO.1
P8.0 / KSO.0

GND
VCC

P6.7 / SOC

P6.6
P6.5 / PWI.1
P6.4 / PWI.0

P6.3 / PWO.3
P6.2 / PWO.2

P6.1 / PWO.1
P6.0 / PWO.0

P5.7 / AI.7
P5.6 / AI.6
P5.5 / AI.5
P5.4 / AI.4
P5.3 / AI.3
P5.2 / AI.2
P5.1 / AI.1
P5.0 / AI.0

GND

A0

IOW

IOR

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87

86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65

SMI1

KBOBF

PM1CS

KBCS

AGND

VRH

VRL

AVCC

HGND

SD7

SD6

SD5

SD4

SD3

SD2

SD1

SD0

NC

NC

SMI2

PM2CS

P10.0

P10.1

P10.2

P10.3

P10.4

NC

PSEN

ALE

P0.7 / AD7

P0.6 / AD6

P0.5 / AD5

P0.4 / AD4

P0.3 / AD3

P0.2 / AD2

P0.1 / AD1

P0.0 / AD0

VCC

XTAL2

XTAL1

GND

P2.7 / A15

P2.6 / A14

P2.5 / A13

P2.4 / A12

P2.3 / A1 1

P2.2 / A10

P2.1 / A9

P2.0 / A8

RST

P3.7 / RD

P3.6 / WR

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

39404142434445464748495051525354555657585960616263

64

DS80CH11

011200 9/88

2.1 PIN FUNCTION SUMMARY

PIN SYMBOL DESCRIPTION

36 A0 Command / Data Select: Input. Address input used by the host processor in data

transfers to the keyboard controller and power management #1 and #2 interface ports to
indicate whether the transfer is command (A0=1) or data (A0=0).

43 AGND Analog Ground.

106 ALE Address Latch Enable: Output. This signal functions as a clock to latch the external

address LSB from the multiplexed address/data bus on Port 0. This signal is commonly
connected to the latch enable of an external 373 family transparent latch. ALE has a
pulse width of 1.5 XTAL1 cycles and a period of 4 XTAL1 cycles. ALE is forced high

when the SEM is in a Reset condition.
46 AVCC Analog VCC.
17

35
86

117

GND Digital circuit ground.

47 HGND Host Interface Ground:
68 HVCC Host Interface VCC:
38 IOR I/O Read: Input. I/O Read is used to signal a read operation is in effect on the host

address/data bus.
37 IOW I/O Write: Input. I/O Write is used to signal a write operation is in effect on the host

address/data bus.
42 KBCS Keyboard Chip Select: (Input, active low). This is a chip select signal used to enable

the keyboard control host interface port.
40 KBOBF Keyboard Output Buffer Full: (Output, active high). This signal is set when the key-

board control host interface data buffer contains data to be read by the host. KBOBF will

be driven low when host reads the keyboard control data buffer register .
56

57

108

NC No Connection.

121
122
123
124
125
126
127
128

P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)

Port 0 / Address/Data Outputs 7–0: I/O. Port 0 is an open–drain 8–bit bi–directional

I/O port. As an alternate function Port 0 can function as the multiplexed address/data

bus to access off–chip memory . During the time when ALE is high, the LSB of a memory

address is presented. When ALE falls to a logic 0, the port transitions to a bi–directional

data bus. This bus is used to read external ROM and read/write external RAM memory

or peripherals. When used as a memory bus, the port provides active high drivers. The

reset condition of Port 0 is tri–state. Pull–up resistors are required when using Port 0 as

an I/O port.

DS80CH11

011200 10/88

PIN SYMBOL DESCRIPTION

87
88
89
90
91
92
93
94

P1.0 (T2)

P1.1 (T2EX)

P1.2 SCL1
P1.3 SDA1
P1.4 SCL2
P1.5 SDA2

P1.6
P1.7

Port 1/ (Alternate Functions): – I/O. Port 1 provides eight lines which can be individu­ally selected as bi–directional I/O port pins or as the alternate functions listed below:

Alternate

Port

Function Description

P1.0 T2 External I/O for Timer/Counter 2
P1.1 T2EX Timer/Counter 2 Capture/Reload Trigger
P1.2 SCL1 2–Wire Serial Clock 1
P1.3 SDA1 2–Wire Serial Data 1
P1.4 SCL2 2–Wire Serial Clock 2
P1.5 SDA2 2–Wire Serial Data 2
P1.6 (None)
P1.7 (None)

Note that P1.7 – P1.2 are high–drive pins which are always open–drain and must be
used with external pull–ups when used as I/O port pins. P1.1 and P1.0 have internal
pull–up resistors.

109

110
111
112
113
114
115
116

P2.0 (A8)

P2.1 (A9)
P2.2 (A10)
P2.3 (A11)
P2.4 (A12)
P2.5 (A13)
P2.6 (A14)
P2.7 (A15)

Port 2 / Address Outputs A15–8: – I/O. Port 2 is a pseudo–bi–directional I/O port with
internal pull–up resistors. As an alternate function Port 2 can function as MSB of the
external address bus.

95
96
97
98

99
100
103
104

P3.0(RXD0)

P3.1 (TXD0)

P3.2 (INT0

)

P3.3 (INT1

)
P3.4 (T0)
P3.5 (T1)

P3.6 (WR

)

P3.7 (RD

)

Port 3 / (Alternate Functions): – I/O. Port 3 provides eight lines each of which can
serve as psuedo–bi–directional I/O port pins or as the alternate functions as listed
below. Internal pull–up resistors are always present on these pins.

Alternate

Port

Function Description

P3.0 RXD0 Serial Port 0 Input
P3.1 TXD0 Serial Port 0 Output
P3.2 INT0

External Interrupt 0

P3.3 INT1

External Interrupt 1
P3.4 T0 Timer 0 External Input
P3.5 T1 Timer 1 External Input
P3.6 WR

External Data Memory Write Strobe
P3.7 RD

External Data Memory Read Strobe

77
78
79
80
81
82
83
84

P4.0 (KSI.0)
P4.1 (KSI.1)
P4.2 (KSI.2)
P4.3 (KSI.3)
P4.4 (KSI.4)
P4.5 (KSI.5)
P4.6 (KSI.6)
P4.7 (KSI.7)

Port 4 / KSI.7–0: – I/O / Keyboard Scan Inputs. Port 4 provides eight lines which can be
individually selected as psuedo–bi–directional I/O port pins or as an interrupt Inputs for
key scanning. Port 4 pins incorporate Schmitt inputs with pull–up resistors.

DS80CH11

011200 11/88

PIN SYMBOL DESCRIPTION

34
33
32
31
30
29
28
27

P5.0 (AI.0)
P5.1 (AI.1)
P5.2 (AI.2)
P5.3 (AI.3)
P5.4 (AI.4)
P5.5 (AI.5)
P5.6 (AI.6)
P5.7 (AI.7)

Port 5 / AI.7–0: – I/O / A/D inputs. Port 5 provides eight lines which can be individually
selected as open–drain psuedo–bi–directional I/O port pins or as A/D inputs. Pull–up
resistors are required when using Port 5 as an I/O port.

26
25
24
23
22
21
20
19

P6.0 (PWO.0)
P6.1 (PWO.1)
P6.2 (PWO.2)
P6.3 (PWO.3)

P6.4 (PWI.0)
P6.5 (PWI.1)

P6.6

P6.7 / SOC

Port 6 / PW0.3 – 0: – I/O / Pulse–Width Modulated Outputs. Port 6 provides eight lines
which can all serve as psuedo–bi–directional I/O port pins with internal pull–up
resistors. Six lines can be individually selected to serve the pulse–width modulator
function indicated below:

Alternate

Port

Function Description

P6.0 PWO.0 PWM 0 output (active high drive when enabled)
P6.1 PWO.1 PWM 1 output (active high drive when enabled)
P6.2 PWO.2 PWM 2 output (active high drive when enabled)
P6.3 PWO.3 PWM 3 output (active high drive when enabled)
P6.4 PWI.0 Optional clock input for PWM channels 0 and 2
P6.5 PWI.1 Optional clock input for PWM channels 1 and 3
P6.6 (none)
P6.7 SOC External A / D start of conversion signal

69
70
71
72
73
74
75
76

P7.0 (AMI.0)

(LED.0)

P7.1 (AMI.1)

(LED.1)

P7.2 (AMI.2)

(LED.2)

P7.3 (AMI.3)

(LED.3)

P7.4 (AMI.4)

(LED.4)

P7.5 (AMI.5)

(LED.5)

P7.6 (AMI.6)

(LED.6)

P7.7 (AMI.7)

(LED.7)

Port 7 / AMI.7–0 / LED.7–0: – I/O / Activity Monitor Inputs / LED Control. Port 7 provides
eight lines which can serve as a psuedo–bi–directional I/O port pins with internal pull–
ups or as Activity Monitor inputs. When used as Activity Monitor inputs, these pins are
typically connected to the chip select line of an external peripheral device, and can be
programmed to sense active–high or active–low signals. Any pin which is programmed
as an Activity Monitor input by setting its AMEn bit to a 1 will have its pull–up device dis­abled and thereby function as an open–drain

pin in order to eliminate unnecessary cur-

rent drain. All port 7 pins are capable of controlling LED’s.

16
15
14
13
12
11
10

9

P8.0 (KSO.0)
P8.1 (KSO.1)
P8.2 (KSO.2)
P8.3 (KSO.3)
P8.4 (KSO.4)
P8.5 (KSO.5)
P8.6 (KSO.6)
P8.7 (KSO.7)

Port 8 / KSO.7–0:– I/O. Port 8 provides eight lines of open–drain psuedo–bi–directional
I/O port pins. Typically, these lines are used for key–scan outputs.

DS80CH11

011200 12/88

PIN SYMBOL DESCRIPTION

8
7
6
5
4
3
2
1

P9.0 (KSO.8)

P9.1 (KSO.9)
P9.2 (KSO.10)
P9.3 (KSO.11)
P9.4 (KSO.12)
P9.5 (KSO.13)
P9.6 (KSO.14)
P9.7 (KSO.15)

Port 9 / KSO.15–8: – I/O. Port 9 provides eight lines of open–drain psuedo–bi–direc­tional I/O port pins. Typically, these lines are used for key–scan outputs.

60
61
62
63
64
65
66
67

P10.0
P10.1
P10.2
P10.3
P10.4
P10.5
P10.6
P10.7

Port10: –I/O. Port 10 provides eight lines of general purpose Input or Output.

41 PM1CS Power Management #1 Chip Select: (Input, active low). This is a chip select signal

used to enable the power management #1 host interface port.

59 PM2CS Power Management #2 Chip Select: (Input, active low). This is a chip select signal

used to enable the power management #2 host interface port.

107 PSEN Program Store Enable: Output. This signal goes low when off–chip program memory

is being accessed via Ports 0 and 2. It is commonly connected to optional external ROM
memory as a chip enable. PSEN

will provide an active low pulse and is driven high when

external ROM is not being accessed.

105 RST Reset: Input, active high The RST input pin contains a Schmitt voltage input to recog-

nize external active high Reset inputs. The pin also employs an internal pull–down
resistor to allow for a combination of wired OR external Reset sources. An RC is not
required for power–up, as the controller provides this function internally.

55
54
53
52
51
50
49
48

SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7

System Data Bus: (Bi–directional). SD7–0 are data bus lines used for data transfers
between the host processor and the keyboard interface buffer and power management
#1 and #2 interface buffers.

39 SMI1 System Management Interrupt #1: (Output, active low). This signal is driven low

when the power management #1 host interface data buffer contains data to be read by
the host. SMI1

will be returned to a High Level when host reads the power management

#1 data buffer register.

58 SMI2 System Management Interrupt #2: (Output, active low). This signal is driven low

when the power management #2, host interface data buffer contains data to be read by
the host. SMI2

will be returned to a high level when the host reads the power manage-

ment #2 data buffer register .

DS80CH11

011200 13/88

PIN SYMBOL DESCRIPTION

18
85

120

VCC Digital Power Supply Input: For microcontroller and associated functions.

101 VPFW Power Fail Warning: Output, active low. The VPFW pin signals an impending power

failure when VCC drops below VPFW voltage threshold.

44 VRH A/D Positive Voltage Reference: The VRH pin is the positive reference (upper voltage

limit) of the A/D Converter.

45 VRL A/D Negative Voltage Reference: The VRL pin is the negative reference (lower volt-

age limit) of the A/D Converter.

102 VRST Power Fail Reset: Output, active low. The VRST pin signals a “power not good” condi-

tion to the system when system VCC has dropped below the VRST voltage threshold.

118
119

XTAL1
XTAL2

µC Crystal Oscillator Inputs. XTAL1 and XT AL2 provide support for parallel resonant,
AT cut crystals. XT AL1 acts also as an input if there is an external clock source in place
of a crystal. XTAL2 serves as the output of the crystal amplifier.

DS80CH11

011200 14/88

2.2 PIN CHARACTERISTICS

PIN NAME

POWER DOWN

MODE STATE

I/O BUFFER TYPE

RESET

STATE

36 A0 – I –
43 AGND – – –

106 ALE Low O Low

46 AVCC – – –
17 GND – – –
35 GND – – –
86 GND – – –

117 GND – – –

47 HGND – – –
68 HVCC – – –
38 IOR – I –
37 IOW – I –
42 KBCS – I –
40 KBOBF Hold O Low
57 NC – – –

56 NC – – –
108 NC – – –
121 P0.0 / AD0 High–Z Open–Drain (port)

CMOS drive (bus)

High–Z

122 P0.1 / AD1 High–Z Open–Drain (port)

CMOS drive (bus)

High–Z

123 P0.2 / AD2 High–Z Open–Drain (port)

CMOS drive (bus)

High–Z

124 P0.3 / AD3 High–Z Open–Drain (port)

CMOS drive (bus)

High–Z

125 P0.4 / AD4 High–Z Open–Drain (port)

CMOS drive (bus)

High–Z

126 P0.5 / AD5 High–Z Open–Drain (port)

CMOS drive (bus)

High–Z

127 P0.6 / AD6 High–Z Open–Drain (port)

CMOS drive (bus)

High–Z

128 P0.7 / AD7 High–Z Open–Drain (port)

CMOS drive (bus)

High–Z

87 P1.0 / T2 Hold Pull–up Weak High

88 P1.1 / T2EX Hold Pull–up Weak High

89 P1.2 / SCL1 Hold Open–drain High–Z

90 P1.3 / SDA1 Hold Open–drain High–Z

DS80CH11

011200 15/88

2.2 PIN CHARACTERISTICS (cont’d)

PIN NAME

POWER DOWN

MODE STATE

I/O BUFFER TYPE

RESET

STATE

91 P1.4 /SCL2 Hold Open–drain High–Z
92 P1.5 /SDA2 Hold Open–drain High–Z
93 P1.6 Hold Open–drain High–Z

94 P1.7 Hold Open–drain High–Z
109 P2.0 / A8 Hold Pull–up Weak High
110 P2.1 / A9 Hold Pull–up Weak High
111 P2.2 / A10 Hold Pull–up Weak High
112 P2.3 / A11 Hold Pull–up Weak High
113 P2.4 / A12 Hold Pull–up Weak High
114 P2.5 / A13 Hold Pull–up Weak High
115 P2.6 / A14 Hold Pull–up Weak High
116 P2.7 / A15 Hold Pull–up Weak High

95 P3.0 / RXD0 Hold Pull–up Weak High

96 P3.1 / TXD0 Hold Pull–up Weak High

97 P3.2 / INT0 Hold Pull–up Weak High

98 P3.3 / INT1 Hold Pull–up Weak High

99 P3.4 / T0 Hold Pull–up Weak High
100 P3.5 / T1 Hold Pull–up Weak High
103 P3.6 / WR Hold Pull–up Weak High
104 P3.7 / RD Hold Pull–up Weak High

77 P4.0 / KSI.0 Hold Pull–up Weak High

78 P4.1 / KSI.1 Hold Pull–up Weak High

79 P4.2 / KSI.2 Hold Pull–up Weak High

80 P4.3 / KSI.3 Hold Pull–up Weak High

81 P4.4 / KSI.4 Hold Pull–up Weak High

82 P4.5 / KSI.5 Hold Pull–up Weak High

83 P4.6 / KSI.6 Hold Pull–up Weak High

84 P4.7 / KSI.7 Hold Pull–up Weak High

34 P5.0 / AI.0 Hold Open–drain High–Z

33 P5.1 / AI.1 Hold Open–drain High–Z

32 P5.2 / AI.2 Hold Open–drain High–Z

31 P5.3 / AI.3 Hold Open–drain High–Z

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011200 16/88

2.2 PIN CHARACTERISTICS (cont’d)

PIN NAME

POWER DOWN

MODE STATE

I/O BUFFER TYPE

RESET

STATE

30 P5.4 / AI.4 Hold Open–drain High–Z
29 P5.5 / AI.5 Hold Open–drain High–Z
28 P5.6 / AI.6 Hold Open–drain High–Z
27 P5.7 / AI.7 Hold Open–drain High–Z
26 P6.0 / PWO.0 Hold Pull–up (PWMn disabled)

CMOS drive (PWMn enabled)

Weak High

25 P6.1 / PWO.1 Hold Pull–up (PWMn disabled)

CMOS drive (PWMn enabled)

Weak High

24 P6.2 / PWO.2 Hold Pull–up (PWMn disabled)

CMOS drive (PWMn enabled)

Weak High

23 P6.3 / PWO.3 Hold Pull–up (PWMn disabled)

CMOS drive (PWMn enabled)

Weak High

22 P6.4 / PWI.0 Hold Pull–up Weak High
21 P6.5 / PWI.1 Hold Pull–up Weak High
20 P6.6 Hold Pull–up Weak High
19 P6.7 / SOC Hold Pull–up Weak High
69 P7.0 / AMI.0 /

LED.0

Hold Pull–up Weak High

70 P7.1 / AMI.1 /

LED.1

Hold Pull–up Weak High

71 P7.2 / AMI.2 /

LED.2

Hold Pull–up Weak High

72 P7.3 / AMI.3 /

LED.3

Hold Pull–up Weak High

73 P7.4 / AMI.4/

LED.4

Hold Pull–up Weak High

74 P7.5 / AMI.5/

LED.5

Hold Pull–up Weak High

75 P7.6 / AMI.6/

LED.6

Hold Pull–up Weak High

76 P7.7 / AMI.7/

LED.7

Hold Pull–up Weak High

16 P8.0 / KSO.0 Hold Open–drain High–Z
15 P8.1 / KSO.1 Hold Open–drain High–Z
14 P8.2 / KSO.2 Hold Open–drain High–Z
13 P8.3 / KSO.3 Hold Open–drain High–Z
12 P8.4 / KSO.4 Hold Open–drain High–Z
11 P8.5 / KSO.5 Hold Open–drain High–Z
10 P8.6 / KSO.6 Hold Open–drain High–Z

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011200 17/88

2.2 PIN CHARACTERISTICS (cont’d)

PIN NAME

POWER DOWN

MODE STATE

I/O BUFFER TYPE

RESET

STATE

9 P8.7 / KSO.7 Hold Open–drain High–Z
8 P9.0 / KSO.8 Hold Open–drain High–Z
7 P9.1 / KSO.9 Hold Open–drain High–Z
6 P9.2 / KSO.10 Hold Open–drain High–Z
5 P9.3 / KSO.11 Hold Open–drain High–Z
4 P9.4 / KSO.12 Hold Open–drain High–Z
3 P9.5 / KSO.13 Hold Open–drain High–Z
2 P9.6 / KSO.14 Hold Open–drain High–Z

1 P9.7 / KSO.15 Hold Open–drain High–Z
60 P10.0 Hold Pull–up Weak High
61 P10.1 Hold Pull–up Weak High
62 P10.2 Hold Pull–up Weak High
63 P10.3 Hold Pull–up Weak High
64 P10.4 Hold Pull–up Weak High
65 P10.5 Hold Pull–up Weak High
66 P10.6 Hold Pull–up Weak High
67 P10.7 Hold Pull–up Weak High
41 PM1CS – I –
59 PM2CS – I –

107 PSEN Low O Low
105 RST – I –

55 SD0 (note 2) Bi–directional (note 2)
54 SD1 (note 2) Bi–directional (note 2)
53 SD2 (note 2) Bi–directional (note 2)
52 SD3 (note 2) Bi–directional (note 2)
51 SD4 (note 2) Bi–directional (note 2)
50 SD5 (note 2) Bi–directional (note 2)
49 SD6 (note 2) Bi–directional (note 2)
48 SD7 (note 2) Bi–directional (note 2)
39 SMI1 Hold O High
58 SMI2 Hold O High
18 VCC – – –
85 VCC – – –

120 VCC – – –

DS80CH11

011200 18/88

2.2 PIN CHARACTERISTICS (cont’d)

PIN NAME

POWER DOWN

MODE STATE

I/O BUFFER TYPE

RESET

STATE

101 VPFW (note 3) O (note 3)

44 VRH – – –
45 VRL – – –

102 VRST (note 3) O (note 3)

118 XTAL1 – I –
119 XTAL2 H O –

PIN STATE DESCRIPTIONS

High–Z High Impedance
Enabled Power applied; electrically functioning input
Unchanged Previous state not affected

NOTES:

1. As shown above, the original port pins P1.7–P1.2 have been modified to open–drain instead of having “Internal”
pull–up resistors.

2. This signal is independently powered from the HVCC on pin 68. As a result, the state of the reset pin and the power
down mode have no effect on its operation.

3. VRST

and VPFW reflects the state of VCC with respect to the power–fail reset and power–fail warning trip points,

respectively, and is unaf fected by the RST pin and power down mode state.

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011200 19/88

3.0 CORE MICROCONTROLLER

3.1 CORE MICRO OVERVIEW

The SEM incorporates the Dallas High Speed Micro
core which is a fully static CMOS 8051 compatible
microcontroller with a new internal architecture
designed for high performance. The higher speed
operation of the microcontroller core comes not just
from increasing the clock frequency, but from a newer,
more efficient design of the internal architecture. The
major features of the High Speed Micro Core include:

• 4 clocks/machine cycle (8032 = 12)

• Wasted cycles removed

• Runs DC to 25 Mhz clock rates @ 5V

• Single–cycle instruction in 160 ns

• Uses less power for equivalent work

• Dual data pointer

• Optional variable length MOVX to access fast/slow

RAM /peripherals

3.2 INSTRUCTION SET SUMMARY

All instructions in the SEM perform the same functions
as their 80C32 counterparts. Their affect on bits, flags,
and other status functions are identical. However, the
timing of each instruction is different. This applies both
in absolute and relative number of clocks.

For absolute timing of real–time events, the timing of
software loops will need to be calculated using the table
below. However, counter/timers default to run at the
older 12 clocks per increment. Therefore, while soft­ware runs at higher speed, timer–based events need no
modification to operate as before. Timers can be set to

run at 4 clocks per increment cycle to take advantage of
higher speed operation.

The relative time of two instructions might be different in
the new architecture than it was previously. For exam­ple, in the original architecture, the “MOVX A, @ DPTR”
instruction and the “MOV direct, direct” instruction used
two machine cycles or 24 oscillator cycles. Therefore,
they required the same amount of time. In the GEM, the
MOVX instruction can be done in two machine cycles or
8 oscillator cycles but the “MOV direct, direct” uses
three machine cycles or 12 oscillator cycles. While both
are faster than their original counterparts, they now
have different execution times from each other. This is
because in most cases, the SEM uses one cycle for
each byte. The timing of each instruction should be
examined for familiarity with the changes. Note that a
machine cycle now requires just four clocks, and pro­vides one ALE pulse per cycle. Many instructions
require only one cycle, but some require five. In the orig­inal architecture, all were one or two cycles except for
MUL and DIV.

INSTRUCTION SET SUMMARY Table 3–1

Legends:

A – Accumulator
Rn – Register R7–R0
direct – Internal Register address
@Ri – Internal Register pointed–to by R0 or R1

(except MOVX)
rel – 2’s complement offset byte
bit – direct bit–address
#data – 8–bit constant
#data 16 – 16–bit constant
addr 16 – 16–bit destination address
addr 11 – 11–bit destination address

DS80CH11

011200 20/88

INSTRUCTION SET SUMMARY Table 3–1 (cont’d)

INSTRUCTION BYTE

OSCILLATOR

CYCLES

INSTRUCTION BYTE

OSCILLATOR

CYCLES

Arithmetic Instructions:

ADD A, Rn 1 4 INC A 1 4
ADD A, direct 2 8 INC Rn 1 4
ADD A, @Ri 1 4 INC direct 2 8
ADD A, #data 2 8 INC @Ri 1 4
ADDC A, Rn 1 4 INC DPTR 1 12
ADDC A, direct 2 8 DEC A 1 4
ADDC A, @Ri 1 4 DEC Rn 1 4
ADDC A, #data 2 8 DEC direct 2 8
SUBB A, Rn 1 4 DEC @Ri 1 4
SUBB A, direct 2 8 MUL AB 1 20
SUBB A, @Ri 1 4 DIV AB 1 20
SUBB A, #data 2 8 DA A 1 4

Logical Instructions:

ANL A, Rn 1 4 XRL A, Rn 1 4
ANL A, direct 2 8 XRL A, direct 2 8
ANL A, @Ri 1 4 XRL A, @Ri 1 4
ANL A, #data 2 8 XRL A, #data 2 8
ANL direct, A 2 8 XRL direct, A 2 8
ANL direct, #data 3 12 XRL direct, #data 3 12
ORL A, Rn 1 4 CLR A 1 4
ORL A, direct 2 8 CPL A 1 4
ORL A, @Ri 1 4 RL A 1 4
ORL A, #data 2 8 RLC A 1 4
ORL direct, A 2 8 RR A 1 4
ORL direct, #data 3 12 RRC A 1 4

SWAP A 1 4

Data Transfer
Instructions:

MOV A, Rn 1 4 MOVC A, @A+DPTR 1 12
MOV A, direct 2 8 MOVC A, @A+PC 1 12
MOV A, @Ri 1 4 MOVX A, @Ri 1 8–36
MOV A, #data 2 8 MOVX A, @DPTR 1 8–36
MOV Rn, A 1 4 MOVX @Ri, A 1 8–36
MOV Rn, direct 2 8 MOVX @DPTR, A 1 8–36
MOV Rn, #data 2 8 PUSH direct 2 8
MOV direct, A 2 8 POP direct 2 8
MOV direct, Rn 2 8 XCH A, Rn 1 4
MOV direct1, direct2 3 12 XCH A, direct 2 8
MOV direct, @Ri 2 8 XCH A, @Ri 1 4
MOV direct, #data 3 12 XCHD A, @Ri 1 4
MOV @Ri, A 1 4
MOV @Ri, direct 2 8
MOV @Ri, #data 2 8
MOV DPTR, #data 16 3 12

DS80CH11

011200 21/88

INSTRUCTION SET SUMMARY Table 3–1 (cont’d)

Bit Manipulation
Instructions:

CLR C 1 4 ANL C, bit 2 8
CLR bit 2 8 ANL C, bit

28
SETB C 1 4 ORL C, bit 2 8
SETB bit 2 8 ORL C, bit

28
CPL C 1 4 MOV C, bit 2 8
CPL bit 2 8 MOV bit, C 2 8

Program Branching
Instructions:

ACALL addr 11 2 12 CJNE A, direct, rel 3 16
LCALL addr 16 3 16 CJNE A, #data, rel 3 16
RET 1 16 CJNE Rn, #data, rel 3 16
RETI 1 16 CJNE @ Ri, #data, rel 3 16
AJMP addr 11 2 12 NOP 1 4
LJMP addr 16 3 16 JC rel 2 12
SJMP rel 2 12 JNC rel 2 12
JMP @A+DPTR 1 12 JB bit, rel 3 16
JZ rel 2 12 JNB bit, rel 3 16
JNZ rel 2 12 JBC bit, rel 3 16
DJNZ Rn, rel 2 12
DJNZ direct, rel 3 16

The Table above shows the speed for each class of
instruction. Note that many of the instructions have mul­tiple opcodes. There are 255 opcodes for 111 instruc­tions. Of the 255 opcodes, 159 are three times faster
than the original 80C32. While a system than empha­sizes those instructions will see the most improvement,
the large total number that receive a three to one
improvement assure a dramatic speed increase for any
system. The speed improvement summary is provided
below.

3.3 SPEED IMPROVEMENT

The following table summarizes the speed improve­ment of the High Speed Micro core over a standard 12
clock / machine cycle 8052 device.

#Opcodes Speed Improvement

159 3.0 x
51 1.5 x
43 2.0 x
2 2.4 x
255 Average: 2.5

3.4 INSTRUCTION SET ADDITIONAL
REFERENCES

The user should refer to the Dallas High Speed Micro
User’s Guide for a complete description of the instruc­tion set including its address modes, coding, and timing
for the SEM.

3.5 RESET

The High–Speed Micro has three ways of entering a
reset state:

• Power–On / Fail Reset

• Watchdog Timer Reset

• External Reset

The operation of the CPU timing and states during a
reset are documented in the Dallas High Speed Micro
User’s Guide under the “Reset Conditions” section. The
Watchdog Timer reset is documented in the Watchdog
Timer section of the Dallas High Speed Micro User’s
Guide. The operation of the Power–On / Fail reset is
described in the Power Management section of this doc­ument.

DS80CH11

011200 22/88

3.6 INTERRUPT CONTROL

The SEM provides 16 sources of interrupt with three
priority levels. The Power–fail Interrupt (PFI), if
enabled, always has the highest priority . There are two
remaining user selectable priorities: high and low. If two
interrupts that have the same priority occur simulta-

neously, the hardware–determined precedence given
below determines which is a acted upon. Except for the
PFI, all interrupts that are new to the 8051 family have a
lower natural priority than the originals.

INTERRUPT PRIORITY Table 3–2

NAME DESCRIPTION VECTOR

NATURAL
PRIORITY

8051/DALLAS

PFI Power Fail Interrupt 33h 1 DALLAS
INT0 External Interrupt 0 03h 2 8051
TF0 Timer 0 0Bh 3 8051
INT1 External Interrupt 1 13h 4 8051
TF1 Timer 1 1Bh 5 8051
SCON0 TI0 or RI0 from Serial Port 0 23h 6 8051
TF2 Timer 2 2Bh 7 8051
AMI Activity Monitor Interrupt 3Bh 8 DALLAS
2WI1 2–Wire Serial Port 1 43h 9 DALLAS
ADI A/D End of Conversion 4Bh 10 DALLAS
2WI2 2–Wire Serial Port 2 53h 11 DALLAS
KBI Keyboard Buffer Input 5Bh 12 DALLAS
PBI1 Power Mgmt. Buffer Input #1 63h 13 DALLAS
KDI Key Detect Input 6Bh 14 DALLAS
WDI WatchDog Periodic Interrupt 73h 15 DALLAS
PBI2 Power Mgmt. Buffer Input #2 7Bh 16 DALLAS

INTERRUPT CONTROL SUMMARY Table 3–3

INTERRUPT

SOURCE

FLAG(S)

FLAG

LOC.

ENABLE

ENABLE

LOC.

PRIORITY

PRIORITY

LOC.

Power Fail PFI WDCON.4 EPFI WDCON.5 N/A N/A
External 0 IE0 TCON.1 EX0 IE.0 PX0 IP.0
Timer 0 TF0 TCON.5 ET0 IE.1 PT0 IP.1
External 1 IE1 TCON.3 EX1 IE.2 PX1 IP.2
Timer 1 TF1 TCON.7 ET1 IE.3 PT1 IP.3
Serial Port 0 RI0,TI0 SCON0.0/

SCON0.1

ES0 IE.4 PS0 IP.4

Timer 2 TF2 T2CON.7 ET2 IE.5 PT2 IP.5
Activity monitor AMF7–0 AMF.7–0 EAM IE.6 PAM IP.6

DS80CH11

011200 23/88

INTERRUPT CONTROL SUMMARY Table 3–3 (cont’d)

INTERRUPT

SOURCE

FLAG(S)

FLAG

LOC.

ENABLE

ENABLE

LOC.

PRIORITY

PRIORITY

LOC.

2–Wire Serial Port 1 2WIF1 2WCON1.4 E2W1 EIE.0 P2W1 EIP.0
A/D End of Conv. EOC ADCON1.6 EAD EIE.1 PAD EIP.1
2–Wire Serial Port 2 2WIF2 2WCON2.4 E2W2 EIE.2 P2W2 EIP.2
Keyboard Buffer KIBF KBSTAT.1 EKB EIE.3 PKB EIP.3
Power Mgmt. #1 Buffer PIBF1 PMSTAT1.1 EPB1 EIE.4 PPB1 EIP.4
Key Detect Input KDF7–0 KDF.7–0 EKD EIE.5 PKD EIP.5
WatchDog periodic WDIF WDCON.3 EWDI EIE.6 PWDI EIP.6
Power Mgmt. #2 Buffer PIBF2 PMSTAT2.1 EPB2 EIE.7 PPB2 EIP.7

A complete description of the interrupt structure of the microcontroller core including operation of the priority scheme
and acknowledgment operation is contained in the Dallas High Speed Micro User’s Guide.

DS80CH11

011200 24/88

4.0 MEMORY RESOURCES

4.1 OVERVIEW

The SEM contains the following memory resources and
features:

• 256 bytes of on–chip direct (scratchpad) RAM

• 256 bytes of on–chip MOVX data RAM

• Off–chip program and data memory expansion

• Software enable/disable of on–chip data memory

4.2 DATA MEMORY ACCESS

Unlike many 8051 derivatives, the SEM contains on–
chip data memory. Although physically on–chip, soft­ware accesses this area in the same way off–chip data
memory is accessed: via the MOVX instruction. The
256 bytes of SRAM is located between address 0000h
and 00FFh.

Access to the on–chip data RAM is optional under soft­ware control. When enabled by software, the data

SRAM is between 0000h and 00FFh. Any MOVX
instruction that uses this area will go to the on–chip RAM
while enabled. MOVX addresses greater than 256
automatically go to external memory through Ports
0 & 2.

When disabled, the 256 bytes of memory area is trans­parent to the system memory map. Any MOVX directed
to the space between 0000h and FFFFh goes to the
expanded bus on Ports 0 & 2. This also is the default
condition. This default allows the SEM to drop into an
existing system that uses these addresses for other
hardware and still have full compatibility.

The on–chip data area is selected by software using two
bits in the Power Management Register at location C4h.
This selection is dynamically programmable. Thus
access to the on–chip area becomes transparent to
reach off–chip devices at the same addresses. The
control bits are DME1 (PMR.1) and DME0 (PMR.0).
Their operation is described in Table 4–1.

DATA MEMORY ACCESS CONTROL Table 4–1

DME1 DME0 DATA MEMORY ADDRESS MEMORY FUNCTION

0 0 0000h – FFFFh External Data Memory (Default condition)
0 1 0000h – 00FFh

0100h – FFFFh

Internal SRAM Data Memory

External Data Memory
1 0 Reserved Reserved
1 1 0000h – 00FFh

0100h – FFFBh

FFFCh

FFFDh – FFFFh

Internal SRAM Data Memory

Reserved – no external access

Read access to the status of lock bits

Reserved – no external access

Notes on the status byte read at FFFCh with DME1, 0 = 1, 1: Bits 2–0 reflect the programmed status of the security
lock bits LB3–LB1. They are individually set to a logic 1 to correspond to a security lock bit that has been programmed.
These status bits allow software to verify that the part has been locked before running if desired. The bits are read
only.

4.2.1 Stretch Memory Cycle

The SEM allows software to adjust the speed of off–chip
data memory access. The micro is capable of perform­ing the MOVX in as little as two instruction cycles. The
on–chip SRAM uses this speed and any MOVX instruc­tion directed internally uses two cycles. However, the
time can be stretched for interface to external devices.
This allows access to both fast memory and slow
memory or peripherals with no glue logic. Even in high–
speed systems, it may not be necessary or desirable to

perform off–chip data memory access at full speed. In
addition, there are a variety of memory mapped periph­erals such as LCDs or UARTs that are slow.

Operation of the Stretch MOVX function is fully docu­mented in the Dallas High Speed Micro User’s Guide.

DS80CH11

011200 25/88

4.2.2 Dual Data Pointer

A second data pointer register (DPTR 1) is incorporated
into the SEM in addition to the standard one in the 8051.
This feature allows faster execution of many operations
involving data memory access, such as block moves.

Operation of the dual data pointer function is fully docu­mented in the Dallas High Speed Micro User’s Guide.

4.3 EXTERNAL MEMORY INTERFACE

Interface techniques for interfacing external memory as
program or data storage to the SEM via Ports 0 and 2
are described in the Dallas High Speed Micro User’s
Guide.

4.4 DIRECT (SCRATCHPAD) RAM ACCESS

The SEM incorporates a full 256 bytes of direct RAM.
This RAM is accessed in a manner identical to that of a

standard 80C52 compatible device. A full description of
this memory along with the instructions that access it is
contained in the Dallas High Speed Micro User’s Guide.

4.5 SPECIAL FUNCTION REGISTERS

Special Function Registers (SFRs) control most special
features of the SEM. This allows the SEM to have many
new features but use the same instruction set as the

8051. When writing software to use a new feature, an
equate statement defines the SFR to an assembler or
compiler. This is the only change needed to access the
new function. The SEM duplicates the SFRs contained
in the standard 80C52. Table 4–2 is a summary of the
values loaded into the SEM’s SFR’s on reset. T able 4–3
is a summary of all of the SFR’s and the control bits they
contain.

F8h

F0h

E8h

E0h

D8h

D0h

C8h

C0h
B8h

B0h

A8h

A0h

98h

90h

88h

80h

DS80CH11

011200 26/88

SPECIAL FUNCTION REGISTER RESET VALUES Table 4–2

* New functions are in bold

EIP

00000000

B

00000000

PORT10
11111111

PMSTAT2

XXXXXX00

PMDIN2

XXXXXXXX

PMDOUT2

XXXXXXXX

EIE

00000000

PORT9

11111111

PW23CON

00000000

PWM2

00000000

PWM3

00000000

ACC

00000000

PORT8

11111111

PW23CS

00000000

PW2FG

00000000

PW3FG

00000000

WDCON

0X0X0XX0

2WCON2

00000000

2WSTAT12

00000000

2WSTAT22

00000000

PW01CON

00000000

PWM0

00000000

PWM1

00000000

PSW

00000000

2WSADR2

00000000

2WDAT2

00000000

2WFS2

00000000

PORT7

11111111

PW01CS

00000000

PW0FG

00000000

PW1FG

00000000

T2CON

00000000

T2MOD

11111100

RCAP2L

00000000

RCAP2H

00000000

TL2

00000000

TH2

00000000

PMR

010X0000

STATUS

00000000

TA

11111111

IP

10000000

SADEN0

00000000

PORT6

11111111

PMSTAT1

XXXXXX00

PMDIN1

XXXXXXXX

PMDOUT1

XXXXXXXX

PORT3

11111111

ADCON1

00000000

ADCON2
00000000

ADMSB

00000000

ADLSB

00000000

WINHI

00000000

WINLO

00000000

IE

00000000

SADDR0

00000000

PORT5

11111111

KBSTAT

XXXXXX00

KBDIN

XXXXXXXX

KBDOUT

XXXXXXXX

PORT2

11111111

PORT4

11111111

KDE

00000000

KDF

00000000

SCON0

00000000

SBUF0

00000000

2WSADR1

00000000

2WDAT1

00000000

2WFS1

00000000

2WCON1
00000000

2WSTAT11

00000000

2WSTAT21

00000000

PORT1

11111111

EXIF

0000XXX0

AME

00000000

AMQ

00000000

AMP

00000000

AMF

00000000

TCON

00000000

TMOD

00000000

TL0

00000000

TL1

00000000

TH0

00000000

TH1

00000000

CKCON

00000001

PORT0

11111111SP000001 11

DPL

00000000

DPH

00000000

DPL1

00000000

DPH1

00000000

DPS

00000000

PCON

00110000

FFh

F7h

EFh

E7h

DFh

D7h

CFh

C7h

BFh

B7h

AFh

A7h

9Fh

97h

8Fh

87h

DS80CH11

011200 27/88

SPECIAL FUNCTION REGISTER LOCATIONS Table 4–3

* New functions are in bold

REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ADDRESS

PORT0 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 80h
SP 81h
DPL 82h
DPH 83h

DPL1 84h
DPH1 85h
DPS 0 0 0 0 0 0 0 SEL 86h

PCON SMOD SMOD0 – – GF1 GF0 STOP IDLE 87h
TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 88h
TMOD GATE C/T M1 M0 GATE C/T M1 M0 89h
TL0 8Ah
TL1 8Bh
TH0 8Ch
TH1 8Dh
CKCON WD1 WD0 T2M T1M T0M MD2 MD1 MD0 8Eh
PORT1 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 90h

EXIF – – – – XT/RG RGMD RGSL BGS 91h
AME AME7 AME6 AME5 AME4 AME3 AME2 AME1 AME0 92h
AMQ AMQ7 AMQ6 AMQ5 AMQ4 AMQ3 AMQ2 AMQ1 AMQ0 93h
AMP AMP7 AMP6 AMP5 AMP4 AMP3 AMP2 AMP1 AMP0 94h
AMF AMF7 AMF6 AMF5 AMF4 AMF3 AMF2 AMF1 AMF0 95h

SCON0 SM0/FE SM1 SM2 REN TB8 RB8 TI0 RI0 98h
SBUF0 SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0 99h

2WSADR1 SLA6 SLA5 SLA4 SLA3 SLA2 SLA1 SLA0 – 9Ah
2WDAT1 9Bh
2WFS1 9Ch
2WCON1 2WEN1 STA1 STO1 2WIF1 BMM1 ANAK1 – – 9Dh
2WSTAT11 BER1 ARL1 RSTO1 TXI1 RXI1 TSTA1 RSTA1 – 9Eh
2WSTAT21 BB1 ADM1 X/R1 ACKS1 – – – – 9Fh

PORT2 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 A0h

PORT4 P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0 A4h
KDE KDE7 KDE6 KDE5 KDE4 KDE3 KDE2 KDE1 KDE0 A5h
KDF KDF7 KDF6 KDF5 KDF4 KDF3 KDF2 KDF1 KDF0 A6h

IE EA EAM ET2 ES0 ET1 EX1 ET0 EX0 A8h
SADDR0 A9h