Dallas Semiconductor DS80C323-QCD, DS80C323-MCD, DS80C323-ECD, DS80C320-QNL, DS80C320-QNG Datasheet
...
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple
ormation about device errata,
DS80C320/DS80C323
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axim
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FEATURES
§ 80C32-Compatible
- 8051 pin and instruction set compatible
- Four 8-bit I/O ports
- Three 16-bit timer/counters
- 256 bytes scratchpad RAM
- Addresses 64 kB ROM and 64 kB RAM
§ High-speed architecture
- 4 clocks/machine cycle (8032=12)
- DC to 33 MHz (DS80C320)
- DC to 18 MHz (DS80C323)
- Single-cycle instruction in 121 ns
- Uses less power for equivalent work
- Dual data pointer
- Optional variable length MOVX to access
fast/slow RAM/peripherals
§ High integration controller includes:
- Power-fail reset
- Programmable watchdog timer
- Early -warning power-fail interrupt
§ Two full-duplex hardware serial ports
§ 13 total interrupt sources with six external
§ Available in 40-pin DIP, 44-pin PLCC and
TQFP
High-Speed/Low-Power Micro
PIN ASSIGNMENT
revisions of any device may be simultaneously available through various sales channels. For inf
click here: http://www.maxim-ic.com/errata.
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DS80C320/DS80C323
DESCRIPTION
The DS80C320/DS80C323 is a fast 80C31/80C32-compatible microcontroller. Wasted clock and
memory cycles have been removed using a redesigned processor core. As a result, every 8051 instruction
is executed between 1.5 and 3 times faster than the original for the same crystal speed. Typical
applications will see a speed improvement of 2.5 times using the same code and same crystal. The
DS80C320 offers a maximum crystal rate of 33 MHz, resulting in apparent execution speeds of 82.5 MHz
(approximately 2.5X).
The DS80C320/DS80C323 is pin-compatible with all three packages of the standard 80C32 and offers the
same timer/counters, serial port, and I/O ports. In short, the device is extremely familiar to 8051 users but
provides the speed of a 16-bit processor.
The DS80C320 provides several extras in addition to greater speed. These include a second full hardware
serial port, seven additional interrupts, programmable watchdog timer, power-fail interrupt and reset. The
device also provides dual data pointers (DPTRs) to speed block data memory moves. It can also adjust the
speed of off-chip data memory access to between two and nine machine cycles for flexibility in selecting
memory and peripherals.
The DS80C320 operating voltage ranges from 4.25V to 5.5V, making it ideal as a high-performance
upgrade to existing 5V systems. For applications in which power consumption is critical, the DS80C323
offers the same feature set as the DS80C320, but with 2.7V to 5.5V operation.
ORDERING INFORMATION
PART NUMBER PACKAGE MAX CLOCK SPEED TEMPERATURE RANGE
DS80C320-MCG 40-pin plastic DIP 25 MHz 0°C to +70°C
DS80C320-QCG 44-pin PLCC 25 MHz 0°C to +70°C
DS80C320-ECG 44-pin TQFP 25 MHz 0°C to +70°C
DS80C320-MNG 40-pin plastic DIP 25 MHz -40°C to +85°C
DS80C320-QNG 44-pin PLCC 25 MHz -40°C to +85°C
DS80C320-ENG 44-pin TQFP 25 MHz -40°C to +85°C
DS80C320-MCL 40-pin plastic DIP 33 MHz 0°C to +70°C
DS80C320-QCL 44-pin PLCC 33 MHz 0°C to +70°C
DS80C320-ECL 44-pin TQFP 33 MHz 0°C to +70°C
DS80C320-MNL 40-pin plastic DIP 33 MHz -40°C to +85°C
DS80C320-QNL 44-pin PLCC 33 MHz -40°C to +85°C
DS80C320-ENL 44-pin TQFP 33 MHz -40°C to +85°C
DS80C323-MCD 40-pin plastic DIP 18 MHz 0°C to +70°C
DS80C323-QCD 44-pin PLCC 18 MHz 0°C to +70°C
DS80C323-ECD 44-pin TQFP 18 MHz 0°C to +70°C
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DS80C320 BLOCK DIAGRAM Figure 1
DS80C320/DS80C323
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DS80C320/DS80C323
commonly connected to external ROM memory as a chip enable.
INT3
INT5
PIN DESCRIPTION Table 1
DIP PLCC TQFP SIGNAL NAME DESCRIPTION
40 44 38 VCC VCC - +5V. (+3V DS80C323)
20 22, 23 16, 17 GND GND - Digital circuit ground.
9 10 4 RST RST - Input. The RST input pin contains a Schmitt voltage input to
recognize external active high Reset inputs. The pin also employs an
internal pulldown resistor to allow for a combination of wired OR
external Reset sources. An RC is not required for power-up, as the
device provides this function internally.
18
19
29 32 26
30 33 27 ALE ALE – Output. The Address Latch Enable output functions as a
39
38
37
36
35
34
33
32
1-8 2-9 40-44
Port Alternate Function
1 2 40 P1.0 T2 External I/O for Timer/Counter 2
2 3 41 P1.1 T2EX Timer/Counter 2 Capture/Reload Trigger
3 4 42 P1.2 RXD1 Serial Port 1 Input
4 5 43 P1.3 TXD1 Serial Port 1 Output
5 6 44 P1.4 INT2 External Interrupt 2 (Positive Edge Detect)
6 7 1
7 8 2 P1.6 INT4 External Interrupt 4 (Positive Edge Detect)
8 9 3
20
21
43
42
41
40
39
38
37
36
14
15
37
36
35
34
33
32
31
30
1-3
XTAL2
XTAL1
XTAL1, XTAL2 - The crystal oscillator pins XTAL1 and XTAL2
provide support for parallel resonant, AT cut crystals. XTAL1 acts
also as an input in the event that an external clock source is used in
place of a crystal. XTAL2 serves as the output of the crystal
amplifier.
PSEN PSEN - Output. The Program Store Enable output. This signal is
PSEN will provide an active low pulse width of 2.25 XTAL1 cycles
with a period of four XTAL1 cycles. PSEN is driven high when data
memory (RAM) is being accessed through the bus and during a reset
condition.
clock to latch the external address LSB from the multiplexed
address/data bus. This signal is commonly connected to the latch
enable of an external 373 family transparent latch. ALE has a pulse
width of 1.5 XTAL1 cycles and a period of four XTAL1 cycles. ALE
is forced high when the device is in a Reset condition.
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD0-7 (Port 0) - I/O. Port 0 is the multiplexed address/data bus.
During the time when ALE is high, the LSB of a memory address is
presented. When ALE falls, the port transitions to a bi-directional
data bus. This bus is used to read external ROM and read/write
external RAM memory or peripherals. The Port 0 has no true port
latch and can not be written directly by software. The reset condition
of Port 0 is high. No pullup resistors are needed.
AD7
P1.0-P1.7 Port 1 - I/O. Port 1 functions as both an 8-bit bi-directional I/O port
and an alternate functional interface for Timer 2 I/O, new External
Interrupts, and new Serial Port 1. The reset condition of Port 1 is with
all bits at a logic 1. In this state, a weak pullup holds the port high.
This condition also serves as an input mode, since any external
circuit that writes to the port will overcome the weak pullup. When
software writes a 0 to any port pin, the device will activate a strong
pulldown that remains on until either a 1 is written or a reset occurs.
Writing a 1 after the port has been at 0 will cause a strong transition
driver to turn on, followed by a weaker sustaining pullup. Once the
momentary strong driver turns off, the port once again becomes the
output high (and input) state. The alternate modes of Port 1 are
outlined as follows:
P1.5
P1.7
External Interrupt 3 (Negative Edge Detect)
External Interrupt 5 (Negative Edge Detect)
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DS80C320/DS80C323
INT0
INT1
DIP PLCC TQFP SIGNAL NAME DESCRIPTION
21
22
23
24
25
26
27
28
10-17
Port Alternate Mode
10 11 5 P3.0 RXD0 Serial Port 0 Input
11 13 7 P3.1 TXD0 Serial Port 0 Output
12 14 8
13 15 9
14 16 10 P3.4 T0 Timer 0 External Input
15 17 11 P3.5 T1 Timer 1 External Input
16 18 12
17 19 13
31 35 29
- 12
- 1 39 NC - Reserved. These pins are reserved for additional ground pins
24
25
26
27
28
29
30
31
11,
13-19
34
18
19
20
21
22
23
24
25
5, 7-13 P3.0-P3.7 Port 3 - I/O. Port 3 functions as both an 8-bit bi-directional I/O port
6
28
A8 (P2.0)
A9 (P2.1)
A10 (P2.2)
A11 (P2.3)
A12 (P2.4)
A13 (P2.5)
A14 (P2.6)
A15 (P2.7)
EA EA - Input. This pin must be connected to ground for proper
NC NC - Reserved. These pins should not be connected. They are
A15-A8 (Port 2) - Output . Port 2 serves as the MSB for external
addressing. P2.7 is A15 and P2.0 is A8. The device will
automatically place the MSB of an address on P2 for external ROM
and RAM access. Although Port 2 can be accessed like an ordinary
I/O port, the value stored on the Port 2 latch will never be seen on the
pins (due to memory access). Therefore writing to Port 2 in software
is only useful for the instructions MOVX A, @Ri or MOVX @Ri, A.
These instructions use the Port 2 internal latch to supply the external
address MSB. In this case, the Port 2 latch value will be supplied as
the address information.
and an alternate functional interface for External Interrupts, Serial
Port 0, Timer 0 & 1 Inputs, RD and WR strobes. The reset condition
of Port 3 is with all bits at a logic 1. In this state, a weak pullup holds
the port high. This condition also serves as an input mode, since any
external circuit that writes to the port will overcome the weak pullup.
When software writes a 0 to any port pin, the device will activate a
strong pulldown that remains on until either a 1 is written or a reset
occurs. Writing a 1 after the port has been at 0 will cause a strong
transition driver to turn on, followed by a weaker sustaining pullup.
Once the momentary strong driver turns off, the port once again
becomes both the output high and input state. The alternate modes of
Port 3 are outlined below:
P3.2
P3.3
P3.6 WR External Data Memory Write Strobe
P3.7 RD External Data Memory Read Strobe
operation.
reserved for use with future devices in this family.
on future products.
External Interrupt 0
External Interrupt 1
80C32 COMPATIBILITY
The DS80C320/DS80C323 is a CMOS 80C32-compatible microcontroller designed for high
performance. In most cases it will drop into an existing 80C32 design to significantly improve the
operation. Every effort has been made to keep the device familiar to 8032 users, yet it has many new
features. In general, software written for existing 80C32-based systems will work on the
DS80C320/DS80C323. The exception is critical timing since the High-Speed Microcontroller performs
its instructions much faster than the original. It may be necessary to use memories with faster access
times if the same crystal frequency is used.
Application note 57 “DS80C320 Memory Interface Timing” is a useful tool to help the embedded system
designer select the proper memories for her or his application.
The DS80C320/DS80C323 runs the standard 8051 instruction set and is pin-compatible with an 80C32 in
any of three standard packages. It also provides the same timer/counter resources, full-duplex serial port,
256 bytes of scratchpad RAM and I/O ports as the sta ndard 80C32. Timers will default to a 12 clock per
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DS80C320/DS80C323
cycle operation to keep timing compatible with original 8051 systems. However, they can be programmed
to run at the new 4 clocks per cycle if desired.
New hardware features are accessed using Special Func tion Registers that do not overlap with standard
80C32 locations. A summary of these SFRs is provided below.
The DS80C320/DS80C323 addresses memory in an identical fashion to the standard 80C32. Electrical
timing will appear different due to the high-speed nature of the product. However, the signals are
essentially the same. Detailed timing diagrams are provided below in the electrical specifications.
This data sheet assumes the user is familiar with the basic features of the standard 80C32. In addition to
these standard features, the DS80C320/DS80C323 includes many new functions. This data sheet provides
only a summary and overview. Detailed descriptions are available in the User’s Guide located in the front
of the High-Speed Microcontroller data book.
COMPARATIVE TIMING OF THE DS80C320/DS80C323 AND 80C32 Figure 2
DS80C320/DS80C323 TIMING
STANDARD 80C32 TIMING
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DS80C320/DS80C323
HIGH -SPEED OPERATION
The DS80C320/DS80C323 is built around a high speed 80C32 compatible core. Higher speed comes not
just from increasing the clock frequency, but from a newer, more efficient design.
In this updated core, dummy memory cycles have been eliminated. In a conventional 80C32, machine
cycles are generated by dividing the clock frequency by 12. In the DS80C320/DS80C323, the same
machine cycle is performed in 4 clocks. Thus the fastest instruction, one machine cycle, is executed three
times faster for the same crystal frequency. Note that these are identical instructions. A comparison of the
timing differences is shown in Figure 2. The majority of instructions will see the full 3 to 1 speed
improvement. Some instructions will get between 1.5 and 2.4 X improvement. Note that all instructions
are faster than the original 80C51. Table 2 below shows a summary of the instruction set including the
speed.
The numerical average of all opcodes is approximately a 2.5 to 1 speed improvement. Individual
programs will be affected differently, depending on the actual instructions used. Speed-sensitive
applications would make the most use of instructions that are three times faster. However, the sheer
number of 3 to 1 improved opcodes makes dramatic speed improvements likely for any code. The Dual
Data Pointer feature also allows the user to eliminate wasted instructions when moving blocks of
memory.
INSTRUCTION SET SUMMARY
All instructions in the DS80C320/DS80C323 perform the same functions as their 80C32 counterparts.
Their effect on bits, flags, and other status functions is identical. However, the timing of each instruction
is different. This applies both in absolute and relative number of clocks.
For absolute timing of real-time events, the timing of software loops will need to be calculated using the
table below. However, counter/timers default to run at the older 12 clocks per increment. Therefore, while
software runs at higher speed, timer-based events need no modification to operate as before. Timers can
be set to run at 4 clocks per increment cycle to take advantage of higher speed operation.
The relative time of two instructions might be different in the new architecture than it was previously. For
example, in the original architecture, the “MOVX A, @DPTR” instruction and the “MOV direct, direct”
instruction used two machine cycles or 24 oscillator cycles. Therefore, they required the same amount of
time. In the DS80C320/DS80C323, the MOVX instruction can be done in two machine cycles or eight
oscillator cycles but the “MOV direct, direct” uses three machine cycles or 12 oscillator cycles. While
both are faster than their original counterpa rts, they now have different execution times from each other.
This is because in most cases, the DS80C320/DS80C323 uses one cycle for each byte. The user
concerned with precise program timing should examine the timing of each instruction for familiarity with
the changes. Note that a machine cycle now requires just four clocks, and provides one ALE pulse per
cycle. Many instructions require only one cycle, but some require five. In the original architecture, all
were one or two cycles except for MUL and DIV.
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DS80C320/DS80C323
INSTRUCTION SET SUMMARY Table 2
Legends:
A - Accumulator
Rn - Register R7 -R0
direct - Internal Register address
@Ri - Internal Register pointed-to by R0 or R1 (except MOVX)
rel - 2’s complement offset byte
bit - direct bit-address
#data - 8-bit constant
#data 16 - 16-bit constant
addr 16 - 16-bit destination address
addr 11 - 11-bit destination address
OSCILLATOR OSCILLATOR
INSTRUCTION BYTE CYCLES INSTRUCTION BYTE CYCLES
Arithmatic Instructions:
ADD A, Rn 1 4 INC A 1 4
ADD A, direct 2 8 INC Rn 1 4
ADD A, @Ri 1 4 INC direct 2 8
ADD A, #data 2 8 INC @Ri 1 4
ADDC A, Rn 1 4 INC DPTR 1 12
ADDC A, direct 2 8 DEC A 1 4
ADDC A, @Ri 1 4 DEC Rn 1 4
ADDC A, #data 2 8 DEC direct 2 8
SUBB A, Rn 1 4 DEC @Ri 1 4
SUBB A, direct 2 8 MUL AB 1 20
SUBB A, @Ri 1 4 DIV AB 1 20
SUBB A, #data 2 8 DA A 1 4
Logical Instructions:
ANL A, Rn 1 4 XRL A, Rn 1 4
ANL A, direct 2 8 XRL A, direct 2 8
ANL A, @Ri 1 4 XRL A, @Ri 1 4
ANL A, #data 2 8 XRL A, #data 2 8
ANL direct, A 2 8 XRL direct, A 2 8
ANL direct, #data 3 12 XRL direct, #data 3 12
ORL A, Rn 1 4 CLR A 1 4
ORL A, direct 2 8 CPL A 1 4
ORL A, @Ri 1 4 RL A 1 4
ORL A, #data 2 8 RLC A 1 4
ORL direct, A 2 8 RR A 1 4
ORL direct, #data 3 12 RRC A 1 4
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DS80C320/DS80C323
Data Transfer
Instructions:
MOV A, Rn 1 4 MOVC A, @A+DPTR 1 12
MOV A, direct 2 8 MOVC A, @A+PC 1 12
MOV A, @Ri 1 4 MOVX A, @Ri 1 8-36*
MOV A, #data 2 8 MOVX A, @DPTR 1 8-36*
MOV Rn, A 1 4 MOVX @Ri, A 1 8-36*
MOV Rn, direct 2 8 MOVX @DPTR, A 1 8-36*
MOV Rn, #data 2 8 PUSH direct 2 8
MOV direct, A 2 8 POP direct 2 8
MOV direct, Rn 2 8 XCH A, Rn 1 4
MOV direct1, direct2 3 12 XCH A, direct 2 8
MOV direct, @Ri 2 8 XCH A, @Ri 1 4
MOV direct, #data 3 12 XCHD A, @Ri 1 4
MOV @Ri, A 1 4
MOV @Ri, direct 2 8
MOV @Ri, #data 2 8
MOV DPTR, #data 16 3 12
*User Selectable
Bit Manipulation
Instructions:
CLR C 1 4 ANL C, bit 2 8
CLR bit 2 8
SETB C 1 4 ORL C, bit 2 8
SETB bit 2 8
CPL C 1 4 MOV C, bit 2 8
CPL bit 2 8 MOV bit, C 2 8
Program Branching
Instructions:
ACALL addr 11 2 12 CJNE A, direct, rel 3 16
LCALL addr 16 3 16 CJNE A, #data, rel 3 16
RET 1 16 CJNE Rn, #data, rel 3 16
RETI 1 16 CJNE Ri, #data, rel 3 16
AJMP addr 11 2 12 NOP 1 4
LJMP addr 16 3 16 JC rel 2 12
SJMP rel 2 12 JNC rel 2 12
JMP @A+DPTR 1 12 JB bit, rel 3 16
JZ rel 2 12 JNB bit, rel 3 16
JNZ rel 2 12 JBC bit, rel 3 16
DJNZ Rn, rel 2 12
DJNZ direct, rel 3 16
ANL C, bit
ORL C, bit
2 8
2 8
The table above shows the speed for each class of instruction. Note that many of the instructions have
multiple opcodes. There are 255 opcodes for 111 instructions. Of the 255 opcodes, 159 are three times
faster than the original 80C32. While a system that emphasizes those instructions will see the most
improvement, the large total number that receive a 3 to 1 improvement assure a dramatic speed increase
for any system. The speed improvement summary is provided below.
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DS80C320/DS80C323
SPEED ADVANTAGE SUMMARY
#Opcodes Speed Improvement
159 3.0 x
51 1.5 x
43 2.0 x
2 2.4 x
255 Average: 2.5
MEMORY ACCESS
The DS80C320/DS80C323 contains no on-chip ROM and 256 bytes of scratchpad RAM. Off-chip
memory is accessed using the multiplexed address/data bus on P0 and the MSB address on P2. A typical
memory connection is shown in Figure 3. Timing diagrams are provided in the Electrical Specifications.
Program memory (ROM) is accessed at a fixed rate determined by the crystal frequency and the actual
instructions. As mentioned above, an instruction cycle requires 4 clocks. Data memory (RAM) is
accessed according to a variable speed MOVX instruction as described below.
TYPICAL MEMORY CONNECTION Figure 3
STRETCH MEMORY CYCLE
The DS80C320/DS80C323 allows the application software to adjust the speed of data memory access.
The microcontroller is capable of performing the MOVX in as little as two instruction cycles. However,
this value can be stretched as needed so that both fast memory and slow memory or peripherals can be
accessed with no glue logic. Even in high-speed systems, it may not be necessary or desirable to perform
data memory access at full speed. In addition, there are a variety of memory mapped peripherals such as
LCD displays or UARTs that are not fast.
The Stretch MOVX is controlled by the Clock Control Register at SFR location 8Eh as described below.
This allows the user to select a stretch value between 0 and 7. A Stretch of 0 will result in a two -machine
cycle MOVX. A Stretch of 7 will result in a MOVX of nine machine cycles. Software can dynamically
change this value depending on the particular memory or peripheral.
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DS80C320/DS80C323
On reset, the Stretch value will default to a 1, resulting in a three-cycle MOVX. Therefore, RAM access
will not be performed at full speed. This is a convenience to existing designs that may not have fast RAM
in place. When maximum speed is desired, the software should select a Stretch value of 0. When using
very slow RAM or peripherals, a larger stretch value can be selected. Note that this affects data memory
only and the only way to slow program memory (ROM) access is to use a slower crystal.
Using a Stretch value between 1 and 7 causes the microcontroller to stretch the read/write strobe and all
related timing. This results in a wider read/write strobe allowing more time for memory/peripherals to
respond. The timing of the variable speed MOVX is shown in the Electrical Specifications. Note that full
speed access is not the reset default case. Table 3 below shows the resulting strobe widths for each
Stretch value. The memory stretch is implemented using the Clock Control Special Function Register at
SFR location 8Eh. The stretch value is selected using bits CKCON.2-0. In the table, these bits are referred
to as M2 through M0. The first stretch (default) allows the use of common 120 ns or 150 ns RAMs
without dramatically lengthening the memory access.
DATA MEMORY CYCLE STRETCH VALUES Table 3
CKCON.2-0 MEMORY
RD or WR STROBE
MD2 MD1 MD0 CYCLES WIDTH IN CLOCKS TIME @ 25 MHz
0 0 0 2 2 80 ns
0 0 1 3 (default) 4 160 ns
0 1 0 4 8 320 ns
0 1 1 5 12 480 ns
1 0 0 6 16 640 ns
1 0 1 7 20 800 ns
1 1 0 8 24 960 ns
1 1 1 9 28 1120 ns
STROBE WIDTH
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DS80C320/DS80C323
DUAL DATA POINTER
Data memory block moves can be accelera ted using the Dual Data Pointer (DPTR). The standard 8032
DPTR is a 16-bit value that is used to address off-chip data RAM or peripherals. In the
DS80C320/DS80C323, the standard 16-bit data pointer is called DPTR0 and is located at SFR addresses
82h and 83h. These are the standard locations. The new DPTR is located at SFR 84h and 85h and is
called DPTR1. The DPTR Select bit (DPS) chooses the active pointer and is located at the LSB of the
SFR location 86h. No other bits in register 86h have any effect and are set to 0. The user switches
between data pointers by toggling the LSB of register 86h. The increment (INC) instruction is the fastest
way to accomplish this. All DPTR-related instructions use the currently selected DPTR for any activity.
Therefore only one instruction is required to switch from a source to a destination address. Using the
Dual-Data Pointer saves code from needing to save source and destination addresses when doing a block
move. Once loaded, the software simply switches between DPTR and 1. The relevant register locations
are as follows.
DPL 82h Low byte original DPTR
DPH 83h High byte original DPTR
DPL1 84h Low byte new DPTR
DPH1 85h High byte new DPTR
DPS 86h DPTR Select (LSB)
Sample code listed below illustrates the saving from using the dual DPTR. The example program was
original code written for an 8051 and requires a total of 1869 DS80C320/DS80C323 machine cycles. This
takes 299 µs to execute at 25 MHz. The new code using the Dual DPTR requires only 1097 machine
cycles taking 175.5 µs. The Dual DPTR saves 772 machine cycles or 123.5 µs for a 64-byte block move.
Since each pass through the loop saves 12 machine cycles when compared to the single DPTR approach,
larger blocks gain more efficiency using this feature.
64- BYTE BLOCK MOVE W ITHOUT DUAL DATA POINTER
; SH and SL are high and low byte source address.
; DH and DL are high and low byte of destination address.
# CYCLES
MOV R5, #64d ; NUMBER OF BYTES TO MOVE 2
MOV DPTR, #SHSL ; LOAD SOURCE ADDRESS 3
MOV R1, #SL ; SAVE LOW BYTE OF SOURCE 2
MOV R2, #SH ; SAVE HIGH BYTE OF SOURCE 2
MOV R3, #DL ; SAVE LOW BYTE OF DESTINATION 2
MOV R4, #DH ; SAVE HIGH BYTE OF DESTINATION 2
MOVE:
; THIS LOOP IS PERFORMED THE NUMBER OF TIMES LOADED INTO R5, IN THIS EXAMPLE 64
MOVX A, @DPTR ; READ SOURCE DATA BYTE 2
MOV R1, DPL ; SAVE NEW SOURCE POINTER 2
MOV R2, DPH ; 2
MOV DPL, R3 ; LOAD NEW DESTINATION 2
MOV DPH, R4 ; 2
MOVX @DPTR, A ; WRITE DATA TO DESTINATION 2
INC DPTR ; NEXT DESTINATION ADDRESS 3
MOV R3, DPL ; SAVE NEW DESTINATION POINTER 2
MOV R4, DPH ; 2
MOV DPL, R1 ; GET NEW SOURCE POINTER 2
MOV DPH, R2 ; 2
INC DPTR ; NEXT SOURCE ADDRESS 3
DJNZ R5, MOVE ; FINISHED WITH TABLE? 3
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DS80C320/DS80C323
64- BYTE BLOCK MOVE WITH DUAL DATA POINTER
; SH and SL are high and low byte source address.
; DH and DL are high and low byte of destination address.
; DPS is the data pointer select. Reset condition is DPS=0, DPTR0 is selected.
# CYCLES
EQU DPS, #86h ; TELL ASSEMBLER ABOUT DPS
MOV R5, #64 ; NUMBER OF BYTES TO MOVE 2
MOV DPTR, #DHDL ; LOAD DESTINATION ADDRESS 3
INC DPS ; CHANGE ACTIVE DPTR 2
MOV DPTR, #SHSL ; LOAD SOURCE ADDRESS 2
MOVE:
; THIS LOOP IS PERFORMED THE NUMBER OF TIMES LOADED INTO R5, IN THIS EXAMPLE 64
MOVX A, @DPTR ; READ SOURCE DATA BYTE 2
INC DPS ; CHANGE DPTR TO DESTINATION 2
MOVX @DPTR, A ; WRITE DATA TO DESTINATION 2
INC DPTR ; NEXT DESTINATION ADDRESS 3
INC DPS ; CHANGE DATA POINTER TO SOURCE 2
INC DPTR ; NEXT SOURCE ADDRESS 3
DJNZ R5, MOVE ; FINISHED WITH TABLE? 3
PERIPHERAL OVERVIEW
Peripherals in the DS80C320/DS80C323 are accessed using Special Function Registers (SFRs). The
device provides several of the most commonly needed peripheral functions in microcomputer-based
systems. These functions are new to the 80C32 family and include a second serial port, Power-fail Reset,
Power-fail Interrupt, and a programmable Watchdog Timer. These are described below, and more details
are available in the High-Speed Microcontroller User’s Guide.
SERIAL PORTS
The DS80C320/DS80C323 provides a serial port (UART) that is identical to the 80C32. Many
applications require serial communication with multiple devices. Therefore a second hardware serial port
is provided that is a full duplicate of the standard one. It optionally uses pins P1.2 (RXD1) and P1.3
(TXD1). This port has duplicate control functions included in new SFR locations. The second serial port
operates in a comparable manner with the first. Both can operate simultaneously but can be at different
baud rates.
The second serial port has similar control registers (SCON1 at C0h, SBUF1 at C1h) to the original. One
difference is that for timer-based baud rates, the original serial port can use Timer 1 or Timer 2 to
generate baud rates. This is selected via SFR bits. The new serial port can only use Timer 1.
TIMER RATE CONTROL
One important difference exists between the DS80C320/DS80C323 and 80C32 regarding timers. The
original 80C32 used a 12 clock per cycle scheme for timers and consequently for some serial baud rates
(depending on the mode). The DS80C320/DS80C323 architecture normally runs using 4 clocks per cycle.
However, in the area of timers, it will default to a 12-clock per cycle scheme on a reset. This allows
existing code with real-time dependencies such as baud rates to operate properly. If an application needs
higher speed timers or serial baud rates, t he timers can be set to run at the 4-clock rate.
The Clock Control register (CKCON - 8Eh) determines these timer speeds. When the relevant CKCON
bit is a logic 1, the device uses 4 clocks per cycle to generate timer speeds. When the control bit is set to a
0, the device uses 12 clocks for timer speeds. The reset condition is a 0. CKCON.5 selects the speed of
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