Dallas Semiconductor DS2506S, DS2506 Datasheet
www.dalsemi.com
C
DS2506
64-kbit Add-Only Memory
FEATURES
65536 bits Electrically Programmable Read
Only Memory (EPROM) communicates with
the economy of one signal plus ground
Unique, factory-lasered and tested 64-bit
registration number (8-bit family code +
48-bit serial number + 8-bit CRC tester)
assures absolute traceability because no two
parts are alike
Built-in multidrop controller ensures
compatibility with other MicroLAN products
EPROM partitioned into two hundred fifty six
256-bit pages for randomly accessing
packetized data records
Each memory page can be permanently write-
protected to prevent tampering
Device is an “add only” memory where
additional data can be programmed into
EPROM without disturbing existing data
Architecture allows software to patch data by
superseding an old page in favor of a newly
programmed page
Reduces control, address, data, power, and
programming signals to a single data pin
Directly connects to a single port pin of a
microprocessor and communicates at up to
16.3 kbits per second
Overdrive mode boosts communication speed
to 142 kbits per second
8-bit family code specifies DS2506
communications requirements to reader
Presence detector acknowledges when the
reader first applies voltage
Low cost PR35 or 8-pin SOIC surface mount
package
Reads over a wide voltage range of 2.8V to
6.0V from -40°C to +85°C; programs at
11.5V to 12.0V from -40°C to +50°C
PIN ASSIGNMENT
PR-35
DALLAS
DS2506
N
GND
DATA
123
Bottom View
See Mech.
Drawings Section
NC NC
DATA
GND
1
2
3
4
8-PIN SOIC
(208 mil)
ORDERING INFORMATION
DS2506 PR35 Package
DS2506S 8-Pin SOIC Package
8
7
6
5
NCNC
NC
NC
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DS2506
SILICON LABEL DESCRIPTION
The DS2506 64 kbits Add-Only Memory identifies and stores relevant information about the product to
which it is associated. This lot or product specific information can be accessed with minimal interface, for
example a single port pin of a microcontroller. The DS2506 consists of a factory-lasered registration
number that includes a unique 48-bit serial number, an 8-bit CRC, and an 8-bit Family Code (0FH) plus
64 kbits of user-programmable EPROM. The power to program and read the DS2506 is derived entirely
from the 1-Wire communication line. Data is transferred serially via the 1-Wire protocol which requires
only a single data lead and a ground return. The entire device can be programmed and then writeprotected if desired. Alternatively, the part may be programmed multiple times with new data being
appended to, but not overwriting, existing data with each subsequent programming of the device. Note:
Individual bits can be changed only from a logical 1 to a logical 0, never from a logical 0 to a logical 1. A
provision is also included for indicating that a certain page or pages of data are no longer valid and have
been replaced with new or updated data that is now residing at an alternate page address. This page
address redirection allows software to patch data and enhance the flexibility of the device as a stand-alone
database. The 48-bit serial number that is factory-lasered into each DS2506 provides a guaranteed unique
identity which allows for absolute traceability. The PR35 and SOIC packages provide a compact
enclosure that allows standard assembly equipment to handle the device easily for attachment to printed
circuit boards or wiring. Typical applications include storage of calibration constants, maintenance
records, asset tracking, product revision status and access codes.
OVERVIEW
The block diagram in Figure 1 shows the relationships between the major control and memory sections of
the DS2506. The DS2506 has three main data components: 1) 64-bit lasered ROM, 2) 65536-bits
EPROM Data Memory, and 3) 2816-bits EPROM Status Memory. The device derives its power for read
operations entirely from the 1-Wire communication line by storing energy on an internal capacitor during
periods of time when the signal line is high and continues to operate off of this “parasite” power source
during the low times of the 1-Wire line until it returns high to replenish the parasite (capacitor) supply.
During programming, 1-Wire communication occurs at normal voltage levels and then is pulsed
momentarily to the programming voltage to cause the selected EPROM bits to be programmed. The
1-Wire line must be able to provide 12 volts and 10 milliamperes to adequately program the EPROM
portions of the part. Whenever programming voltages are present on the 1-Wire line a special high
voltage detect circuit within the DS2506 generates an internal logic signal to indicate this condition. The
hierarchical structure of the 1-Wire protocol is shown in Figure 2. The bus master must first provide one
of the six ROM Function Commands, 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM, 5)
Overdrive-Skip ROM or 6) Overdrive-Match ROM. Upon completion of an Overdrive ROM command
byte executed at regular speed, the device will enter the Overdrive mode where all subsequent
communication occurs at a higher speed. These commands operate on the 64-bit lasered ROM portion of
each device and can singulate a specific device if many are present on the 1-Wire line as well as indicate
to the bus master how many and what types of devices are present. The protocol required for these ROM
Function Commands is described in Figure 8. After a ROM Function Command is successfully executed,
the memory functions that operate on the EPROM portions of the DS2506 become accessible and the bus
master may issue any one of the five Memory Function Commands specific to the DS2506 to read or
program the various data fields. The protocol for these Memory Function Commands is described in
Figure 5. All data is read and written least significant bit first.
64-BIT LASERED ROM
Each DS2506 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code.
The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits. (See Figure 3).
The 64-bit ROM and ROM Function Control section allow the DS2506 to operate as a 1-Wire device and
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DS2506
follow the 1-Wire protocol detailed in the section “1-Wire Bus System.” The memory functions required
to read and program the EPROM sections of the DS2506 are not accessible until the ROM function
protocol has been satisfied. This protocol is described in the ROM functions flow chart (Figure 8). The
1-Wire bus master must first provide one of six ROM function commands: 1) Read ROM, 2) Match
ROM, 3) Search ROM, 4) Skip ROM, 5) Overdrive-Skip ROM or 6) Overdrive-Match ROM. After a
ROM function sequence has been successfully executed, the bus master may then provide any one of the
memory function commands specific to the DS2506 (Figure 5).
The 1-Wire CRC of the lasered ROM is generated using the polynomial X8 + X5 + X4 + 1. Additional
information about the Dallas Semiconductor 1-Wire Cyclic Redundancy Check is available in the Book
of DS19xx iButton Standards. The shift register acting as the CRC accumulator is initialized to zero.
Then starting with the least significant bit of the family code, 1 bit at a time is shifted in. After the 8th bit
of the family code has been entered, then the serial number is entered. After the 48th bit of the serial
number has been entered, the shift register contains the CRC value. Shifting in the 8 bits of CRC should
return the shift register to all zeroes.
DS2506 BLOCK DIAGRAM Figure 1
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HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL Figure 2
DS2506
64-BIT LASERED ROM Figure 3
8-Bit CRC Code 48-Bit Serial Number 8-Bit Family Code (0FH)
MSB LSB MSB LSB MSB LSB
65536-BITS EPROM
The memory map in Figure 4 shows the 65536-bit EPROM section of the DS2506 which is configured as
256 pages of 32 bytes each. The 8-bit scratchpad is an additional register that acts as a buffer when
programming the memory. Data is first written to the scratchpad and then verified by reading an 16-bit
CRC from the DS2506 that confirms proper receipt of the data and address. If the buffer contents are
correct, a programming voltage should be applied and the byte of data will be written into the selected
address in memory. This process insures data integrity when programming the memory. The details for
reading and programming the 65536-bit EPROM portion of the DS2506 are given in the Memory
Function Commands section.
EPROM STATUS BYTES
In addition to the 65536 bits of data memory the DS2506 provides 2816 bits of Status Memory accessible
with separate commands.
The EPROM Status Bytes can be read or programmed to indicate various conditions to the software
interrogating the DS2506. The first 32 bytes of the EPROM Status Memory (addresses 000 to 01FH)
contain the Write Protect Page bits which inhibit programming of the corresponding page in the 65536-bit
main memory area if the appropriate write protection bit is programmed. Once a bit has been
programmed in the Write Protect Page section of the Status Memory, the entire 32 byte page that
corresponds to that bit can no longer be altered but may still be read.
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DS2506
The next 32 bytes of the EPROM Status Memory (addresses 020 to 03FH) contain the Write Protect bits
which inhibit altering the Page Address Redirection Byte corresponding to each page in the 65536-bit
main memory area.
The following 32 bytes within the EPROM Status Memory (addresses 040 to 05FH) are reserved for use
by the iButton operating software TMEX. Their purpose is to indicate which memory pages are already in
use. Originally, all of these bits are unprogrammed, indicating that the device does not store any data. As
soon as data is written to any page of the device under control of TMEX, the bit inside this bitmap
corresponding to that page will be programmed to 0, marking this page as used. These bits are application
flags only and have no impact on the internal logic of the DS2506.
The next 256 bytes of the EPROM Status Memory (addresses 100H to 1FFH) contain the Page Address
Redirection Bytes which indicate if one or more of the pages of data in the 65536-bit EPROM section
have been invalidated by software and redirected to the page address contained in the appropriate
redirection byte. The hardware of the DS2506 makes no decisions based on the contents of the Page
Address Redirection Bytes. Since with EPROM technology bits can only be changed from a logical 1 to
a logical 0 by programming, it is not possible to simply rewrite a page if the data requires changing or
updating. But with space permitting, an entire page of data can be redirected to another page within the
DS2506. Under TMEX a page is redirected by writing the one’s complement of the new page address
into the Page Address Redirection Byte that corresponds to the original (replaced) page. This architecture
allows the user’s software to make a “data patch” to the EPROM by indicating that a particular page or
pages should be replaced with those indicated in the Page Address Redirection Bytes. To leave an
authentic audit trail of data patches, it is recommended to also program the write protect bit of the Page
Address Redirection Byte, after the page redirection is programmed. Without this protection, it is still
possible to modify the Page Address Redirection Byte, making it point to a different memory page than
the true one.
If a Page Address Redirection Byte has a FFH value, the data in the main memory that corresponds to
that page is valid. If a Page Address Redirection Byte has some other hex value than FFH, the data in the
page corresponding to that redirection byte is invalid. According to the TMEX definitions the valid data
can now be found at the one’s complement of the page address indicated by the hex value stored in the
associated Page Address Redirection Byte. A value of FDH in the redirection byte for page 1, for
example, would indicate that the updated data is now in page 2. The status memory is programmed
similarly to the data memory. Details for reading and programming the EPROM status memory portion of
the DS2506 are given in the Memory Function Commands section.
The Status Memory address range of the DS2506 extends from 000 to 1FFH. The memory locations 60H
to 0FFH and 200H and higher are physically not implemented. Reading these locations will usually
result in FFH bytes. Attempts to write to these locations will be ignored.
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DS2506 MEMORY MAP Figure 4
STATUS MEMORY MAP
DS2506
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DS2506
MEMORY FUNCTION COMMANDS
The “Memory Function Flow Chart” (Figure 5) describes the protocols necessary for accessing the
various data fields within the DS2506. The Memory Function Control section, 8-bit scratchpad, and the
Program Voltage Detect circuit combine to interpret the commands issued by the bus master and create
the correct control signals within the device. A three byte protocol is issued by the bus master. It is
comprised of a command byte to determine the type of operation and two address bytes to determine the
specific starting byte location within a data field. The command byte indicates if the device is to be read
or written. Writing data involves not only issuing the correct command sequence but also providing a
12-volt programming voltage at the appropriate times. To execute a write sequence, a byte of data is first
loaded into the scratchpad and then programmed into the selected address. Write sequences always occur
a byte at a time. To execute a read sequence, the starting address is issued by the bus master and data is
read from the part beginning at that initial location and continuing to the end of the selected data field or
until a reset sequence is issued. All bits transferred to the DS2506 and received back by the bus master
are sent least significant bit first.
READ MEMORY [F0H]
The Read Memory command is used to read data from the 65536 bits EPROM data field. The bus master
follows the command byte with a two byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates a
starting byte location within the data field. With every subsequent read data time slot the bus master
receives data from the DS2506 starting at the initial address and continuing until the end of the 65536 bits
data field is reached or until a Reset Pulse is issued. If reading occurs through the end of memory space,
the bus master may issue sixteen additional read time slots and the DS2506 will respond with a 16-bit
CRC of the command, address bytes and all data bytes read from the initial starting byte through the last
byte of memory. This CRC is the result of clearing the CRC generator and then shifting in the command
byte followed by the two address bytes and the data bytes beginning at the first addressed memory
location and continuing through to the last byte of the EPROM data memory. After the CRC is received
by the bus master, any subsequent read time slots will appear as logical 1s until a Reset Pulse is issued.
Any reads ended by a Reset Pulse prior to reaching the end of memory will not have the 16-bit CRC
available.
Typically a 16-bit CRC would be stored with each page of data to insure rapid, error-free data transfers
that eliminate having to read a page multiple times to determine if the received data is correct or not. (See
Book of DS19xx iButton Standards, Chapter 7 for the recommended file structure to be used with the 1Wire environment). If CRC values are imbedded within the data, a Reset Pulse may be issued at the end
of memory space during a Read Memory command.
READ STATUS [AAH]
The Read Status command is used to read data from the EPROM Status data field. The bus master
follows the command byte with a two byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates a
starting byte location within the data field. With every subsequent read data time slot the bus master
receives data from the DS2506 starting at the supplied address and continuing until the end of an eight
byte page of the EPROM Status data field is reached. At that point the bus master will receive a 16-bit
CRC of the command byte, address bytes and status data bytes. This CRC is computed by the DS2506
and read back by the bus master to check if the command word, starting address and data were received
correctly. If the CRC read by the bus master is incorrect, a Reset Pulse must be issued and the entire
sequence must be repeated.
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DS2506
Note that the initial pass through the Read Status flow chart will generate a 16-bit CRC value that is the
result of clearing the CRC generator and then shifting in the command byte followed by the two address
bytes, and finally the data bytes beginning at the first addressed memory location and continuing through
to the last byte of the addressed EPROM Status data page. The last byte of a Status data page always has
an ending address of xx7 or xxFH. Subsequent passes through the Read Status flow chart will generate a
16-bit CRC that is the result of clearing the CRC generator and then shifting in the new data bytes starting
at the first byte of the next page of the EPROM Status data field.
This feature is provided since the EPROM Status information may change over time making it impossible
to program the data once and include an accompanying CRC that will always be valid. Therefore, the
Read Status command supplies a 16-bit CRC that is based on and always is consistent with the current
data stored in the EPROM Status data field.
MEMORY FUNCTION FLOW CHART Figure 5
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