Dallas Semiconductor DS2450S Datasheet

DS2450

1-Wire

Quad A/D Converter

www.dalsemi.com

VNCDATA

GND

AIN-A

AIN-B

AIN-C

AIN-D

234

8

7

651

TM

FEATURES

§ Four high-impedance inputs to measure

analog voltages over the 1-Wire bus

§ User programmable input range (2.56V,

5.12V), resolution (1 to 16 bits) and alarm
thresholds

§ 5V, single supply operation

§ Very low power: 2.5 mW active, 25 µW idle

§ Built-in multidrop controller allows multiple

DS2450’s to be identified and operated on a
common 1-Wire bus

§ Responds to Conditional Search if the analog

voltage crosses the alarm thresholds

§ Channels not used as analog input can serve

as open drain digital outputs for closed-loop
control

§ Directly connects to a single port pin of a

microprocessor and communicates at up to

16.3k bits per second

§ Overdrive mode boosts communication speed

to 142k bits per second

§ On-chip 16-bit CRC-generator for

safeguarding data transfers

§ Unique, factory-lasered and tested 64-bit

registration number (8-bit family code + 48­bit serial number 8-bit CRC tester) assures
absolute traceability because no two parts are
alike

§ 8-bit family code specifies device

communication requirements to bus master

§ Operating temperature range from -40°C to
+85°C

§ Compact, low cost 8-pin SOIC surface mount
package

PIN ASSIGNMENT

8-PIN SOIC (208 MIL)

PIN DESCRIPTION

V

CC

NC Do Not Connect
DATA 1-Wire Bus
GND Ground
AIN-A Analog Input A
AIN-B Analog Input B
AIN-C Analog Input C
AIN-D Analog Input D

4.5 to 5.5 Volts

ORDERING INFORMATION

DS2450S 8-pin SOIC

DESCRIPTION

The DS2450 1-Wire Quad A/D Converter is based on a successive-approximation analog to digital
converter with a four to one analog multiplexer. Each input channel has its own register set to store the
input voltage range, resolution, and alarm threshold values as well as flags to enable participation of the
device in the conditional search if the input voltage leaves the specified range. Two alarm flags for each
channel indicate if the voltage measured was too high or too low without requiring the bus master to do

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DS2450

the comparison. Each A/D conversion is initiated by the bus master. A channel not used as analog input
can serve as a digital open-drain output. After disabling the input the bus master can directly switch on or
off the open-drain transistor at the selected channel. All device settings are stored in SRAM and kept
non-volatile while the device gets power either through the 1-Wire bus or through its VCC pin. After
powering up a power-on reset flag signals the bus master the need to restore the device settings before the
regular operation can resume. All device registers and conversion read-out registers are organized as
three 8-byte memory pages similar to the Status Memory of a DS2505/6 device. An on-chip CRC16
generator protects the communication against transmission errors when reading through the end of a
memory page as well as when writing individual bytes.

OVERVIEW

The block diagram in Figure 1 shows the major function blocks of the device. The DS2450 contains a
factory-lasered registration number that includes a unique 48-bit serial number, an 8-bit CRC, and an 8­bit family code (20H). The 64-bit ROM portion of the DS2450 not only creates an absolutely unique
electronic identification for the device itself but also is a means to locate and address the device in order
to exercise its control functions.

The device gets its power either from the 1-Wire bus or through its VCC pin. Without a VCC supply the
device stores energy on an internal capacitor during periods where the signal line is high and continues to
operate off of this “parasite” power source during the low times of the 1-Wire line until it returns to high
to replenish the parasite (capacitor) supply. This, however, provides sufficient energy only for
communication. To perform an A/D conversion a strong pullup of the 1-Wire bus to 5V or a VCC supply
is required.

DS2450 BLOCK DIAGRAM Figure 1

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HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL Figure 2

DS2450

The DS2450 uses the standard Dallas Semiconductor 1-Wire protocol for data transfers. Communication
to and from the DS2450 requires a single bi-directional line that is typically a port pin of a
microcontroller. The hierarchical structure of the 1-Wire protocol is shown in Figure 2. The 1-Wire bus
master must first provide one of the seven ROM Function Commands, 1) Read ROM, 2) Match ROM, 3)
Search ROM, 4) Conditional Search ROM, 5) Skip ROM, 6) Overdrive-Skip ROM or 7) Overdrive­Match ROM. Upon completion of an overdrive ROM command byte executed at standard speed, the
device will enter Overdrive mode where all subsequent communication occurs at a higher speed. The
protocol required for these ROM function commands is described in Figure 9. After a ROM function
command is successfully executed, the memory and control functions become accessible and the master
may provide any one of the available commands. The protocol for these commands is described in Figure

6. All data is read and written least significant bit first.

64-BIT LASERED ROM

Each DS2450 contains a unique ROM code that is 64 bits long. The first eight bits are a 1-Wire family
code. The next 48 bits are a unique serial number. The last eight bits are a CRC of the first 56 bits. (See
Figure 3.) The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and
XOR gates as shown in Figure 4. The polynomial is X8 + X5 + X4 + 1. Additional information about the
Dallas 1-Wire Cyclic Redundancy Check is available in the Book of DS19xx iButtonTM Standards. The
shift register acting as the CRC accumulator is initialized to zero. Then starting with the least significant
bit of the family code, one bit at a time is shifted in. After the 8th bit of the family code has been entered,
then the serial number is entered. After the 48th bit of the serial number has been entered, the shift
register contains the CRC value. Shifting in the eight bits of CRC should return the shift register to all
zeros.

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DS2450

64-BIT LASERED ROM Figure 3

1-WIRE CRC-GENERATOR Figure 4

DEVICE REGISTERS

All registers of the DS2450 are mapped into a linear memory range of 24 adjacent bytes organized as
three 8-byte pages. The first page, called conversion read-out, contains the memory area where the chip­internal logic places the results of a conversion for the bus master to read. Starting with channel A at the
lowest address, each channel has an area of 16 bits assigned for the conversion result, as shown in Figure
5a. The power-on default for the conversion read-out registers is all zeros. Regardless of the resolution
requested, the most significant bit of the conversion is always at the same bit position. If less than 16-bit
resolution is requested, the least significant bits of the conversion result will be filled with zeros in order
to always generate a 16-bit result. For applications that require less than four analog inputs, one should
start using input D for the first channel, input C for the second one, etc. The advantage is that when
reading the conversion results one reaches the end of the page and with it the CRC16 sooner and
minimizes the traffic on the 1-Wire bus. For more details on reading please refer to the Read Memory
command description.

MEMORY MAP PAGE 0, CONVERSION READ-OUT Figure 5a

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

00
01
02
03
04
05
06
07

The control and status information for all channels is located in memory page 1 (Figure 5b). As for the
conversion read-out, each channel has assigned 16 bits. The four least significant bits, called RC3 to
RC0, are an unsigned binary number that represents the number of bits to be converted. A code of 1111
(15 decimal) will generate a 15-bit result. For a full 16-bit conversion the code number needs to be 0000.
The next two bits beyond RC3 will always read 0. They have no function and cannot be changed to 1s.

A A A A A A A LSBIT A

MSBIT A A A A A A A A

B B B B B B B LSBIT B

MSBIT B B B B B B B B

C C C C C C C LSBIT C

MSBIT C C C C C C C C

D D D D D D D LSBIT D

MSBIT D D D D D D D D

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DS2450

The next bits, OC (output control) and OE (enable output) control the alternate use of a channel as output.
For normal operation as analog input the OE bit of a channel needs to be 0, rendering the OC bit to a
don’t care. With OE set to 1, a 0 for OC will make the channel’s output transistor conducting, a 1 for OC
will switch the transistor off. With a pullup resistor to a positive voltage, for example, the OC bit will
directly translate into the voltage equivalent of its logic state. Enabling the output does not disable the
analog input. Conversions remain possible, but will result in values close to 0 if the transistor is
conducting.

The IR bit in the second byte of a channel’s control and status memory selects the input voltage range.
With IR set to 0, the highest possible conversion result is reached at 2.55V. Setting IR to 1 requires an
input voltage of 5.10V for the same result. The next bit beyond IR has no function. It will always read 0
and cannot be changed to 1.

The next two bits, AEL alarm enable low and AEH alarm enable high, control whether the device will
respond to the Conditional Search command (see ROM Functions) if a conversion results in a value
higher (AEH) than or lower (AEL) than the channel’s alarm threshold voltage as specified in the alarm
settings. The alarm flags AFL (low) and AFH (high) tell the bus master whether the channel’s input
voltage was beyond the low or high threshold at the latest conversion. These flags are cleared
automatically if a new conversion reveals a non-alarming value. They can alternatively be written to 0 by
the bus master without a conversion.

The next bit of a channel’s control and status memory always reads 0 and cannot be changed to 1. The
POR bit (power on reset) is automatically set to 1 as the device performs a power-on reset cycle. As long
as this bit is set the device will always respond to the Conditional Search command in order to notify the
bus master that the control and threshold data is no longer valid. After powering-up the POR bit needs to
be written to 0 by the bus master. This may be done together with restoring the control and threshold
data. It is possible for the bus master to write the POR bit to a 1. This will make the device participate in
the conditional search but will not generate a reset cycle. Since the POR bit is related to the device and
not channel-specific the value written with the most recent setting of an input range or alarm enable
applies. The power-on default setting for the control/status data is 08h for the first and 8Ch for the
second byte of each channel.

MEMORY MAP PAGE 1, CONTROL/STATUS DATA Figure 5b

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

08

09
0A
0B
0C
0D
0E

0F

OE-A OC-A 0 0 RC3-A RC2-A RC1-A RC0-A

POR 0 AFH-A AFL-A AEH-A AEL-A 0 IR-A

OE-B OC-B 0 0 RC3-B RC2-B RC1-B RC0-B

POR 0 AFH-B AFL-B AEH-B AEL-B 0 IR-B

OE-C OC-C 0 0 RC3-C RC2-C RC1-C RC0-C

POR 0 AFH-C AFL-C AEH-C AEL-C 0 IR-C

OE-D OC-D 0 0 RC3-D RC2-D RC1-D RC0-D

POR 0 AFH-D AFL-D AEH-D AEL-D 0 IR-D

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DS2450

MEMORY MAP PAGE 2, ALARM SETTINGS Figure 5c

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

10

11

12

13

14

15

16

17

The registers for the alarm threshold voltages of each channel are located in memory page 2 with the low
threshold being at the lower address (Figure 5c). The power-on default thresholds are 00h for low alarm
and FFh for high alarm. The alarm settings are always eight bits. For a resolution higher or equal to
eight bits the alarm flag will be set if the eight most significant bits of the conversion result yield a
number higher than stored in the high alarm register (AFH) or lower than stored in the low alarm register
(AFL). For a resolution lower than eight bits the least significant bits of the alarm registers are ignored.

There is a fourth memory page in the address range of 18 to 1F used during calibration at the factory.
This memory page is accessible to the user through the Read Memory and Write Memory commands.
Changing the data of this page arbitrarily will de-calibrate the A/D converter or make the device
nonfunctional until it undergoes a power-on reset. If the device is VCC powered the analog circuitry
must be kept permanently active by writing a value of 40 hex to memory address 1C after power-up.
This also eliminates the offset time otherwise needed with each CONVERT command. See the
description of the CONVERT command for details.

MSBL-A A A A A A A LSBL-A

MSBH-A A A A A A A LSBH-A

MSBL-B B B B B B B LSBL-B

MSBH-B B B B B B B LSBH-B

MSBL-C C C C C C C LSBL-C
MSBH-C C C C C C C LSBH-C
MSBL-D D D D D D D LSBL-D
MSBH-D D D D D D D LSBH-D

FUNCTION COMMANDS

The Function Command Flow Chart (Figure 6) describes the protocols necessary for accessing the device
registers. Since the memory map of the DS2450 is small compared to the 16-bit addressing capabilities
the 11 most significant bits of the address will be forced to 0 before they enter the CRC-generator. The
communication between master and DS2450 takes place either at regular speed (default, OD = 0) or at
Overdrive Speed (OD = 1). If not explicitly set into Overdrive mode the device assumes regular speed.

READ MEMORY [AAH]

The Read Memory command is used to read conversion results, control/status data and alarm settings.
The bus master follows the command byte with a two byte address (TA1=(T7:T0), TA2=(T15:T8)) that
indicates a starting byte location within the memory map. With every subsequent read data time slot the
bus master receives data from the DS2450 starting at the supplied address and continuing until the end of
an eight-byte page is reached. At that point the bus master will receive a 16-bit CRC of the command
byte, address bytes and data bytes. This CRC is computed by the DS2450 and read back by the bus
master to check if the command word, starting address and data were received correctly. If the CRC read
by the bus master is incorrect, a Reset Pulse must be issued and the entire sequence must be repeated.

Note that the initial pass through the Read Memory flow chart will generate a 16-bit CRC value that is the
result of clearing the CRC-generator and then shifting in the command byte followed by the two address
bytes, and finally the data bytes beginning at the first addressed memory location and continuing through
to the last byte of the addressed page. Subsequent passes through the Read Memory flow chart will
generate a 16-bit CRC that is the result of clearing the CRC-generator and then shifting in the new data
bytes starting at the first byte of the next page.

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DS2450

WRITE MEMORY [55H]

The Write Memory command is used to write to memory pages 1 and 2 in order to set the channel­specific control data and alarm thresholds. The bus master will follow the command byte with a two byte
starting address (TA1=(T7:T0), TA2=(T15:T8)) and a data byte of (D7:D0). A 16-bit CRC of the
command byte, address bytes, and data byte is computed by the DS2450 and read back by the bus master
to confirm that the correct command word, starting address, and data byte were received. Now the
DS2450 copies the data byte to the specified memory location. With the next eight time slots the bus
master receives a copy of the same byte but read from memory for verification. If the verification fails, a
Reset Pulse should be issued and the current byte address should be written again.

If the bus master does not issue a Reset Pulse and the end of memory was not yet reached, the DS2450
will automatically increment its address counter to address the next memory location. The new two-byte
address will also be loaded into the 16-bit CRC-generator as a starting value. The bus master will send
the next byte using eight write time slots. As the DS2450 receives this byte it also shifts it into the CRC­generator and the result is a 16-bit CRC of the new data byte and the new address. With the next sixteen
read time slots the bus master will read this 16-bit CRC from the DS2450 to verify that the address
incremented properly and the data byte was received correctly. If the CRC is incorrect, a Reset Pulse
should be issued in order to repeat the Write Memory command sequence.

Note that the initial pass through the Write Memory flow chart will generate a 16-bit CRC value that is
the result of shifting the command byte into the CRC-generator, followed by the two address bytes, and
finally the data byte. Subsequent passes through the Write Memory flow chart due to the DS2450
automatically incrementing its address counter will generate a 16-bit CRC that is the result of loading (not
shifting) the new (incremented) address into the CRC-generator and then shifting in the new data byte.

The decision to continue after having received a bad CRC or if the verification fails is made entirely by
the bus master. Write access to the conversion read-out registers is not possible. If a write attempt is
made to a page 0 address the device will follow the Write Memory flow chart correctly but the
verification of the data byte read back from memory will usually fail. The Write Memory command
sequence can be ended at any point by issuing a Reset Pulse.

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FUNCTION COMMAND FLOW CHART Figure 6

DS2450

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