Dallas Semiconductor DS2407P, DS2407 Datasheet
DS2407
DS2407
Dual Addressable Switch Plus
1K–Bit Memory
FEATURES
• Open drain PIO pins are controlled and their logic
level can be determined over 1–Wire
closed–loop control
TM
bus for
• Dual Channel operation (TSOC package)
• PIO pin channel A sink capability of 50 mA at 0.4V with
soft turn–on; channel B 8 mA at 0.4V
• Maximum operating voltage of 13V at PIO–A, 6.5V at
PIO–B
• 1024 bits user–programmable OTP EPROM
• 7 bytes of user–programmable status memory to con-
trol the device
• Multiple DS2407s can be identified on a common
1–Wire bus and be turned on or off independently of
other devices on the bus
• Unique, factory–lasered and tested 64–bit registra-
tion number (8–bit family code + 48–bit serial number
+ 8–bit CRC tester) assures error–free selection and
absolute identity because no two parts are alike
• On–chip CRC16 generator allows detection of data
transfer errors
• Built–in multidrop controller ensures compatibility
with other MicroLAN
TM
products
• Reduces control, address, data, programming and
power to a single data pin
• Directly connects to a single port pin of a microproces-
sor and communicates at up to 16.3k bits/s
• Low cost TO–92 or 6–pin TSOC surface mount
package
• 1–Wire communication operates over a wide voltage
range of 2.8V to 6.0V from –40°C to +85°C
• Supports Conditional Search with user–program-
mable condition
• V
bondout for optional external supply to the device
CC
(TSOC package only)
• Hidden Mode; the device will respond only to a Match
ROM command or a Conditional Search when in this
mode.
PIN ASSIGNMENT
TO–92
DALLAS
DS2407
123
321
BOTTOM VIEW
See Mech. Drawings
Section
See Mech. Drawings
PIN DESCRIPTION
TO–92 TSOC
Pin 1 Ground Ground
Pin 2 Data Data
Pin 3 PIO–A PIO–A
Pin 4 –––– V
Pin 5 –––– NC
Pin 6 –––– PIO–B
DATA
1–WIRE
PROTOCOL
CC
PIO–A
TSOC PACKAGE
6
1
5
2
4
3
TOP VIEW
3.7 X 4.0 X 1.5 mm
SIDE VIEW
Section
PIO–B
012099 1/31
DS2407
ORDERING INFORMATION
DS2407 TO–92 package
DS2407P 6–pin TSOC package
DS2407T Tape & Reel version of DS2407
DS2407V Tape & Reel version of DS2407P
DS2407X Chip Scale Pkg., Tape & Reel
ADDRESSABLE SWITCHTM DESCRIPTION
The DS2407 Dual Addressable Switch Plus Memory is
a pair of open drain N–channel transistors that can be
turned on or off via the 1–Wire bus. Alternatively, either
open drain output can serve as a logic input that can be
monitored via the same 1–Wire bus. In addition, the
device has 1024 bits of EPROM to store relevant
information such as switch function, physical location,
etc. The device is addressed by matching its individual
64–bit factory–lasered registration number. The 64–bit
number consists of an 8–bit family code, a unique 48–bit
serial number, and an 8–bit cyclic redundancy check.
Communication with the DS2407 follows the standard
Dallas Semiconductor 1–Wire protocol and can be
accomplished with a single port pin of a microcontroller.
Multiple DS2407 devices can reside on a common
1–Wire bus creating a MicroLAN. The network controller circuitry is embedded within the chip including a
search algorithm to determine the identity of each
DS2407 on the network. The open drain outputs (PIO
pins) for each DS2407 on the MicroLAN can be independently switched on or off whether there is one or
many devices sharing the same 1–Wire bus. The logic
level of the PIO pins for each device on the MicroLAN
can also be individually sensed and reported to the bus
master. The device also supports a Conditional Search
command to identify and access devices that qualify for
certain user–specified conditions. Qualification may be
the status of a PIO–pin, the state of the output transistor
or a latched activity flag.
OVERVIEW
The DS2407 Dual Addressable Switch Plus Memory
provides a means for assigning an electronically readable identification to a particular node or location with
additional control capability provided by two open–drain
N–channel MOSFETs that can be remotely switched
and sensed via communication over the 1–Wire bus
(Figure 1). The DS2407 contains a factory–lasered registration number that includes a unique 48–bit serial
number, an 8–bit CRC, and an 8–bit family code (12h).
The 64–bit ROM portion of the DS2407 not only creates
an absolutely unique electronic identification for the
device itself but also is a means to locate and obtain or
change the state of the switches that are associated
with the 64–bit ROM.
The device derives its power entirely from the 1–Wire
bus by storing energy on an internal capacitor during
periods of time when the signal line is high and continues to operate off of this “parasite” power source during
the low times of the 1–Wire line until it returns high to
replenish the parasite (capacitor) supply. For applications in feeder–networks where the low–times of the
1–Wire line may be very long, the V
pin may be con-
CC
nected to an external voltage supply to operate the
device.
The DS2407 uses the standard Dallas Semiconductor
1–Wire protocol for data transfers (Figure 2), with all
data being read and written least significant bit first.
Communication to and from the DS2407 requires a
single bi–directional line that is typically a port pin of a
microcontroller. The 1–Wire bus master (microcontroller) must first issue one of five ROM function commands: 1) Read ROM, 2) Match ROM, 3) Search ROM,
4) Skip ROM, or 5) Conditional Search ROM. These
commands operate on the 64–bit lasered ROM portion
of each device and can singulate a specific device if
many are present on the 1–Wire line as well as indicate
to the bus master how many and what type of each
device is present. After a ROM function command is
successfully executed, the open–drain outputs can be
switched or sensed, or the contents of the memory can
be read or written via the 1–Wire bus. Writing the 1024
bits of data memory or writing to the EPROM sections of
the status memory requires a 12V programming pulse.
When programming the DS2407, only EPROM–based
devices are allowed to be present on the 1–Wire line.
012099 2/31
DS2407
64–BIT LASERED ROM
Each DS2407 contains a unique ROM code that is 64
bits long. The first eight bits are a 1–Wire family code.
The next 48 bits are a unique serial number. The last
eight bits are a CRC of the first 56 bits. (See Figure 3.)
The 1–Wire CRC of the lasered ROM is generated using
the polynomial X
about the Dallas Semiconductor 1–Wire Cyclic Redundancy Check is available in the Book of DS19xx
iButton Standards. The 64–bit ROM and ROM Function
Control section allow the DS2407 to operate as a
1–Wire device and follow the 1–Wire protocol detailed in
the section “1–Wire Bus System”. The functions
required to read and write the data and status memory
of the DS2407 and to access the switches are not
accessible until the ROM function protocol has been
satisfied. This protocol is described in the ROM functions flow chart (Figure 12). The 1–Wire bus master
must first provide one of the five ROM function commands. After a ROM function sequence has been successfully executed, the bus master may then provide
any one of the memory function commands specific to
the DS2407 (Figure 6).
8
+ X5 + X4 + 1. Additional information
MEMORY
The DS2407 contains two memory sections, Data
Memory and Status Memory. The data memory consists
of 1024 bits of one–time programmable EPROM organized as 4 pages of 32 bytes each. The size of the
device’s status memory is 8 bytes. The first seven bytes
of status memory (addresses 0 to 6) are also realized as
EPROM. The eighth byte (address 7) consists of SRAM
cells which shadow the contents of address 6 each time
the device powers up. The complete memory map is
shown in Figure 4. The 8–bit scratchpad is an additional
register that acts as a buffer when writing the memory.
Data is first written to the scratchpad and then verified
by reading a 16–bit CRC from the DS2407 that confirms
proper receipt of the data and address. If the buffer contents are correct, a programming pulse should be
applied and the byte of data will be written into the
selected address in memory. This process insures data
integrity when programming the memory . The details for
reading and programming the EPROM portions of the
DS2407 are given in the Memory Function Commands
section.
012099 3/31
DS2407
DS2407 BLOCK DIAGRAM Figure 1
PARASITE POWER
INT VDD
VDD
PROGRAM
VOLTAGE
DETECT
DATA1–WIRE BUS
1–WIRE FUNCTION
CONTROL
MEMORY
FUNCTION
CONTROL
16–BIT CRC
GENERATOR
DATA MEMORY
1024–BIT EPROM
(4 PAGES OF 32 BYTES)
STATUS MEMORY
7 BYTES EPROM
1 BYTE SRAM
64–BIT LASERED
ROM
8–BIT
SCRATCHPAD
012099 4/31
PIO–A
PIO–B
PIO
CONTROL
HIERARCHICAL STRUCTURE FOR 1–WIRE PROTOCOL Figure 2
DS2407
BUS
MASTER
1–WIRE BUS
COMMAND
LEVEL:
1–WIRE ROM FUNCTION
COMMANDS (SEE FIGURE 12)
DS2407 SPECIFIC
MEMORY FUNCTION
COMMANDS
(SEE FIGURE 6)
DS2407
AVAILABLE
COMMANDS:
READ ROM
MATCH ROM
SEARCH ROM
SKIP ROM
CONDITIONAL 64–BIT ROM,
SEARCH ROM CONDITIONAL SEARCH
WRITE MEMORY 1024–BIT EPROM
WRITE STATUS
READ MEMORY
READ STATUS
EXT. READ MEMORY
CHANNEL ACCESS PIO CHANNELS
DATA FIELD
AFFECTED:
64–BIT ROM
64–BIT ROM
64–BIT ROM
N/A
SETTINGS AT ST A TUS
MEMORY LOCATION 7,
DEVICE/CHANNEL STATUS
STATUS MEMORY
1024–BIT EPROM
STATUS MEMORY
1024–BIT EPROM
OTHER
DEVICES
64–BIT LASERED ROM Figure 3
8–Bit CRC Code 48–Bit Serial Number 8–Bit Family Code (12H)
MSB LSBMSBLSB MSBLSB
012099 5/31
DS2407
DS2407 MEMORY MAP Figure 4
STARTING
ADDRESS
0000H
0020H
1K BIT
EPROM
0040H
0060H
8–BIT
SCRATCHPAD
32–BYTE FINAL STORAGE EPROM PAGE 0
32–BYTE FINAL STORAGE EPROM
32–BYTE FINAL STORAGE EPROM
32–BYTE FINAL STORAGE EPROM
PAGE 1
PAGE 2
PAGE 3
VALID DEVICE
SETTINGS (SRAM)
POWER–ON
DEFAULT SETTINGS
FACTORY
BYTE
REDIRECITON
BYTES
BIT MAP OF
USED PAGES
WRITE–PROTECT BITS
DATA MEMORY
8 BYTES
STATUS
MEMORY
DS2407 ST ATUS MEMORY MAP Figure 5
ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0 (EPROM) BM 3 BM 2 BM 1 BM 0 WP 3 WP 2 WP 1 WP 0
1 (EPROM) 1 1 1 1 1 1 Redir. 0 Redir. 0
2 (EPROM) 1 1 1 1 1 1 Redir. 1 Redir. 1
3 (EPROM) 1 1 1 1 1 1 Redir. 2 Redir. 2
4 (EPROM) 1 1 1 1 1 1 Redir. 3 Redir. 3
5 (EPROM) EPROM factory byte
6 (EPROM X Pwr–On
Status
PIO–B
7 (SRAM) Supply
Indication
(read
PIO–B
Channel
Flip–Flop
only)
Pwr–On
Status
PIO–A
PIO–A
Channel
Flip–Flop
Pwr–On
Status
CSS4
CSS4
Channel
Select
Pwr–On
Status
CSS3
CSS3
Channel
Select
Pwr–On
Status
CSS2
CSS2
Source
Select
Pwr–On
Status
CSS1
CSS1
Source
Select
Pwr–On
Status
CSS0
CSS0
Polarity
012099 6/31
DS2407
STATUS MEMORY
The Status Memory can be read or written to indicate
various conditions to the software interrogating the
DS2407. These conditions include special features for
the data memory, definition of the power–on default and
actual settings for the Conditional Search as well as the
channel flip–flops and the external power supply indication. How these functions are assigned to the bits of the
Status Memory is detailed in Figure 5. The channel flip–
flops and power supply indication are also included in
the Channel Info Byte of the Channel Access command
protocol (see Figure 6).
The first four bits of the Status Memory (address 0, bits 0
to 3) contain the Write Protect Page bits which inhibit
programming of the corresponding page in the 1024–bit
data memory area if the appropriate write protection bit
is programmed. Once a bit has been programmed in the
Write Protect Page section of the Status Memory, the
entire 32 byte page that corresponds to that bit can no
longer be altered but may still be read. The remaining 4
bits of Status Memory location 0 are reserved for use by
the iButton operating software TMEX. Their purpose is
to indicate which memory pages are already in use.
Originally, all of these bits are unprogrammed, indicating that the device does not contain any data. As soon
as data is written to any page of the device under control
of TMEX, the bit inside this bitmap corresponding to that
page will be programmed to 0, marking this page as
used. These bits are application flags only and have no
impact on the internal logic of the DS2407.
The next four bytes of the Status Memory (addresses 1
to 4) contain the Page Address Redirection Bytes which
indicate if one or more of the pages of data in the
1024–bits EPROM memory section have been invalidated by software and redirected to the page address
contained in the appropriate redirection byte. The hardware of the DS2407 makes no decisions based on the
contents of the Page Address Redirection Bytes. Since
with EPROM technology bits can only be changed from
a logical 1 to a logical 0 by programming, it is not possible to simply rewrite a page if the data requires changing or updating. But with space permitting, an entire
page of data can be redirected to another page within
the DS2407. Under TMEX, a page is redirected by writing the one’s complement of the new page address into
the Page Address Redirection Byte that corresponds to
the original (replaced) page. This architecture allows
the user’s software to make a “data patch” to the
EPROM by indicating that a particular page or pages
should be replaced with those indicated in the Page
Address Redirection Bytes.
Under TMEX, if a Page Address Redirection Byte has a
FFh value, the data in the main memory that corresponds to that page is valid. If a Page Address Redirection Byte has some other hex value than FFh, the data in
the page corresponding to that redirection byte is
invalid. According to the TMEX definitions, the valid
data will now be found at the one’s complement of the
page address indicated by the hex value stored in the
associated Page Address Redirection Byte. A value of
FDh in the redirection byte for page 1, for example,
would indicate that the updated data is now in page 2.
Since the data memory consists of four pages only , the 6
most significant bits of the redirection bytes cannot be
programmed to zeros.
Status Memory location 5 is programmed to 00h at the
factory. Status Memory location 6 contains the power–on default settings for the Conditional Search Select
(CSS0 to CSS4, bits 0 to 4) and the PIO channels. The
power–on settings become valid as they are internally
transferred by the device into Status Memory location 7
after the device has powered up and the bus master
sends a ROM Function Command byte for the first time.
The codes for the Conditional Search Settings are
detailed with the description of the Conditional Search
command later in this data sheet. If both CSS1 and
CSS2 in Status Memory Location 7 are set to zero, the
DS2407 will enter a “Hidden Mode” where it will keep its
status but only responds to Match ROM and Conditional
Search. To respond to Conditional Search the polarity
(CSS0) needs to be 1. The “Hidden Mode” can be ended
either by a power–on reset or by matching the device’s
registration number and setting CSS1 or CSS2 to 1.
012099 7/31
DS2407
The output transistors of both channels are controlled
by their channel flip–flops. These flip–flops are accessible through bit locations 5 and 6 of Status Memory
address 7 as well as through the Channel Access command. Setting a channel flip–flop to 0 will make the
associated PIO–transistor conducting or on, setting the
flip–flop to 1 will switch the transistor off. When powering
up, the output transistors of both channels are non–conducting or off. They may change their status as the
user–programmed power–on status is transferred into
Status Memory location 7. Bit 7 of Status Memory Location 7 indicates if the DS2407 is connected to an external power supply. Without external supply this read–
only bit will be 0. If the voltage applied to the V
CC
pin is
high enough to keep the device powered up, this bit will
be 1.
The Status Memory is programmed similarly to the data
memory. Details for reading and programming the status memory portion of the DS2407 are given in the
Memory Function Commands section.
MEMORY FUNCTION COMMANDS
The “Memory Function Flow Chart” (Figure 6) describes
the protocols necessary for accessing the various data
fields and PIO channels within the DS2407. The
Memory Function Control section, 8–bit scratchpad,
and the Program Voltage Detect circuit combine to interpret the commands issued by the bus master and create
the correct control signals within the device. A three–
byte protocol is issued by the bus master. It is comprised
of a command byte to determine the type of operation
and two address bytes to determine the specific starting
byte location within a data field or to supply and
exchange setup and status data when accessing the
PIO channels. The command byte indicates if the
device is to be read or written or if the PIO channels are
to be accessed. Writing data involves not only issuing
the correct command sequence but also providing a
12–volt programming voltage at the appropriate times.
To execute a write sequence, a byte of data is first
loaded into the scratchpad and then programmed into
the selected address. Write sequences always occur a
byte at a time. To execute a read sequence, the starting
address is issued by the bus master and data is read
from the part beginning at that initial location and continuing to the end of the selected data field or until a reset
sequence is issued. All bits transferred to the DS2407
and received back by the bus master are sent least significant bit first.
READ MEMORY [F0h]
The Read Memory command is used to read data from
the 1024–bit EPROM data memory field. The bus master follows the command byte with a two–byte address
(TA1=(T7:T0), TA2=(T15:T8)) that indicates a starting
byte location within the data field. Since the data
memory contains 128 bytes, T15:T8 and T7 should all
be zero. With every subsequent read data time slot the
bus master receives data from the DS2407 starting at
the initial address and continuing until the end of the
1024–bits data field is reached or until a Reset Pulse is
issued. If reading occurs through the end of memory
space, the bus master may issue sixteen additional read
time slots and the DS2407 will respond with a 16–bit
CRC of the command, address bytes and all data bytes
read from the initial starting byte through the last byte of
memory. This CRC is the result of clearing the CRC generator and then shifting in the command byte followed
by the two address bytes and the data bytes beginning
at the first addressed memory location and continuing
through to the last byte of the EPROM data memory.
After the CRC is received by the bus master, any subsequent read time slots will appear as logical 1s until a
Reset Pulse is issued. Any reads ended by a Reset
Pulse prior to reaching the end of memory will not have
the 16–bit CRC available.
Typically the software controlling the device should
store a 16–bit CRC with each page of data to insure
rapid, error–free data transfers that eliminate having to
read a page multiple times to determine if the received
data is correct or not. (See Book of DS19xx i
Standards, Chapter 7 for the recommended file structure to be used with the 1–Wire environment). If CRC
values are imbedded within the data it is unnecessary to
read the end–of–memory CRC. The Read Memory
command can be ended at any point by issuing a Reset
Pulse.
Button
012099 8/31
DS2407
EXTENDED READ MEMORY [A5h]
The Extended Read Memory command supports page
redirection when reading data from the 1024–bit
EPROM data field. One major difference between the
Extended Read Memory and the basic Read Memory
command is that the bus master receives the Redirection Byte (see description of Status Memory) first before
investing time in reading data from the addressed
memory location. This allows the bus master to quickly
decide whether to continue and access the data at the
selected starting page or to terminate and restart the
reading process at the redirected page address.
In addition to page redirection, the Extended Read
Memory command also supports “bit–oriented” applications where the user cannot store a 16–bit CRC with the
data itself. With bit–oriented applications the EPROM
information may change over time within a page boundary making it impossible to include an accompanying
CRC that will always be valid. Therefore, the Extended
Read Memory command concludes each page with the
DS2407 generating and supplying a 16–bit CRC that is
based on and therefore always consistent with the current data stored in each page of the 1024–bit EPROM
data field.
After having sent the command code of the Extended
Read Memory command, the bus master sends a two–
byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates a starting byte location within the data field. By
sending eight read data time slots, the master receives
the Redirection Byte associated with the page given by
the starting address. With the next sixteen read data
time slots, the bus master receives a 16–bit CRC of the
command byte, address bytes and the Redirection
Byte. This CRC is computed by the DS2407 and read
back by the bus master to check if the command word,
starting address and Redirection Byte were received
correctly.
If the CRC read by the bus master is incorrect, a Reset
Pulse must be issued and the entire sequence must be
repeated. If the CRC received by the bus master is correct, the bus master issues read time slots and receives
data from the DS2407 starting at the initial address and
continuing until the end of a 32–byte page is reached. At
that point the bus master will send sixteen additional
read time slots and receive a 16–bit CRC that is the
result of shifting into the CRC generator all of the data
bytes from the initial starting byte to the last byte of the
current page.
With the next 24 read data time slots the master will
receive the Redirection Byte of the next page followed
by a 16–bit CRC of the Redirection Byte. After this, data
is again read from the 1024–bits EPROM data field
starting at the beginning of the new page. This
sequence will continue until the final page and its
accompanying CRC are read by the bus master.
The Extended Read Memory command provides a
16–bit CRC at two locations within the transaction flow
chart: 1) after the Redirection Byte and 2) at the end of
each memory page. The CRC at the end of the memory
page is always the result of clearing the CRC generator
and shifting in the data bytes beginning at the first
addressed memory location of the EPROM data page
until the last byte of this page. With the initial pass
through the Extended Read Memory flow chart the
16–bit CRC value after the Redirection Byte is the result
of shifting the command byte into the cleared CRC generator, followed by the two address bytes and the
Redirection Byte. Subsequent passes through the
Extended Read Memory flow chart will generate a
16–bit CRC that is the result of clearing the CRC generator and then shifting in the Redirection Byte only. After
the 16–bit CRC of the last page is read, the bus master
will receive logical 1s from the DS2407 until a Reset
Pulse is issued. The Extended Read Memory command
sequence can be ended at any point by issuing a Reset
Pulse.
WRITING EPROM MEMORY
The DS2407 has two independent EPROM memory
fields, Data Memory and Status Memory. The function
flow for writing either field is almost identical. After the
appropriate write command has been issued, the bus
master will send a two–byte starting address
(TA1=(T7:T0), TA2=(T15:T8)) and a byte of data
(D7:D0). A 16–bit CRC of the command byte, address
bytes, and data byte is computed by the DS2407 and
read back by the bus master to confirm that the correct
command word, starting address, and data byte were
received.
012099 9/31
DS2407
If the CRC read by the bus master is incorrect, a Reset
Pulse must be issued and the entire sequence must be
repeated. If the CRC received by the bus master is correct, a programming pulse (12 volts on the 1–Wire bus
for 480 µs) is issued by the bus master. Prior to programming, the entire unprogrammed EPROM memory field
will appear as logical 1s. For each bit in the data byte
provided by the bus master that is set to a logical 0, the
corresponding bit in the selected byte of the EPROM
memory is programmed to a logical 0 after the programming pulse has been applied.
After the 480 µs programming pulse is applied and the
data line returns to the idle level (5 volts), the bus master
issues eight read time slots to verify that the appropriate
bits have been programmed. The DS2407 responds
with the data from the selected EPROM address sent
least significant bit first. This byte contains the bitwise
logical AND of all data ever written to this address. If the
EPROM byte contains 1s in bit positions where the byte
issued by the master contained 0s, a Reset Pulse
should be issued and the current byte address should
be programmed again. If the DS2407 EPROM byte contains 0s in the same bit positions as the data byte, the
programming was successful and the DS2407 will automatically increment its address counter to select the
next byte in the EPROM memory field. The new two–
byte address will also be loaded into the 16–bit CRC
generator as a starting value. The bus master will issue
the next byte of data using eight write time slots.
As the DS2407 receives this byte of data into the
scratchpad, it also shifts the data into the CRC generator that has been preloaded with the current address
and the result is a 16–bit CRC of the new data byte and
the new address. After supplying the data byte, the bus
master will read this 16–bit CRC from the DS2407 with
sixteen read time slots to confirm that the address
incremented properly and the data byte was received
correctly. If the CRC is incorrect, a Reset Pulse must be
issued and the write sequence must be restarted. If the
CRC is correct, the bus master will issue a programming
pulse and the selected byte in memory will be programmed.
Note that the initial pass through the write flow chart will
generate an 16–bit CRC value that is the result of shifting the command byte into the CRC generator, followed
by the two address bytes, and finally the data byte. Subsequent passes through the write flow chart due to the
DS2407 automatically incrementing its address counter
will generate a 16–bit CRC that is the result of loading
(not shifting) the new (incremented) address into the
CRC generator and then shifting in the new data byte.
For both of these cases, the decision to continue (to
apply a program pulse to the DS2407) is made entirely
by the bus master, since the DS2407 will not be able to
determine if the 16–bit CRC calculated by the bus master agrees with the 16–bit CRC calculated by the
DS2407. If an incorrect CRC is ignored and a program
pulse is applied by the bus master, incorrect programming could occur within the DS2407. Also note that the
DS2407 will always increment its internal address
counter after the receipt of the eight read time slots used
to confirm the programming of the selected EPROM
byte. The decision to continue is again made entirely by
the bus master. Therefore if the EPROM data byte does
not match the supplied data byte but the master continues with the write command, incorrect programming
could occur within the DS2407. The write command
sequence can be ended at any point by issuing a Reset
Pulse.
012099 10/31
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